diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/quick | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/quick')
19 files changed, 16274 insertions, 16014 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 973b187d4..01efe7b2f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,309 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357988000 # Number of ticks simulated -final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869358498000 # Number of ticks simulated +final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2868261 # Simulator instruction rate (inst/s) -host_op_rate 2868259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82489350498 # Simulator tick rate (ticks/s) -host_mem_usage 370556 # Number of bytes of host memory used -host_seconds 22.66 # Real time elapsed on the host -sim_insts 64999904 # Number of instructions simulated -sim_ops 64999904 # Number of ops (including micro ops) simulated +host_inst_rate 1825215 # Simulator instruction rate (inst/s) +host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52491614317 # Simulator tick rate (ticks/s) +host_mem_usage 318168 # Number of bytes of host memory used +host_seconds 35.61 # Real time elapsed on the host +sim_insts 65000470 # Number of instructions simulated +sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66539648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory -system.physmem.bytes_read::total 68196992 # Number of bytes read from this memory +system.physmem.bytes_read::total 68179008 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7833408 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 106432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7831360 # Number of bytes written to this memory +system.physmem.bytes_written::total 7831360 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122397 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1065297 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122365 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35594910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36471874 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4189330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4189330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4189330 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 948901 # Transaction distribution -system.membus.trans_dist::ReadResp 948901 # Transaction distribution -system.membus.trans_dist::WriteReq 14588 # Transaction distribution -system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 80845 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19618 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126515 # Transaction distribution -system.membus.trans_dist::ReadExResp 124290 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1224161 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1224161 # Request fanout histogram +system.physmem.bw_total::cpu0.data 35594910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40661204 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 999765 # number of replacements -system.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use -system.l2c.tags.total_refs 2387620 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56016.884833 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4834.504330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.028554 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 178.991920 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.573230 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5934 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48949 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31465722 # Number of tag accesses -system.l2c.tags.data_accesses 31465722 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 606953 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 626726 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 379523 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1742215 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 777631 # number of Writeback hits -system.l2c.Writeback_hits::total 777631 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111430 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168033 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 606953 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910248 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606953 # number of overall hits -system.l2c.overall_hits::cpu0.data 738156 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379523 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910248 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1665 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941273 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2175 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 5181 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11068 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124984 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1665 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066257 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1665 # number of overall misses -system.l2c.overall_misses::cpu1.data 12101 # number of overall misses -system.l2c.overall_misses::total 1066257 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 618918 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1553336 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 381188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2683488 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 777631 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777631 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2752 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5874 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976505 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778682 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976505 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.596529 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790334 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882022 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505516 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163556 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426542 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584998 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004368 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358224 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584998 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004368 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358224 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80845 # number of writebacks -system.l2c.writebacks::total 80845 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses -system.iocache.demand_misses::total 179 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 179 # number of overall misses -system.iocache.overall_misses::total 179 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758808 # DTB read hits +system.cpu0.dtb.read_hits 7758839 # DTB read hits system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740251 # DTB write hits +system.cpu0.dtb.write_hits 4740268 # DTB write hits system.cpu0.dtb.write_misses 732 # DTB write misses system.cpu0.dtb.write_acv 102 # DTB write access violations system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499059 # DTB hits +system.cpu0.dtb.data_hits 12499107 # DTB hits system.cpu0.dtb.data_misses 7887 # DTB misses system.cpu0.dtb.data_acv 254 # DTB access violations system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525726 # ITB hits +system.cpu0.itb.fetch_hits 3525737 # ITB hits system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529298 # ITB accesses +system.cpu0.itb.fetch_accesses 3529309 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -316,32 +83,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738722771 # number of cpu cycles simulated +system.cpu0.numCycles 3738723791 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 49477745 # Number of instructions committed -system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses +system.cpu0.committedInsts 49478313 # Number of instructions committed +system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124633 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46201705 # number of integer instructions +system.cpu0.num_func_calls 1124639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46202260 # number of integer instructions system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written +system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536107 # number of memory refs -system.cpu0.num_load_insts 7783754 # Number of load instructions -system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.num_mem_refs 12536155 # number of memory refs +system.cpu0.num_load_insts 7783785 # Number of load instructions +system.cpu0.num_store_insts 4752370 # Number of store instructions +system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles +system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530826 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction +system.cpu0.Branches 7530941 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction @@ -369,38 +136,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49485886 # Class of executed instruction +system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed @@ -440,7 +207,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # nu system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed @@ -449,179 +216,28 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.55% # nu system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135929 # number of callpals executed +system.cpu0.kern.callpal::total 135930 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 +system.cpu0.kern.mode_good::kernel 1173 +system.cpu0.kern.mode_good::user 1174 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram -system.iobus.trans_dist::ReadReq 7628 # Transaction distribution -system.iobus.trans_dist::ReadResp 7628 # Transaction distribution -system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 14588 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.icache.tags.replacements 618292 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits -system.cpu0.icache.overall_hits::total 48866947 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses -system.cpu0.icache.overall_misses::total 618939 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1781371 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781373 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -629,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428963 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428963 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428963 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428963 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236541 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6924 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796610 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796610 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits +system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,14 +303,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks -system.cpu0.dcache.writebacks::total 633103 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632997 # number of writebacks +system.cpu0.dcache.writebacks::total 632997 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 618298 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits +system.cpu0.icache.overall_hits::total 48867509 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses +system.cpu0.icache.overall_misses::total 618945 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831559 # DTB read hits +system.cpu1.dtb.read_hits 2831558 # DTB read hits system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 198160 # DTB read accesses @@ -702,7 +367,7 @@ system.cpu1.dtb.write_hits 2101673 # DT system.cpu1.dtb.write_misses 412 # DTB write misses system.cpu1.dtb.write_acv 55 # DTB write access violations system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933232 # DTB hits +system.cpu1.dtb.data_hits 4933231 # DTB hits system.cpu1.dtb.data_misses 3603 # DTB misses system.cpu1.dtb.data_acv 113 # DTB access violations system.cpu1.dtb.data_accesses 288779 # DTB accesses @@ -722,31 +387,31 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738296587 # number of cpu cycles simulated +system.cpu1.numCycles 3738297607 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15522159 # Number of instructions committed -system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses +system.cpu1.committedInsts 15522157 # Number of instructions committed +system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295544 # number of integer instructions +system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295542 # number of integer instructions system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written +system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961786 # number of memory refs -system.cpu1.num_load_insts 2849090 # Number of load instructions +system.cpu1.num_mem_refs 4961785 # number of memory refs +system.cpu1.num_load_insts 2849089 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles +system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214163 # Number of branches fetched +system.cpu1.Branches 2214162 # Number of branches fetched system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction @@ -775,11 +440,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525875 # Class of executed instruction +system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed @@ -793,11 +458,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -849,115 +514,67 @@ system.cpu1.kern.mode_switch_good::kernel 0.434066 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits -system.cpu1.icache.overall_hits::total 15144687 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses -system.cpu1.icache.overall_misses::total 381188 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 201756 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4587330 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4587330 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4587330 # number of overall hits -system.cpu1.dcache.overall_hits::total 4587330 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits +system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219203 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219203 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219203 # number of overall misses -system.cpu1.dcache.overall_misses::total 219203 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses +system.cpu1.dcache.overall_misses::total 219201 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses @@ -972,8 +589,392 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks -system.cpu1.dcache.writebacks::total 144528 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks +system.cpu1.dcache.writebacks::total 144531 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 380671 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits +system.cpu1.icache.overall_hits::total 15144661 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses +system.cpu1.icache.overall_misses::total 381212 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7628 # Transaction distribution +system.iobus.trans_dist::ReadResp 7628 # Transaction distribution +system.iobus.trans_dist::WriteReq 56140 # Transaction distribution +system.iobus.trans_dist::WriteResp 14588 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses +system.iocache.demand_misses::total 179 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 179 # number of overall misses +system.iocache.overall_misses::total 179 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 999763 # number of replacements +system.l2c.tags.tagsinuse 65320.982513 # Cycle average of tags in use +system.l2c.tags.total_refs 2387511 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064813 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.242188 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 56016.894287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4834.499535 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.023150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 178.992489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.573052 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48943 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31464842 # Number of tag accesses +system.l2c.tags.data_accesses 31464842 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 606959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 626686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 379549 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1742207 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 777528 # number of Writeback hits +system.l2c.Writeback_hits::total 777528 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 111433 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168036 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 606959 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910243 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606959 # number of overall hits +system.l2c.overall_hits::cpu0.data 738119 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379549 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910243 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1663 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941271 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2285 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1553296 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 381212 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2683478 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 777528 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777528 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # 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number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.596544 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004362 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505509 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426539 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.585010 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004362 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358225 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.585010 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004362 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358225 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 80845 # number of writebacks +system.l2c.writebacks::total 80845 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 948899 # Transaction distribution +system.membus.trans_dist::ReadResp 948899 # Transaction distribution +system.membus.trans_dist::WriteReq 14588 # Transaction distribution +system.membus.trans_dist::WriteResp 14588 # Transaction distribution +system.membus.trans_dist::Writeback 122365 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution +system.membus.trans_dist::ReadExReq 126515 # Transaction distribution +system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 2300222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2425204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73456146 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1265678 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1265678 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777528 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237890 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762424 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627155 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6929248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758587 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41895 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index d02473de7..608395ba3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,146 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829331993500 # Number of ticks simulated -final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332273500 # Number of ticks simulated +final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2920462 # Simulator instruction rate (inst/s) -host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88984410684 # Simulator tick rate (ticks/s) -host_mem_usage 366200 # Number of bytes of host memory used -host_seconds 20.56 # Real time elapsed on the host -sim_insts 60038469 # Number of instructions simulated -sim_ops 60038469 # Number of ops (including micro ops) simulated +host_inst_rate 1690642 # Simulator instruction rate (inst/s) +host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51512796649 # Simulator tick rate (ticks/s) +host_mem_usage 313048 # Number of bytes of host memory used +host_seconds 35.51 # Real time elapsed on the host +sim_insts 60038341 # Number of instructions simulated +sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory +system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 948404 # Transaction distribution -system.membus.trans_dist::ReadResp 948404 # Transaction distribution -system.membus.trans_dist::WriteReq 9838 # Transaction distribution -system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 74279 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116985 # Transaction distribution -system.membus.trans_dist::ReadExResp 116985 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1174168 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1174168 # Request fanout histogram -system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710423 # DTB read hits +system.cpu.dtb.read_hits 9710422 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -148,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062919 # DTB hits +system.cpu.dtb.data_hits 16062918 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974637 # ITB hits +system.cpu.itb.fetch_hits 4974648 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979643 # ITB accesses +system.cpu.itb.fetch_accesses 4979654 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -168,31 +73,31 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658670345 # number of cpu cycles simulated +system.cpu.numCycles 3658670905 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038469 # Number of instructions committed -system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses +system.cpu.committedInsts 60038341 # Number of instructions committed +system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913692 # number of integer instructions +system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913563 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115703 # number of memory refs -system.cpu.num_load_insts 9747509 # Number of load instructions +system.cpu.num_mem_refs 16115702 # number of memory refs +system.cpu.num_load_insts 9747508 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles +system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles +system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064428 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction +system.cpu.Branches 9064400 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction @@ -221,34 +126,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050307 # Class of executed instruction +system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -287,7 +192,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -296,96 +201,99 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192179 # number of callpals executed +system.cpu.kern.callpal::total 192180 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.trans_dist::ReadReq 7358 # Transaction distribution -system.iobus.trans_dist::ReadResp 7358 # Transaction distribution -system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 9838 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.cpu.icache.tags.replacements 919603 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2042728 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits +system.cpu.dcache.overall_hits::total 13655960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses +system.cpu.dcache.overall_misses::total 2026094 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks +system.cpu.dcache.writebacks::total 833501 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 919605 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -393,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130077 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits +system.cpu.icache.overall_hits::total 59129947 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses +system.cpu.icache.overall_misses::total 920232 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -428,15 +336,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992289 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992295 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy @@ -445,66 +353,66 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -514,106 +422,199 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks -system.cpu.l2cache.writebacks::total 74279 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks +system.cpu.l2cache.writebacks::total 74285 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042707 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits -system.cpu.dcache.overall_hits::total 13655981 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks -system.cpu.dcache.writebacks::total 833484 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7358 # Transaction distribution +system.iobus.trans_dist::ReadResp 7358 # Transaction distribution +system.iobus.trans_dist::WriteReq 51390 # Transaction distribution +system.iobus.trans_dist::WriteResp 9838 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 41686 # number of replacements +system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 948404 # Transaction distribution +system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::WriteReq 9838 # Transaction distribution +system.membus.trans_dist::WriteResp 9838 # Transaction distribution +system.membus.trans_dist::Writeback 115797 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116991 # Transaction distribution +system.membus.trans_dist::ReadExResp 116991 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1215692 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1215692 # Request fanout histogram +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index dd52d45d1..9ca2241e2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,121 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961827 # Number of seconds simulated -sim_ticks 1961826628500 # Number of ticks simulated -final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962845 # Number of seconds simulated +sim_ticks 1962844580000 # Number of ticks simulated +final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1248737 # Simulator instruction rate (inst/s) -host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40231703865 # Simulator tick rate (ticks/s) -host_mem_usage 312404 # Number of bytes of host memory used -host_seconds 48.76 # Real time elapsed on the host -sim_insts 60892387 # Number of instructions simulated -sim_ops 60892387 # Number of ops (including micro ops) simulated +host_inst_rate 1184099 # Simulator instruction rate (inst/s) +host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38148129943 # Simulator tick rate (ticks/s) +host_mem_usage 318172 # Number of bytes of host memory used +host_seconds 51.45 # Real time elapsed on the host +sim_insts 60925667 # Number of instructions simulated +sim_ops 60925667 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory +system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407870 # Number of read requests accepted -system.physmem.writeReqs 120906 # Number of write requests accepted -system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue -system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25277 # Per bank write bursts -system.physmem.perBankRdBursts::1 25718 # Per bank write bursts -system.physmem.perBankRdBursts::2 25598 # Per bank write bursts -system.physmem.perBankRdBursts::3 25075 # Per bank write bursts -system.physmem.perBankRdBursts::4 25186 # Per bank write bursts -system.physmem.perBankRdBursts::5 25258 # Per bank write bursts -system.physmem.perBankRdBursts::6 25824 # Per bank write bursts -system.physmem.perBankRdBursts::7 25548 # Per bank write bursts -system.physmem.perBankRdBursts::8 25573 # Per bank write bursts -system.physmem.perBankRdBursts::9 25196 # Per bank write bursts -system.physmem.perBankRdBursts::10 25177 # Per bank write bursts -system.physmem.perBankRdBursts::11 25610 # Per bank write bursts -system.physmem.perBankRdBursts::12 25669 # Per bank write bursts -system.physmem.perBankRdBursts::13 25717 # Per bank write bursts -system.physmem.perBankRdBursts::14 26016 # Per bank write bursts -system.physmem.perBankRdBursts::15 25246 # Per bank write bursts -system.physmem.perBankWrBursts::0 7929 # Per bank write bursts -system.physmem.perBankWrBursts::1 7788 # Per bank write bursts -system.physmem.perBankWrBursts::2 7545 # Per bank write bursts -system.physmem.perBankWrBursts::3 7026 # Per bank write bursts -system.physmem.perBankWrBursts::4 7134 # Per bank write bursts -system.physmem.perBankWrBursts::5 7133 # Per bank write bursts -system.physmem.perBankWrBursts::6 7657 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7395 # Per bank write bursts -system.physmem.perBankWrBursts::9 7084 # Per bank write bursts -system.physmem.perBankWrBursts::10 7119 # Per bank write bursts -system.physmem.perBankWrBursts::11 7401 # Per bank write bursts -system.physmem.perBankWrBursts::12 7832 # Per bank write bursts -system.physmem.perBankWrBursts::13 8315 # Per bank write bursts -system.physmem.perBankWrBursts::14 8567 # Per bank write bursts -system.physmem.perBankWrBursts::15 7699 # Per bank write bursts +system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408360 # Number of read requests accepted +system.physmem.writeReqs 162776 # Number of write requests accepted +system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25705 # Per bank write bursts +system.physmem.perBankRdBursts::1 25985 # Per bank write bursts +system.physmem.perBankRdBursts::2 25732 # Per bank write bursts +system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::4 24847 # Per bank write bursts +system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::6 25534 # Per bank write bursts +system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::8 25150 # Per bank write bursts +system.physmem.perBankRdBursts::9 25518 # Per bank write bursts +system.physmem.perBankRdBursts::10 25462 # Per bank write bursts +system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::12 25577 # Per bank write bursts +system.physmem.perBankRdBursts::13 25454 # Per bank write bursts +system.physmem.perBankRdBursts::14 26241 # Per bank write bursts +system.physmem.perBankRdBursts::15 25973 # Per bank write bursts +system.physmem.perBankWrBursts::0 10613 # Per bank write bursts +system.physmem.perBankWrBursts::1 10753 # Per bank write bursts +system.physmem.perBankWrBursts::2 9796 # Per bank write bursts +system.physmem.perBankWrBursts::3 9387 # Per bank write bursts +system.physmem.perBankWrBursts::4 8893 # Per bank write bursts +system.physmem.perBankWrBursts::5 9110 # Per bank write bursts +system.physmem.perBankWrBursts::6 9958 # Per bank write bursts +system.physmem.perBankWrBursts::7 9669 # Per bank write bursts +system.physmem.perBankWrBursts::8 9689 # Per bank write bursts +system.physmem.perBankWrBursts::9 9901 # Per bank write bursts +system.physmem.perBankWrBursts::10 9876 # Per bank write bursts +system.physmem.perBankWrBursts::11 10215 # Per bank write bursts +system.physmem.perBankWrBursts::12 10815 # Per bank write bursts +system.physmem.perBankWrBursts::13 10652 # Per bank write bursts +system.physmem.perBankWrBursts::14 10531 # Per bank write bursts +system.physmem.perBankWrBursts::15 10637 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1961819616500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1962839541500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407870 # Read request sizes (log2) +system.physmem.readPktSize::6 408360 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120906 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162776 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,632 +158,180 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads -system.physmem.totQLat 2198653000 # Total ticks spent queuing -system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads +system.physmem.totQLat 2202002500 # Total ticks spent queuing +system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing -system.physmem.readRowHits 365377 # Number of row buffer hits during reads -system.physmem.writeRowHits 96760 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes -system.physmem.avgGap 3710114.71 # Average gap between requests -system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states -system.physmem.memoryStateTime::REF 65509600000 # Time in different power states +system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing +system.physmem.readRowHits 365785 # Number of row buffer hits during reads +system.physmem.writeRowHits 133797 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes +system.physmem.avgGap 3436728.80 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states +system.physmem.memoryStateTime::REF 65543660000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states +system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 248270400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 253917720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 135465000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 138546375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587175200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1592791200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 385326720 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 397949760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128136777600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128136777600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65365947855 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65768853780 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1119755735250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119402309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1315614698025 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1315691145435 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.607978 # Core power per rank (mW) -system.physmem.averagePower::1 670.646945 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 292757 # Transaction distribution -system.membus.trans_dist::ReadResp 292757 # Transaction distribution -system.membus.trans_dist::WriteReq 14067 # Transaction distribution -system.membus.trans_dist::WriteResp 14067 # Transaction distribution -system.membus.trans_dist::Writeback 79354 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution -system.membus.trans_dist::ReadExReq 123294 # Transaction distribution -system.membus.trans_dist::ReadExResp 122471 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21418 # Total snoops (count) -system.membus.snoop_fanout::samples 557197 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 557197 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.686708 # Core power per rank (mW) +system.physmem.averagePower::1 670.738650 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342092 # number of replacements -system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use -system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4934.415131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.916198 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.212322 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073365 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51884 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25951455 # Number of tag accesses -system.l2c.tags.data_accesses 25951455 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 690677 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 311497 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138541 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941964 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.763135 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.866605 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.955914 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975322 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.965628 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.474650 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.106488 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415771 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.327842 # 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mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173343 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.569739 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21248383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21248383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7562596 # DTB read hits +system.cpu0.dtb.read_hits 7534386 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5147185 # DTB write hits +system.cpu0.dtb.write_hits 5126601 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12709781 # DTB hits +system.cpu0.dtb.data_hits 12660987 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3660706 # ITB hits +system.cpu0.itb.fetch_hits 3654300 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3664690 # ITB accesses +system.cpu0.itb.fetch_accesses 3658284 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -799,91 +344,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923653257 # number of cpu cycles simulated +system.cpu0.numCycles 3925689160 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 48127777 # Number of instructions committed -system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses -system.cpu0.num_func_calls 1209739 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44643925 # number of integer instructions -system.cpu0.num_fp_insts 213512 # number of float instructions -system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written -system.cpu0.num_mem_refs 12750882 # number of memory refs -system.cpu0.num_load_insts 7590433 # Number of load instructions -system.cpu0.num_store_insts 5160449 # Number of store instructions -system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles -system.cpu0.Branches 7246936 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction -system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction -system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction -system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47974635 # Number of instructions committed +system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses +system.cpu0.num_func_calls 1202793 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_fp_insts 212945 # number of float instructions +system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written +system.cpu0.num_mem_refs 12702031 # number of memory refs +system.cpu0.num_load_insts 7562183 # Number of load instructions +system.cpu0.num_store_insts 5139848 # Number of store instructions +system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles +system.cpu0.Branches 7223323 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction +system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 48136795 # Class of executed instruction +system.cpu0.op_class::total 47983653 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -915,355 +460,125 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed +system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150611 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches +system.cpu0.kern.callpal::total 149871 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1370 -system.cpu0.kern.mode_good::user 1371 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3106 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 98838 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55619 # Transaction distribution -system.iobus.trans_dist::WriteResp 55619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 703089 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits -system.cpu0.icache.overall_hits::total 47433077 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses -system.cpu0.icache.overall_misses::total 703719 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1191194 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks. +system.cpu0.kern.swap_context 3098 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1190018 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits -system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses -system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits +system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1272,62 +587,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks -system.cpu0.dcache.writebacks::total 686359 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks +system.cpu0.dcache.writebacks::total 685854 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122281000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122281000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31509106 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31509106 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34996498062 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34996498062 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34996498062 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34996498062 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1335,26 +650,112 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 699671 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits +system.cpu0.icache.overall_hits::total 47283349 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses +system.cpu0.icache.overall_misses::total 700305 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2348280 # DTB read hits +system.cpu1.dtb.read_hits 2382379 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1676993 # DTB write hits +system.cpu1.dtb.write_hits 1702197 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4025273 # DTB hits +system.cpu1.dtb.data_hits 4084576 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1801078 # ITB hits +system.cpu1.itb.fetch_hits 1808740 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1802142 # ITB accesses +system.cpu1.itb.fetch_accesses 1809804 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1367,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921880878 # number of cpu cycles simulated +system.cpu1.numCycles 3923834014 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12764610 # Number of instructions committed -system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses -system.cpu1.num_func_calls 404048 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11762987 # number of integer instructions -system.cpu1.num_fp_insts 170364 # number of float instructions -system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written -system.cpu1.num_mem_refs 4047820 # number of memory refs -system.cpu1.num_load_insts 2361802 # Number of load instructions -system.cpu1.num_store_insts 1686018 # Number of store instructions -system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles -system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles -system.cpu1.Branches 1821460 # Number of branches fetched -system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction -system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction -system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 12951032 # Number of instructions committed +system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses +system.cpu1.num_func_calls 411532 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_fp_insts 171199 # number of float instructions +system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written +system.cpu1.num_mem_refs 4107226 # number of memory refs +system.cpu1.num_load_insts 2395961 # Number of load instructions +system.cpu1.num_store_insts 1711265 # Number of store instructions +system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles +system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles +system.cpu1.Branches 1849703 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction +system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction +system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction +system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12767489 # Class of executed instruction +system.cpu1.op_class::total 12953911 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1463,207 +864,123 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed +system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 70663 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches +system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 797 +system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 803 system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 430 -system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 436 +system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1956 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 311453 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits -system.cpu1.icache.overall_hits::total 12455485 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses -system.cpu1.icache.overall_misses::total 312004 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 155174 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.308424 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3855056 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks. +system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1968 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 157269 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits -system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses -system.cpu1.dcache.overall_misses::total 169714 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits +system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses +system.cpu1.dcache.overall_misses::total 172223 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1672,62 +989,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks -system.cpu1.dcache.writebacks::total 106457 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks +system.cpu1.dcache.writebacks::total 107940 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1735,5 +1052,696 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 318302 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits +system.cpu1.icache.overall_hits::total 12635057 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses +system.cpu1.icache.overall_misses::total 318854 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55631 # Transaction distribution +system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses +system.iocache.demand_misses::total 176 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 176 # number of overall misses +system.iocache.overall_misses::total 176 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 342754 # number of replacements +system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use +system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25998619 # Number of tag accesses +system.l2c.tags.data_accesses 25998619 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 687419 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668122 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 318193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 105248 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1778982 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 793794 # number of Writeback hits +system.l2c.Writeback_hits::total 793794 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 726 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 129870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42509 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172379 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 687419 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 797992 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 292732 # Transaction distribution +system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::WriteReq 14079 # Transaction distribution +system.membus.trans_dist::WriteResp 14079 # Transaction distribution +system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution +system.membus.trans_dist::ReadExReq 124094 # Transaction distribution +system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22113 # Total snoops (count) +system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 600297 # Request fanout histogram +system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99450 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 04dd39221..166d29f48 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,110 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.919439 # Number of seconds simulated -sim_ticks 1919439025000 # Number of ticks simulated -final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920428 # Number of seconds simulated +sim_ticks 1920427877000 # Number of ticks simulated +final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1406989 # Simulator instruction rate (inst/s) -host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48137648137 # Simulator tick rate (ticks/s) -host_mem_usage 309300 # Number of bytes of host memory used -host_seconds 39.87 # Real time elapsed on the host -sim_insts 56102180 # Number of instructions simulated -sim_ops 56102180 # Number of ops (including micro ops) simulated +host_inst_rate 694902 # Simulator instruction rate (inst/s) +host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23785763794 # Simulator tick rate (ticks/s) +host_mem_usage 317148 # Number of bytes of host memory used +host_seconds 80.74 # Real time elapsed on the host +sim_insts 56105324 # Number of instructions simulated +sim_ops 56105324 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401995 # Number of read requests accepted -system.physmem.writeReqs 115732 # Number of write requests accepted -system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue -system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25161 # Per bank write bursts +system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401719 # Number of read requests accepted +system.physmem.writeReqs 157241 # Number of write requests accepted +system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25160 # Per bank write bursts system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25618 # Per bank write bursts -system.physmem.perBankRdBursts::3 25536 # Per bank write bursts -system.physmem.perBankRdBursts::4 24982 # Per bank write bursts -system.physmem.perBankRdBursts::5 24977 # Per bank write bursts -system.physmem.perBankRdBursts::6 24228 # Per bank write bursts -system.physmem.perBankRdBursts::7 24506 # Per bank write bursts -system.physmem.perBankRdBursts::8 25158 # Per bank write bursts -system.physmem.perBankRdBursts::9 24823 # Per bank write bursts -system.physmem.perBankRdBursts::10 25363 # Per bank write bursts -system.physmem.perBankRdBursts::11 24839 # Per bank write bursts -system.physmem.perBankRdBursts::12 24418 # Per bank write bursts -system.physmem.perBankRdBursts::13 25388 # Per bank write bursts -system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25481 # Per bank write bursts -system.physmem.perBankWrBursts::0 7550 # Per bank write bursts -system.physmem.perBankWrBursts::1 7529 # Per bank write bursts -system.physmem.perBankWrBursts::2 7880 # Per bank write bursts -system.physmem.perBankWrBursts::3 7553 # Per bank write bursts -system.physmem.perBankWrBursts::4 7115 # Per bank write bursts -system.physmem.perBankWrBursts::5 6983 # Per bank write bursts -system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6315 # Per bank write bursts -system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7205 # Per bank write bursts -system.physmem.perBankWrBursts::11 6861 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7980 # Per bank write bursts -system.physmem.perBankWrBursts::15 7780 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 25522 # Per bank write bursts +system.physmem.perBankRdBursts::4 24974 # Per bank write bursts +system.physmem.perBankRdBursts::5 24970 # Per bank write bursts +system.physmem.perBankRdBursts::6 24210 # Per bank write bursts +system.physmem.perBankRdBursts::7 24489 # Per bank write bursts +system.physmem.perBankRdBursts::8 25140 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25361 # Per bank write bursts +system.physmem.perBankRdBursts::11 24836 # Per bank write bursts +system.physmem.perBankRdBursts::12 24395 # Per bank write bursts +system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::14 25772 # Per bank write bursts +system.physmem.perBankRdBursts::15 25478 # Per bank write bursts +system.physmem.perBankWrBursts::0 10040 # Per bank write bursts +system.physmem.perBankWrBursts::1 9905 # Per bank write bursts +system.physmem.perBankWrBursts::2 10447 # Per bank write bursts +system.physmem.perBankWrBursts::3 9982 # Per bank write bursts +system.physmem.perBankWrBursts::4 9551 # Per bank write bursts +system.physmem.perBankWrBursts::5 9392 # Per bank write bursts +system.physmem.perBankWrBursts::6 8805 # Per bank write bursts +system.physmem.perBankWrBursts::7 8555 # Per bank write bursts +system.physmem.perBankWrBursts::8 9942 # Per bank write bursts +system.physmem.perBankWrBursts::9 8777 # Per bank write bursts +system.physmem.perBankWrBursts::10 9524 # Per bank write bursts +system.physmem.perBankWrBursts::11 9288 # Per bank write bursts +system.physmem.perBankWrBursts::12 9847 # Per bank write bursts +system.physmem.perBankWrBursts::13 10608 # Per bank write bursts +system.physmem.perBankWrBursts::14 10278 # Per bank write bursts +system.physmem.perBankWrBursts::15 10262 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1919427104000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1920415956000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401995 # Read request sizes (log2) +system.physmem.readPktSize::6 401719 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157241 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -151,327 +148,180 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 202 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads -system.physmem.totQLat 2129492750 # Total ticks spent queuing -system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads +system.physmem.totQLat 2119831750 # Total ticks spent queuing +system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 359991 # Number of row buffer hits during reads -system.physmem.writeRowHits 93535 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3707411.64 # Average gap between requests -system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states -system.physmem.memoryStateTime::REF 64094160000 # Time in different power states +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 359880 # Number of row buffer hits during reads +system.physmem.writeRowHits 130510 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes +system.physmem.avgGap 3435694.78 # Average gap between requests +system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states +system.physmem.memoryStateTime::REF 64127180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states +system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 236499480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 247272480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 129042375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 134920500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1564266600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1569867000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 370954080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 378814320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 125368176960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 125368176960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 63948324510 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 64460493450 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1095566249250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1095116978250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1287183513255 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1287276522960 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.605262 # Core power per rank (mW) -system.physmem.averagePower::1 670.653719 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 292357 # Transaction distribution -system.membus.trans_dist::ReadResp 292357 # Transaction distribution -system.membus.trans_dist::WriteReq 9649 # Transaction distribution -system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 74180 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116726 # Transaction distribution -system.membus.trans_dist::ReadExResp 116726 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 158 # Total snoops (count) -system.membus.snoop_fanout::samples 518029 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 518029 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375557 # Number of tag accesses -system.iocache.tags.data_accesses 375557 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles -system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.686297 # Core power per rank (mW) +system.physmem.averagePower::1 670.727042 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052455 # DTB read hits -system.cpu.dtb.read_misses 10357 # DTB read misses +system.cpu.dtb.read_hits 9053154 # DTB read hits +system.cpu.dtb.read_misses 10325 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728916 # DTB read accesses -system.cpu.dtb.write_hits 6349129 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728854 # DTB read accesses +system.cpu.dtb.write_hits 6349573 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15401584 # DTB hits -system.cpu.dtb.data_misses 11500 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15402727 # DTB hits +system.cpu.dtb.data_misses 11467 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020848 # DTB accesses -system.cpu.itb.fetch_hits 4974880 # ITB hits +system.cpu.dtb.data_accesses 1020785 # DTB accesses +system.cpu.itb.fetch_hits 4974627 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979890 # ITB accesses +system.cpu.itb.fetch_accesses 4979637 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -484,34 +334,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838878050 # number of cpu cycles simulated +system.cpu.numCycles 3840855754 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102180 # Number of instructions committed -system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses -system.cpu.num_func_calls 1481232 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls -system.cpu.num_int_insts 51977296 # number of integer instructions -system.cpu.num_fp_insts 324326 # number of float instructions -system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written -system.cpu.num_mem_refs 15454224 # number of memory refs -system.cpu.num_load_insts 9089337 # Number of load instructions -system.cpu.num_store_insts 6364887 # Number of store instructions -system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934448 # Percentage of idle cycles -system.cpu.Branches 8412776 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56105324 # Number of instructions committed +system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses +system.cpu.num_func_calls 1481352 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls +system.cpu.num_int_insts 51980283 # number of integer instructions +system.cpu.num_fp_insts 324527 # number of float instructions +system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read +system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written +system.cpu.num_mem_refs 15455353 # number of memory refs +system.cpu.num_load_insts 9090013 # Number of load instructions +system.cpu.num_store_insts 6365340 # Number of store instructions +system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934477 # Percentage of idle cycles +system.cpu.Branches 8413247 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -537,34 +387,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114047 # Class of executed instruction +system.cpu.op_class::total 56117158 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -600,184 +450,229 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192892 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1742 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1742 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192910 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1914 +system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4176 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51197 # Transaction distribution -system.iobus.trans_dist::WriteResp 51201 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927651 # number of replacements -system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks. +system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390139 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits +system.cpu.dcache.overall_hits::total 13648845 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses +system.cpu.dcache.overall_misses::total 1373441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41913 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41901 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51202 # Transaction distribution +system.iobus.trans_dist::WriteResp 9650 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 292355 # Transaction distribution +system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::WriteReq 9650 # Transaction distribution +system.membus.trans_dist::WriteResp 9650 # Transaction distribution +system.membus.trans_dist::Writeback 115689 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116723 # Transaction distribution +system.membus.trans_dist::ReadExResp 116723 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 431 # Total snoops (count) +system.membus.snoop_fanout::samples 559521 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 559521 # Request fanout histogram +system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 1efe64b0a..a51b2d079 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,76 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882634000 # Number of ticks simulated -final_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802895 # Number of seconds simulated +sim_ticks 2802895103500 # Number of ticks simulated +final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1078207 # Simulator instruction rate (inst/s) -host_op_rate 1313778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20582448891 # Simulator tick rate (ticks/s) -host_mem_usage 574132 # Number of bytes of host memory used -host_seconds 136.18 # Real time elapsed on the host -sim_insts 146828350 # Number of instructions simulated -sim_ops 178908035 # Number of ops (including micro ops) simulated +host_inst_rate 967895 # Simulator instruction rate (inst/s) +host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18476638236 # Simulator tick rate (ticks/s) +host_mem_usage 571628 # Number of bytes of host memory used +host_seconds 151.70 # Real time elapsed on the host +sim_insts 146829031 # Number of instructions simulated +sim_ops 178908942 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11809044 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory +system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8407824 # Number of bytes written to this memory +system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193673 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135531 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -119,9 +116,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339775 # DTB read hits -system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16390998 # DTB write hits +system.cpu0.dtb.read_hits 20339962 # DTB read hits +system.cpu0.dtb.read_misses 6874 # DTB read misses +system.cpu0.dtb.write_hits 16391171 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +129,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346646 # DTB read accesses -system.cpu0.dtb.write_accesses 16392091 # DTB write accesses +system.cpu0.dtb.read_accesses 20346836 # DTB read accesses +system.cpu0.dtb.write_accesses 16392264 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730773 # DTB hits -system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738737 # DTB accesses +system.cpu0.dtb.hits 36731133 # DTB hits +system.cpu0.dtb.misses 7967 # DTB misses +system.cpu0.dtb.accesses 36739100 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -159,7 +156,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 97439484 # ITB inst hits +system.cpu0.itb.inst_hits 97440315 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -176,38 +173,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442842 # ITB inst accesses -system.cpu0.itb.hits 97439484 # DTB hits +system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses +system.cpu0.itb.hits 97440315 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442842 # DTB accesses -system.cpu0.numCycles 5605767234 # number of cpu cycles simulated +system.cpu0.itb.accesses 97443673 # DTB accesses +system.cpu0.numCycles 5605792176 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427026 # Number of instructions committed -system.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses +system.cpu0.committedInsts 95427853 # Number of instructions committed +system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000257 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762684 # number of integer instructions +system.cpu0.num_func_calls 8000324 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100763618 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873766 # number of memory refs -system.cpu0.num_load_insts 20597356 # Number of load instructions -system.cpu0.num_store_insts 17276410 # Number of store instructions -system.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles -system.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles +system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written +system.cpu0.num_mem_refs 37874145 # number of memory refs +system.cpu0.num_load_insts 20597552 # Number of load instructions +system.cpu0.num_store_insts 17276593 # Number of store instructions +system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles +system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941641 # Number of branches fetched +system.cpu0.Branches 21941792 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -235,20 +232,20 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882135 # Class of executed instruction +system.cpu0.op_class::total 116883193 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 693468 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 693476 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -256,60 +253,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits -system.cpu0.dcache.overall_hits::total 35144985 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses -system.cpu0.dcache.overall_misses::total 769182 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses +system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses +system.cpu0.dcache.overall_misses::total 769184 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048360 # miss rate for StoreCondReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses @@ -322,16 +319,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511566 # number of writebacks -system.cpu0.dcache.writebacks::total 511566 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks +system.cpu0.dcache.writebacks::total 511648 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109631 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331674 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.774113 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1109742 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -339,32 +336,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993804 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993804 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331674 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331674 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331674 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331674 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331674 # number of overall hits -system.cpu0.icache.overall_hits::total 96331674 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses -system.cpu0.icache.overall_misses::total 1110152 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441826 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441826 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441826 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441826 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441826 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441826 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits +system.cpu0.icache.overall_hits::total 96332394 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses +system.cpu0.icache.overall_misses::total 1110263 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,123 +380,123 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 252467 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16137.499100 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809671 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268655 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.736041 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252403 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.791544 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.201142 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081297 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.858530 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.566587 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # 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number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18448 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7884 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3396 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871102 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7884 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3396 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # 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number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # 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number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,45 +505,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks -system.cpu0.l2cache.writebacks::total 192870 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks +system.cpu0.l2cache.writebacks::total 192841 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322137 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322042 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -570,9 +567,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173905 # DTB read hits -system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587201 # DTB write hits +system.cpu1.dtb.read_hits 12173884 # DTB read hits +system.cpu1.dtb.read_misses 2852 # DTB read misses +system.cpu1.dtb.write_hits 7587193 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -583,12 +580,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176758 # DTB read accesses -system.cpu1.dtb.write_accesses 7587707 # DTB write accesses +system.cpu1.dtb.read_accesses 12176736 # DTB read accesses +system.cpu1.dtb.write_accesses 7587699 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761106 # DTB hits -system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764465 # DTB accesses +system.cpu1.dtb.hits 19761077 # DTB hits +system.cpu1.dtb.misses 3358 # DTB misses +system.cpu1.dtb.accesses 19764435 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -610,7 +607,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 53671578 # ITB inst hits +system.cpu1.itb.inst_hits 53671431 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -627,38 +624,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673312 # ITB inst accesses -system.cpu1.itb.hits 53671578 # DTB hits +system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses +system.cpu1.itb.hits 53671431 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673312 # DTB accesses -system.cpu1.numCycles 5605296143 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673165 # DTB accesses +system.cpu1.numCycles 5605321082 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401324 # Number of instructions committed -system.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses +system.cpu1.committedInsts 51401178 # Number of instructions committed +system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170833 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984226 # number of integer instructions +system.cpu1.num_func_calls 9170823 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984089 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026364 # number of memory refs -system.cpu1.num_load_insts 12289528 # Number of load instructions -system.cpu1.num_store_insts 7736836 # Number of store instructions -system.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles -system.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026333 # number of memory refs +system.cpu1.num_load_insts 12289505 # Number of load instructions +system.cpu1.num_store_insts 7736828 # Number of store instructions +system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles +system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217468 # Number of branches fetched +system.cpu1.Branches 15217445 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401296 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -686,84 +683,84 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289528 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736836 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459439 # Class of executed instruction +system.cpu1.op_class::total 65459288 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 191947 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736020 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503484 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.421646 # Average number of references to valid blocks. +system.cpu1.dcache.tags.replacements 191938 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736020 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751950 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751950 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858675 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858675 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397476 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397476 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits +system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72420 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256151 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256151 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306251 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306251 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92478 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92478 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22559 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22559 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229117 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229117 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259835 # number of overall misses -system.cpu1.dcache.overall_misses::total 259835 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995314 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995314 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489954 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489954 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses +system.cpu1.dcache.overall_misses::total 259820 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485268 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485268 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566086 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566086 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237516 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237516 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,42 +769,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120692 # number of writebacks -system.cpu1.dcache.writebacks::total 120692 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks +system.cpu1.dcache.writebacks::total 120709 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 523402 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148754 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.445569 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 523373 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869250 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869250 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148754 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148754 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148754 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148754 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148754 # number of overall hits -system.cpu1.icache.overall_hits::total 53148754 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses -system.cpu1.icache.overall_misses::total 523914 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672668 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672668 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672668 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672668 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672668 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672668 # number of overall (read+write) accesses +system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits +system.cpu1.icache.overall_hits::total 53148636 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses +system.cpu1.icache.overall_misses::total 523885 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -832,121 +829,121 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 48632 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15302.414906 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716436 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63462 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.289212 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48598 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.533576 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.964027 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.029845 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.932073 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.955385 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.505953 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200374 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227231 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14804 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4941 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001587 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903564 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15214590 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15214590 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3250 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1767 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510040 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99338 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614395 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120692 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120692 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19796 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19796 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3250 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1767 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510040 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634191 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3250 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1767 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510040 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119134 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634191 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 269 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13874 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73337 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87825 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28856 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28856 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22559 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22559 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43819 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43819 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 269 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13874 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117156 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131644 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 269 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13874 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117156 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131644 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3595 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2036 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 702220 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120692 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120692 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28863 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28863 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22559 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22559 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3595 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2036 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765835 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3595 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2036 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765835 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.132122 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026481 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424711 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.125068 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688816 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688816 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.132122 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026481 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495814 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171896 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.132122 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026481 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495814 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171896 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -955,45 +952,45 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32939 # number of writebacks -system.cpu1.l2cache.writebacks::total 32939 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks +system.cpu1.l2cache.writebacks::total 32919 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707576 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499621 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499587 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371622 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram system.iobus.trans_dist::ReadReq 31002 # Transaction distribution system.iobus.trans_dist::ReadResp 31002 # Transaction distribution system.iobus.trans_dist::WriteReq 59433 # Transaction distribution @@ -1050,23 +1047,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses @@ -1081,6 +1078,8 @@ system.iocache.overall_accesses::realview.ide 252 system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -1091,187 +1090,188 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107659 # number of replacements -system.l2c.tags.tagsinuse 62143.932416 # Cycle average of tags in use -system.l2c.tags.total_refs 208094 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168104 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237888 # Average number of references to valid blocks. +system.l2c.tags.replacements 107620 # number of replacements +system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use +system.l2c.tags.total_refs 207975 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48688.063077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7324.743178 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3758.906335 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1656.372339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 711.015210 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.742921 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1910 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13081 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45354 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4903872 # Number of tag accesses -system.l2c.tags.data_accesses 4903872 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 74 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28084 # 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number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1280,49 +1280,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94871 # number of writebacks -system.l2c.writebacks::total 94871 # number of writebacks +system.l2c.writebacks::writebacks 94860 # number of writebacks +system.l2c.writebacks::total 94860 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75959 # Transaction distribution -system.membus.trans_dist::ReadResp 75959 # Transaction distribution +system.membus.trans_dist::ReadReq 75978 # Transaction distribution +system.membus.trans_dist::ReadResp 75978 # Transaction distribution system.membus.trans_dist::WriteReq 30905 # Transaction distribution system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 94871 # Transaction distribution +system.membus.trans_dist::Writeback 131050 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60398 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15640 # Transaction distribution -system.membus.trans_dist::ReadExReq 196324 # Transaction distribution -system.membus.trans_dist::ReadExResp 152195 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution +system.membus.trans_dist::ReadExReq 196304 # Transaction distribution +system.membus.trans_dist::ReadExResp 152218 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 460700 # Request fanout histogram +system.membus.snoop_fanout::samples 496844 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460700 # Request fanout histogram +system.membus.snoop_fanout::total 496844 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1354,33 +1354,33 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 755cdf962..5c160a43e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,59 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783854461500 # Number of ticks simulated -final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783867 # Number of seconds simulated +sim_ticks 2783867165000 # Number of ticks simulated +final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1414038 # Simulator instruction rate (inst/s) -host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27571822204 # Simulator tick rate (ticks/s) -host_mem_usage 560116 # Number of bytes of host memory used -host_seconds 100.97 # Real time elapsed on the host -sim_insts 142771592 # Number of instructions simulated -sim_ops 173801445 # Number of ops (including micro ops) simulated +host_inst_rate 1064003 # Simulator instruction rate (inst/s) +host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20746494205 # Simulator tick rate (ticks/s) +host_mem_usage 558936 # Number of bytes of host memory used +host_seconds 134.19 # Real time elapsed on the host +sim_insts 142773109 # Number of instructions simulated +sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -96,9 +93,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525959 # DTB read hits -system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124081 # DTB write hits +system.cpu.dtb.read_hits 31526301 # DTB read hits +system.cpu.dtb.read_misses 8581 # DTB read misses +system.cpu.dtb.write_hits 23124463 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -109,12 +106,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534539 # DTB read accesses -system.cpu.dtb.write_accesses 23125529 # DTB write accesses +system.cpu.dtb.read_accesses 31534882 # DTB read accesses +system.cpu.dtb.write_accesses 23125911 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650040 # DTB hits -system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54660068 # DTB accesses +system.cpu.dtb.hits 54650764 # DTB hits +system.cpu.dtb.misses 10029 # DTB misses +system.cpu.dtb.accesses 54660793 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -136,7 +133,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 147038107 # ITB inst hits +system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -153,38 +150,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042869 # ITB inst accesses -system.cpu.itb.hits 147038107 # DTB hits +system.cpu.itb.inst_accesses 147044354 # ITB inst accesses +system.cpu.itb.hits 147039592 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042869 # DTB accesses -system.cpu.numCycles 5567712004 # number of cpu cycles simulated +system.cpu.itb.accesses 147044354 # DTB accesses +system.cpu.numCycles 5567737414 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142771592 # Number of instructions committed -system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses +system.cpu.committedInsts 142773109 # Number of instructions committed +system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873874 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls -system.cpu.num_int_insts 153161099 # number of integer instructions +system.cpu.num_func_calls 16873879 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls +system.cpu.num_int_insts 153162826 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written +system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written -system.cpu.num_mem_refs 55938603 # number of memory refs -system.cpu.num_load_insts 31855595 # Number of load instructions -system.cpu.num_store_insts 24083008 # Number of store instructions -system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles -system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles +system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written +system.cpu.num_mem_refs 55939365 # number of memory refs +system.cpu.num_load_insts 31855962 # Number of load instructions +system.cpu.num_store_insts 24083403 # Number of store instructions +system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles +system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396923 # Number of branches fetched +system.cpu.Branches 36397028 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -212,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177218284 # Class of executed instruction +system.cpu.op_class::total 177220138 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 819396 # number of replacements +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 819403 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -233,58 +230,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits -system.cpu.dcache.overall_hits::total 52863618 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits +system.cpu.dcache.overall_hits::total 52864309 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses -system.cpu.dcache.overall_misses::total 814069 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses +system.cpu.dcache.overall_misses::total 814075 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -299,16 +296,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks -system.cpu.dcache.writebacks::total 682037 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks +system.cpu.dcache.writebacks::total 682060 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699006 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1699220 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -317,32 +314,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits -system.cpu.icache.overall_hits::total 145341690 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses -system.cpu.icache.overall_misses::total 1699524 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits +system.cpu.icache.overall_hits::total 145342961 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses +system.cpu.icache.overall_misses::total 1699738 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,21 +350,21 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id @@ -379,29 +376,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits -system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses @@ -423,50 +420,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses system.cpu.l2cache.overall_misses::total 181765 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,45 +472,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks -system.cpu.l2cache.writebacks::total 101899 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks +system.cpu.l2cache.writebacks::total 101898 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36632 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 36631 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram system.iobus.trans_dist::ReadReq 30171 # Transaction distribution system.iobus.trans_dist::ReadResp 30171 # Transaction distribution system.iobus.trans_dist::WriteReq 59016 # Transaction distribution @@ -570,23 +567,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses @@ -601,6 +598,8 @@ system.iocache.overall_accesses::realview.ide 240 system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -611,14 +610,16 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 74235 # Transaction distribution system.membus.trans_dist::ReadResp 74235 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101899 # Transaction distribution +system.membus.trans_dist::Writeback 138088 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -629,31 +630,31 @@ system.membus.trans_dist::ReadExResp 146085 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322858 # Request fanout histogram +system.membus.snoop_fanout::samples 359047 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322858 # Request fanout histogram +system.membus.snoop_fanout::total 359047 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 23357c831..ede2b82db 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,169 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.866913 # Number of seconds simulated -sim_ticks 2866913114000 # Number of ticks simulated -final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.867049 # Number of seconds simulated +sim_ticks 2867048515500 # Number of ticks simulated +final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 786450 # Simulator instruction rate (inst/s) -host_op_rate 951292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17090693254 # Simulator tick rate (ticks/s) -host_mem_usage 609256 # Number of bytes of host memory used -host_seconds 167.75 # Real time elapsed on the host -sim_insts 131924636 # Number of instructions simulated -sim_ops 159576421 # Number of ops (including micro ops) simulated +host_inst_rate 753572 # Simulator instruction rate (inst/s) +host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16376301643 # Simulator tick rate (ticks/s) +host_mem_usage 607016 # Number of bytes of host memory used +host_seconds 175.07 # Real time elapsed on the host +sim_insts 131930165 # Number of instructions simulated +sim_ops 159581077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory +system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory +system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory +system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 205263 # Number of read requests accepted -system.physmem.writeReqs 140582 # Number of write requests accepted -system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue -system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12846 # Per bank write bursts -system.physmem.perBankRdBursts::1 12299 # Per bank write bursts -system.physmem.perBankRdBursts::2 13037 # Per bank write bursts -system.physmem.perBankRdBursts::3 12736 # Per bank write bursts -system.physmem.perBankRdBursts::4 21227 # Per bank write bursts -system.physmem.perBankRdBursts::5 12513 # Per bank write bursts -system.physmem.perBankRdBursts::6 12853 # Per bank write bursts -system.physmem.perBankRdBursts::7 12957 # Per bank write bursts -system.physmem.perBankRdBursts::8 12050 # Per bank write bursts -system.physmem.perBankRdBursts::9 12106 # Per bank write bursts -system.physmem.perBankRdBursts::10 12270 # Per bank write bursts -system.physmem.perBankRdBursts::11 11010 # Per bank write bursts -system.physmem.perBankRdBursts::12 11804 # Per bank write bursts -system.physmem.perBankRdBursts::13 12158 # Per bank write bursts -system.physmem.perBankRdBursts::14 11709 # Per bank write bursts -system.physmem.perBankRdBursts::15 11437 # Per bank write bursts -system.physmem.perBankWrBursts::0 8735 # Per bank write bursts -system.physmem.perBankWrBursts::1 8638 # Per bank write bursts -system.physmem.perBankWrBursts::2 9213 # Per bank write bursts -system.physmem.perBankWrBursts::3 8824 # Per bank write bursts -system.physmem.perBankWrBursts::4 8594 # Per bank write bursts -system.physmem.perBankWrBursts::5 8713 # Per bank write bursts -system.physmem.perBankWrBursts::6 8840 # Per bank write bursts -system.physmem.perBankWrBursts::7 8875 # Per bank write bursts -system.physmem.perBankWrBursts::8 8399 # Per bank write bursts -system.physmem.perBankWrBursts::9 8546 # Per bank write bursts -system.physmem.perBankWrBursts::10 8611 # Per bank write bursts -system.physmem.perBankWrBursts::11 8118 # Per bank write bursts -system.physmem.perBankWrBursts::12 8409 # Per bank write bursts -system.physmem.perBankWrBursts::13 8327 # Per bank write bursts -system.physmem.perBankWrBursts::14 8185 # Per bank write bursts -system.physmem.perBankWrBursts::15 7610 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 204505 # Number of read requests accepted +system.physmem.writeReqs 176547 # Number of write requests accepted +system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12666 # Per bank write bursts +system.physmem.perBankRdBursts::1 12263 # Per bank write bursts +system.physmem.perBankRdBursts::2 12897 # Per bank write bursts +system.physmem.perBankRdBursts::3 12449 # Per bank write bursts +system.physmem.perBankRdBursts::4 21010 # Per bank write bursts +system.physmem.perBankRdBursts::5 12626 # Per bank write bursts +system.physmem.perBankRdBursts::6 12991 # Per bank write bursts +system.physmem.perBankRdBursts::7 13024 # Per bank write bursts +system.physmem.perBankRdBursts::8 12039 # Per bank write bursts +system.physmem.perBankRdBursts::9 12109 # Per bank write bursts +system.physmem.perBankRdBursts::10 12276 # Per bank write bursts +system.physmem.perBankRdBursts::11 10996 # Per bank write bursts +system.physmem.perBankRdBursts::12 11725 # Per bank write bursts +system.physmem.perBankRdBursts::13 12231 # Per bank write bursts +system.physmem.perBankRdBursts::14 11672 # Per bank write bursts +system.physmem.perBankRdBursts::15 11389 # Per bank write bursts +system.physmem.perBankWrBursts::0 10702 # Per bank write bursts +system.physmem.perBankWrBursts::1 10814 # Per bank write bursts +system.physmem.perBankWrBursts::2 11122 # Per bank write bursts +system.physmem.perBankWrBursts::3 10684 # Per bank write bursts +system.physmem.perBankWrBursts::4 10817 # Per bank write bursts +system.physmem.perBankWrBursts::5 11014 # Per bank write bursts +system.physmem.perBankWrBursts::6 11094 # Per bank write bursts +system.physmem.perBankWrBursts::7 11085 # Per bank write bursts +system.physmem.perBankWrBursts::8 10650 # Per bank write bursts +system.physmem.perBankWrBursts::9 11040 # Per bank write bursts +system.physmem.perBankWrBursts::10 10845 # Per bank write bursts +system.physmem.perBankWrBursts::11 10150 # Per bank write bursts +system.physmem.perBankWrBursts::12 10760 # Per bank write bursts +system.physmem.perBankWrBursts::13 10359 # Per bank write bursts +system.physmem.perBankWrBursts::14 10115 # Per bank write bursts +system.physmem.perBankWrBursts::15 9574 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2866912757000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2867048141000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195493 # Read request sizes (log2) +system.physmem.readPktSize::6 194735 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136146 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see +system.physmem.writePktSize::6 172111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -191,154 +188,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads -system.physmem.totQLat 5976562250 # Total ticks spent queuing -system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads +system.physmem.totQLat 5974898500 # Total ticks spent queuing +system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing -system.physmem.readRowHits 175010 # Number of row buffer hits during reads -system.physmem.writeRowHits 85700 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes -system.physmem.avgGap 8289588.56 # Average gap between requests -system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states -system.physmem.memoryStateTime::REF 95732520000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing +system.physmem.readRowHits 174382 # Number of row buffer hits during reads +system.physmem.writeRowHits 117590 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes +system.physmem.avgGap 7524033.84 # Average gap between requests +system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states +system.physmem.memoryStateTime::REF 95736940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states +system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.485397 # Core power per rank (mW) -system.physmem.averagePower::1 669.364885 # Core power per rank (mW) +system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.533155 # Core power per rank (mW) +system.physmem.averagePower::1 669.414075 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -387,25 +408,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24351477 # DTB read hits -system.cpu0.dtb.read_misses 6408 # DTB read misses -system.cpu0.dtb.write_hits 18124986 # DTB write hits -system.cpu0.dtb.write_misses 1114 # DTB write misses +system.cpu0.dtb.read_hits 22739909 # DTB read hits +system.cpu0.dtb.read_misses 4142 # DTB read misses +system.cpu0.dtb.write_hits 16676295 # DTB write hits +system.cpu0.dtb.write_misses 677 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24357885 # DTB read accesses -system.cpu0.dtb.write_accesses 18126100 # DTB write accesses +system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22744051 # DTB read accesses +system.cpu0.dtb.write_accesses 16676972 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42476463 # DTB hits -system.cpu0.dtb.misses 7522 # DTB misses -system.cpu0.dtb.accesses 42483985 # DTB accesses +system.cpu0.dtb.hits 39416204 # DTB hits +system.cpu0.dtb.misses 4819 # DTB misses +system.cpu0.dtb.accesses 39421023 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,8 +448,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 115065570 # ITB inst hits -system.cpu0.itb.inst_misses 3350 # ITB inst misses +system.cpu0.itb.inst_hits 107931670 # ITB inst hits +system.cpu0.itb.inst_misses 2300 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -437,179 +458,178 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses -system.cpu0.itb.hits 115065570 # DTB hits -system.cpu0.itb.misses 3350 # DTB misses -system.cpu0.itb.accesses 115068920 # DTB accesses -system.cpu0.numCycles 5733826228 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses +system.cpu0.itb.hits 107931670 # DTB hits +system.cpu0.itb.misses 2300 # DTB misses +system.cpu0.itb.accesses 107933970 # DTB accesses +system.cpu0.numCycles 5733190951 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111421445 # Number of instructions committed -system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12527454 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls -system.cpu0.num_int_insts 119418221 # number of integer instructions -system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read -system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written -system.cpu0.num_mem_refs 43585923 # number of memory refs -system.cpu0.num_load_insts 24597873 # Number of load instructions -system.cpu0.num_store_insts 18988050 # Number of store instructions -system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles -system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles -system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles -system.cpu0.Branches 28215151 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction -system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction -system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 104697045 # Number of instructions committed +system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses +system.cpu0.num_func_calls 12218983 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls +system.cpu0.num_int_insts 112138973 # number of integer instructions +system.cpu0.num_fp_insts 4560 # number of float instructions +system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read +system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written +system.cpu0.num_mem_refs 40473955 # number of memory refs +system.cpu0.num_load_insts 22968630 # Number of load instructions +system.cpu0.num_store_insts 17505325 # Number of store instructions +system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles +system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles +system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles +system.cpu0.Branches 26957408 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction +system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction +system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 138426785 # Class of executed instruction +system.cpu0.op_class::total 130069369 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 658574 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 555287 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits -system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses -system.cpu0.dcache.overall_misses::total 764106 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 329300 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37695589 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37695589 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38000302 # number of overall hits +system.cpu0.dcache.overall_hits::total 38000302 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 304912 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 304912 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 263418 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 263418 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92252 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 92252 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20070 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20070 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20705 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses +system.cpu0.dcache.overall_misses::total 660582 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232393 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232393 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056630 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056630 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.059156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.059156 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014853 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.014853 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.017087 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.017087 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -618,82 +638,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks -system.cpu0.dcache.writebacks::total 483361 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks +system.cpu0.dcache.writebacks::total 420867 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7211 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14132 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14132 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 7211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 7211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 7211 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 7211 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 297701 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 297701 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 263418 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 263418 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 83423 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 83423 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5938 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5938 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20705 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20705 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 561119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 561119 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 644542 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 644542 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3232031980 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3232031980 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3494328319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3494328319 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1040331239 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1040331239 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86260500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86260500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 420440307 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 420440307 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1400500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -701,58 +721,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1061124 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 945322 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits -system.cpu0.icache.overall_hits::total 114003925 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses -system.cpu0.icache.overall_misses::total 1061645 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits +system.cpu0.icache.overall_hits::total 106985827 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses +system.cpu0.icache.overall_misses::total 945843 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,359 +781,356 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 357554 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 309925 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16107.929627 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1687462 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 325154 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.189732 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428717 # 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number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7436.103816 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.411647 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000196 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.047240 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.070197 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.453864 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.983150 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 9588 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5627 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1190 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 8332 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # 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mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.753173 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.920761 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.920761 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.080680 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1123,57 +1140,57 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 988296 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1198,25 +1215,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4826061 # DTB read hits -system.cpu1.dtb.read_misses 2744 # DTB read misses -system.cpu1.dtb.write_hits 4130169 # DTB write hits -system.cpu1.dtb.write_misses 524 # DTB write misses +system.cpu1.dtb.read_hits 6438534 # DTB read hits +system.cpu1.dtb.read_misses 5066 # DTB read misses +system.cpu1.dtb.write_hits 5578600 # DTB write hits +system.cpu1.dtb.write_misses 983 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4828805 # DTB read accesses -system.cpu1.dtb.write_accesses 4130693 # DTB write accesses +system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6443600 # DTB read accesses +system.cpu1.dtb.write_accesses 5579583 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 8956230 # DTB hits -system.cpu1.dtb.misses 3268 # DTB misses -system.cpu1.dtb.accesses 8959498 # DTB accesses +system.cpu1.dtb.hits 12017134 # DTB hits +system.cpu1.dtb.misses 6049 # DTB misses +system.cpu1.dtb.accesses 12023183 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1238,8 +1255,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20883965 # ITB inst hits -system.cpu1.itb.inst_misses 1747 # ITB inst misses +system.cpu1.itb.inst_hits 28023624 # ITB inst hits +system.cpu1.itb.inst_misses 2794 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1248,178 +1265,179 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses -system.cpu1.itb.hits 20883965 # DTB hits -system.cpu1.itb.misses 1747 # DTB misses -system.cpu1.itb.accesses 20885712 # DTB accesses -system.cpu1.numCycles 5732918807 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses +system.cpu1.itb.hits 28023624 # DTB hits +system.cpu1.itb.misses 2794 # DTB misses +system.cpu1.itb.accesses 28026418 # DTB accesses +system.cpu1.numCycles 5734097031 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20503191 # Number of instructions committed -system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1209330 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22184707 # number of integer instructions -system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written -system.cpu1.num_mem_refs 9245671 # number of memory refs -system.cpu1.num_load_insts 4945342 # Number of load instructions -system.cpu1.num_store_insts 4300329 # Number of store instructions -system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles -system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles -system.cpu1.Branches 3891928 # Number of branches fetched -system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction -system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction -system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction -system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction +system.cpu1.committedInsts 27233120 # Number of instructions committed +system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses +system.cpu1.num_func_calls 1518648 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls +system.cpu1.num_int_insts 29468029 # number of integer instructions +system.cpu1.num_fp_insts 6988 # number of float instructions +system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written +system.cpu1.num_mem_refs 12358568 # number of memory refs +system.cpu1.num_load_insts 6575418 # Number of load instructions +system.cpu1.num_store_insts 5783150 # Number of store instructions +system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles +system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles +system.cpu1.Branches 5151142 # Number of branches fetched +system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction +system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction +system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 25296825 # Class of executed instruction +system.cpu1.op_class::total 33659368 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 218952 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 321673 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits -system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses -system.cpu1.dcache.overall_misses::total 293221 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits +system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses +system.cpu1.dcache.overall_misses::total 396537 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1428,84 +1446,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks -system.cpu1.dcache.writebacks::total 135060 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # 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average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks +system.cpu1.dcache.writebacks::total 197265 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # 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number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1513,58 +1529,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 565004 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 680772 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits -system.cpu1.icache.overall_hits::total 20318443 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses -system.cpu1.icache.overall_misses::total 565517 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits +system.cpu1.icache.overall_hits::total 27342334 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses +system.cpu1.icache.overall_misses::total 681285 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5656981010 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5656981010 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5656981010 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5656981010 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5656981010 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5656981010 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 28023619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 28023619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 28023619 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 28023619 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 28023619 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8303.398739 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1573,356 +1589,361 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024311 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024311 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024311 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6803.097808 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85089 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 135060 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 186017515 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2032887126 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 4336083136 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 6562071278 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 923111999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 935587499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 807820502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 807820502 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1730932501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1743408001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.290550 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.088148 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1932,64 +1953,64 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 818999 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31019 # Transaction distribution -system.iobus.trans_dist::ReadResp 31019 # Transaction distribution -system.iobus.trans_dist::WriteReq 59407 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59437 # Transaction distribution +system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2010,11 +2031,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2035,11 +2056,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2079,601 +2100,613 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36443 # number of replacements -system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use +system.iocache.tags.replacements 36459 # number of replacements +system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328557 # Number of tag accesses -system.iocache.tags.data_accesses 328557 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328293 # Number of tag accesses +system.iocache.tags.data_accesses 328293 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses system.iocache.ReadReq_misses::total 253 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses system.iocache.demand_misses::total 253 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 253 # number of overall misses system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132935 # number of replacements -system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use -system.l2c.tags.total_refs 488817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks. +system.l2c.tags.replacements 132552 # number of replacements +system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use +system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6143442 # Number of tag accesses -system.l2c.tags.data_accesses 6143442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits -system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits -system.l2c.Writeback_hits::total 240423 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits -system.l2c.demand_hits::total 276883 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits -system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits -system.l2c.overall_hits::cpu0.data 33543 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits -system.l2c.overall_hits::cpu1.data 12939 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits -system.l2c.overall_hits::total 276883 # number of overall hits +system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6110572 # Number of tag accesses +system.l2c.tags.data_accesses 6110572 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits +system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits +system.l2c.Writeback_hits::total 239712 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits +system.l2c.demand_hits::total 274257 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits +system.l2c.overall_hits::cpu0.data 25477 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits +system.l2c.overall_hits::cpu1.data 20183 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits +system.l2c.overall_hits::total 274257 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3079 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6828 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 144642 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # 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number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses -system.l2c.demand_misses::total 195660 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 831 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7232 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 26632 # number of demand (read+write) misses +system.l2c.demand_misses::total 195290 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses -system.l2c.overall_misses::cpu0.data 13182 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2688,58 +2721,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228475 # Transaction distribution -system.membus.trans_dist::ReadResp 228474 # Transaction distribution -system.membus.trans_dist::WriteReq 31175 # Transaction distribution -system.membus.trans_dist::WriteResp 31175 # Transaction distribution -system.membus.trans_dist::Writeback 99922 # Transaction distribution +system.membus.trans_dist::ReadReq 228161 # Transaction distribution +system.membus.trans_dist::ReadResp 228160 # Transaction distribution +system.membus.trans_dist::WriteReq 31188 # Transaction distribution +system.membus.trans_dist::WriteResp 31188 # Transaction distribution +system.membus.trans_dist::Writeback 135887 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution +system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28459 # Transaction distribution -system.membus.trans_dist::ReadExResp 11563 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 28446 # Transaction distribution +system.membus.trans_dist::ReadExResp 11501 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129134 # Total snoops (count) -system.membus.snoop_fanout::samples 475892 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 129157 # Total snoops (count) +system.membus.snoop_fanout::samples 511174 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 475892 # Request fanout histogram -system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511174 # Request fanout histogram +system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2772,44 +2805,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 305031 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 304478 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4e27b0ea0..5265a0ac0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,123 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902619 # Number of seconds simulated -sim_ticks 2902619131000 # Number of ticks simulated -final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902845 # Number of seconds simulated +sim_ticks 2902845442000 # Number of ticks simulated +final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 783857 # Simulator instruction rate (inst/s) -host_op_rate 945096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20223090080 # Simulator tick rate (ticks/s) -host_mem_usage 560080 # Number of bytes of host memory used -host_seconds 143.53 # Real time elapsed on the host -sim_insts 112507011 # Number of instructions simulated -sim_ops 135649580 # Number of ops (including micro ops) simulated +host_inst_rate 666753 # Simulator instruction rate (inst/s) +host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17201244826 # Simulator tick rate (ticks/s) +host_mem_usage 558784 # Number of bytes of host memory used +host_seconds 168.76 # Real time elapsed on the host +sim_insts 112519801 # Number of instructions simulated +sim_ops 135665611 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory +system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168277 # Number of read requests accepted -system.physmem.writeReqs 122785 # Number of write requests accepted -system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue -system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9709 # Per bank write bursts -system.physmem.perBankRdBursts::1 9253 # Per bank write bursts -system.physmem.perBankRdBursts::2 10215 # Per bank write bursts -system.physmem.perBankRdBursts::3 10266 # Per bank write bursts -system.physmem.perBankRdBursts::4 18988 # Per bank write bursts -system.physmem.perBankRdBursts::5 10225 # Per bank write bursts -system.physmem.perBankRdBursts::6 10580 # Per bank write bursts -system.physmem.perBankRdBursts::7 10353 # Per bank write bursts -system.physmem.perBankRdBursts::8 9698 # Per bank write bursts -system.physmem.perBankRdBursts::9 9938 # Per bank write bursts -system.physmem.perBankRdBursts::10 9924 # Per bank write bursts -system.physmem.perBankRdBursts::11 8855 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10410 # Per bank write bursts -system.physmem.perBankRdBursts::14 9933 # Per bank write bursts -system.physmem.perBankRdBursts::15 9763 # Per bank write bursts -system.physmem.perBankWrBursts::0 7210 # Per bank write bursts -system.physmem.perBankWrBursts::1 6831 # Per bank write bursts -system.physmem.perBankWrBursts::2 8029 # Per bank write bursts -system.physmem.perBankWrBursts::3 7890 # Per bank write bursts -system.physmem.perBankWrBursts::4 7400 # Per bank write bursts -system.physmem.perBankWrBursts::5 7418 # Per bank write bursts -system.physmem.perBankWrBursts::6 7750 # Per bank write bursts -system.physmem.perBankWrBursts::7 7625 # Per bank write bursts -system.physmem.perBankWrBursts::8 7363 # Per bank write bursts -system.physmem.perBankWrBursts::9 7566 # Per bank write bursts -system.physmem.perBankWrBursts::10 7503 # Per bank write bursts -system.physmem.perBankWrBursts::11 6751 # Per bank write bursts -system.physmem.perBankWrBursts::12 7436 # Per bank write bursts -system.physmem.perBankWrBursts::13 7741 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts -system.physmem.perBankWrBursts::15 7101 # Per bank write bursts +system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168002 # Number of read requests accepted +system.physmem.writeReqs 158976 # Number of write requests accepted +system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9689 # Per bank write bursts +system.physmem.perBankRdBursts::1 9233 # Per bank write bursts +system.physmem.perBankRdBursts::2 10196 # Per bank write bursts +system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::4 18984 # Per bank write bursts +system.physmem.perBankRdBursts::5 10217 # Per bank write bursts +system.physmem.perBankRdBursts::6 10550 # Per bank write bursts +system.physmem.perBankRdBursts::7 10349 # Per bank write bursts +system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::9 9930 # Per bank write bursts +system.physmem.perBankRdBursts::10 9906 # Per bank write bursts +system.physmem.perBankRdBursts::11 8846 # Per bank write bursts +system.physmem.perBankRdBursts::12 9937 # Per bank write bursts +system.physmem.perBankRdBursts::13 10409 # Per bank write bursts +system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::15 9750 # Per bank write bursts +system.physmem.perBankWrBursts::0 9383 # Per bank write bursts +system.physmem.perBankWrBursts::1 8873 # Per bank write bursts +system.physmem.perBankWrBursts::2 10202 # Per bank write bursts +system.physmem.perBankWrBursts::3 10003 # Per bank write bursts +system.physmem.perBankWrBursts::4 9293 # Per bank write bursts +system.physmem.perBankWrBursts::5 9372 # Per bank write bursts +system.physmem.perBankWrBursts::6 9902 # Per bank write bursts +system.physmem.perBankWrBursts::7 9747 # Per bank write bursts +system.physmem.perBankWrBursts::8 9662 # Per bank write bursts +system.physmem.perBankWrBursts::9 9936 # Per bank write bursts +system.physmem.perBankWrBursts::10 9764 # Per bank write bursts +system.physmem.perBankWrBursts::11 9057 # Per bank write bursts +system.physmem.perBankWrBursts::12 9756 # Per bank write bursts +system.physmem.perBankWrBursts::13 9847 # Per bank write bursts +system.physmem.perBankWrBursts::14 9332 # Per bank write bursts +system.physmem.perBankWrBursts::15 9055 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2902618754500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2902845065500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158705 # Read request sizes (log2) +system.physmem.readPktSize::6 158430 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118404 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154595 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -162,157 +159,153 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5064 86.37% 86.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 42 0.72% 87.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 216 3.68% 91.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 215 3.67% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 12 0.20% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.27% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 164 2.80% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads -system.physmem.totQLat 1491102500 # Total ticks spent queuing -system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads +system.physmem.totQLat 1496514000 # Total ticks spent queuing +system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing -system.physmem.readRowHits 138436 # Number of row buffer hits during reads -system.physmem.writeRowHits 90002 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.avgGap 9972510.17 # Average gap between requests -system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states -system.physmem.memoryStateTime::REF 96924620000 # Time in different power states +system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing +system.physmem.readRowHits 138272 # Number of row buffer hits during reads +system.physmem.writeRowHits 122158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes +system.physmem.avgGap 8877799.32 # Average gap between requests +system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states +system.physmem.memoryStateTime::REF 96932160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states +system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.480387 # Core power per rank (mW) -system.physmem.averagePower::1 669.392153 # Core power per rank (mW) +system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.521448 # Core power per rank (mW) +system.physmem.averagePower::1 669.438449 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -355,25 +348,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24532671 # DTB read hits -system.cpu.dtb.read_misses 8148 # DTB read misses -system.cpu.dtb.write_hits 19614515 # DTB write hits +system.cpu.dtb.read_hits 24536392 # DTB read hits +system.cpu.dtb.read_misses 8144 # DTB read misses +system.cpu.dtb.write_hits 19617454 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24540819 # DTB read accesses -system.cpu.dtb.write_accesses 19615925 # DTB write accesses +system.cpu.dtb.read_accesses 24544536 # DTB read accesses +system.cpu.dtb.write_accesses 19618864 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44147186 # DTB hits -system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 44156744 # DTB accesses +system.cpu.dtb.hits 44153846 # DTB hits +system.cpu.dtb.misses 9554 # DTB misses +system.cpu.dtb.accesses 44163400 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -395,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115605918 # ITB inst hits +system.cpu.itb.inst_hits 115618887 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -412,38 +405,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115610680 # ITB inst accesses -system.cpu.itb.hits 115605918 # DTB hits +system.cpu.itb.inst_accesses 115623649 # ITB inst accesses +system.cpu.itb.hits 115618887 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115610680 # DTB accesses -system.cpu.numCycles 5805238262 # number of cpu cycles simulated +system.cpu.itb.accesses 115623649 # DTB accesses +system.cpu.numCycles 5805690884 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112507011 # Number of instructions committed -system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9898964 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls -system.cpu.num_int_insts 119948946 # number of integer instructions -system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read -system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read +system.cpu.committedInsts 112519801 # Number of instructions committed +system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses +system.cpu.num_func_calls 9899743 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls +system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_fp_insts 11290 # number of float instructions +system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read +system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written -system.cpu.num_mem_refs 45428250 # number of memory refs -system.cpu.num_load_insts 24855398 # Number of load instructions -system.cpu.num_store_insts 20572852 # Number of store instructions -system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles -system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927862 # Percentage of idle cycles -system.cpu.Branches 25929462 # Number of branches fetched +system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written +system.cpu.num_mem_refs 45435185 # number of memory refs +system.cpu.num_load_insts 24859277 # Number of load instructions +system.cpu.num_store_insts 20575908 # Number of store instructions +system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles +system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927850 # Percentage of idle cycles +system.cpu.Branches 25931479 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -467,24 +460,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138771647 # Class of executed instruction +system.cpu.op_class::total 138788018 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 822746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 823273 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -493,88 +486,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015632 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233063 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.233063 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048675 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # 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average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25046.697045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21410.502321 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked @@ -583,78 +576,78 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 701068 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 701068 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 818089 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 818089 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5096620250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5096620250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11004051747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11004051747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1414370750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1414370750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99646250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99646250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16100671997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16100671997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17515042747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17515042747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791399500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791399500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221078000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -662,13 +655,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699818 # number of replacements -system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1700967 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -677,44 +670,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113905582 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23258305750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23258305750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23258305750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23258305750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23258305750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23258305750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115618887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115618887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115618887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115618887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115618887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115618887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.415687 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13669.415687 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13669.415687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13669.415687 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,196 +716,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # 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number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1701485 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1701485 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1701485 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1701485 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1701485 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19848767250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19848767250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19848767250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19848767250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19848767250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19848767250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # 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Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6954 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56136 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1024,59 +1017,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 52963 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53126 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1167,42 +1161,44 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1213,104 +1209,114 @@ system.iocache.overall_accesses::realview.ide 234 system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70649 # Transaction distribution -system.membus.trans_dist::ReadResp 70649 # Transaction distribution +system.membus.trans_dist::ReadReq 70650 # Transaction distribution +system.membus.trans_dist::ReadResp 70650 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 82180 # Transaction distribution +system.membus.trans_dist::Writeback 118371 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128451 # Transaction distribution -system.membus.trans_dist::ReadExResp 128451 # Transaction distribution +system.membus.trans_dist::ReadExReq 128452 # Transaction distribution +system.membus.trans_dist::ReadExResp 128452 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 281834 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 318026 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 281834 # Request fanout histogram -system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index cdf4d3024..b2b55eb3a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,76 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783854 # Number of seconds simulated -sim_ticks 2783854461500 # Number of ticks simulated -final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783867 # Number of seconds simulated +sim_ticks 2783867165000 # Number of ticks simulated +final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108552 # Simulator instruction rate (inst/s) -host_op_rate 1349484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21615280295 # Simulator tick rate (ticks/s) -host_mem_usage 562164 # Number of bytes of host memory used -host_seconds 128.79 # Real time elapsed on the host -sim_insts 142771592 # Number of instructions simulated -sim_ops 173801445 # Number of ops (including micro ops) simulated +host_inst_rate 1108011 # Simulator instruction rate (inst/s) +host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21604583679 # Simulator tick rate (ticks/s) +host_mem_usage 560868 # Number of bytes of host memory used +host_seconds 128.86 # Real time elapsed on the host +sim_insts 142773109 # Number of instructions simulated +sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4668256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 728420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5677316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 728420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837248 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory -system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory +system.physmem.bytes_written::total 8854772 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189290 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138082 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142463 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2039372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4151806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2342490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174450 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2342490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180745 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174450 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2039375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7333370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326164 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -113,25 +110,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997075 # DTB read hits -system.cpu0.dtb.read_misses 4808 # DTB read misses -system.cpu0.dtb.write_hits 11281657 # DTB write hits -system.cpu0.dtb.write_misses 898 # DTB write misses +system.cpu0.dtb.read_hits 15994592 # DTB read hits +system.cpu0.dtb.read_misses 4787 # DTB read misses +system.cpu0.dtb.write_hits 11285776 # DTB write hits +system.cpu0.dtb.write_misses 895 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3233 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 774 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16001883 # DTB read accesses -system.cpu0.dtb.write_accesses 11282555 # DTB write accesses +system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 15999379 # DTB read accesses +system.cpu0.dtb.write_accesses 11286671 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278732 # DTB hits -system.cpu0.dtb.misses 5706 # DTB misses -system.cpu0.dtb.accesses 27284438 # DTB accesses +system.cpu0.dtb.hits 27280368 # DTB hits +system.cpu0.dtb.misses 5682 # DTB misses +system.cpu0.dtb.accesses 27286050 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -153,189 +150,189 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 74797961 # ITB inst hits -system.cpu0.itb.inst_misses 2591 # ITB inst misses +system.cpu0.itb.inst_hits 74779253 # ITB inst hits +system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1908 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1917 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800552 # ITB inst accesses -system.cpu0.itb.hits 74797961 # DTB hits -system.cpu0.itb.misses 2591 # DTB misses -system.cpu0.itb.accesses 74800552 # DTB accesses -system.cpu0.numCycles 5536444794 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74781864 # ITB inst accesses +system.cpu0.itb.hits 74779253 # DTB hits +system.cpu0.itb.misses 2611 # DTB misses +system.cpu0.itb.accesses 74781864 # DTB accesses +system.cpu0.numCycles 5536444795 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72639396 # Number of instructions committed -system.cpu0.committedOps 87981758 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77492054 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses -system.cpu0.num_func_calls 8694368 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459714 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77492054 # number of integer instructions -system.cpu0.num_fp_insts 5289 # number of float instructions -system.cpu0.num_int_register_reads 144071276 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447497 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268879516 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833951 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909687 # number of memory refs -system.cpu0.num_load_insts 16164649 # Number of load instructions -system.cpu0.num_store_insts 11745038 # Number of store instructions -system.cpu0.num_idle_cycles 5353616424.336780 # Number of idle cycles -system.cpu0.num_busy_cycles 182828369.663220 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles -system.cpu0.Branches 18600789 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776684 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction +system.cpu0.committedInsts 72626511 # Number of instructions committed +system.cpu0.committedOps 87972361 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77485845 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5272 # Number of float alu accesses +system.cpu0.num_func_calls 8692455 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9458284 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77485845 # number of integer instructions +system.cpu0.num_fp_insts 5272 # number of float instructions +system.cpu0.num_int_register_reads 144065543 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54441741 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4114 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 268855206 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31825195 # number of times the CC registers were written +system.cpu0.num_mem_refs 27911692 # number of memory refs +system.cpu0.num_load_insts 16162187 # Number of load instructions +system.cpu0.num_store_insts 11749505 # Number of store instructions +system.cpu0.num_idle_cycles 5353607103.050808 # Number of idle cycles +system.cpu0.num_busy_cycles 182837691.949192 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles +system.cpu0.Branches 18597060 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61764761 68.82% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59661 0.07% 68.89% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4406 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164649 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16162187 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11749505 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752652 # Class of executed instruction +system.cpu0.op_class::total 89742709 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 819395 # number of replacements +system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 819403 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783754 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819907 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597384 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53784478 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597627 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830585 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166589 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821680 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234631 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234631 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305258 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14823504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128762 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894595 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445159 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209287 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395042 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234989 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222327 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236688 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223434 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26199853 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268663 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468516 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385608 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477950 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863558 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197451 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198871 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396322 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137556 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164107 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61720 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 219237567 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219237567 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15302739 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14826353 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30129092 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10898468 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11441639 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186053 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209002 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395055 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235062 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222268 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236768 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223368 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 26201207 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26267992 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52469199 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26387260 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26476994 # number of overall hits +system.cpu0.dcache.overall_hits::total 52864254 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197067 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199240 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396307 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137729 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 163949 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54389 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61684 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335007 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362978 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 334796 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363189 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 697985 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389352 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424698 # number of overall misses -system.cpu0.dcache.overall_misses::total 814050 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032151 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609266 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239652 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226293 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236688 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223436 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26534860 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631641 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26774960 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902648 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677608 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012737 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses +system.cpu0.dcache.overall_misses::cpu0.data 389185 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424873 # number of overall misses +system.cpu0.dcache.overall_misses::total 814058 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499806 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025593 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036197 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605588 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240442 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270686 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511128 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239724 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236768 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223370 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 26536003 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631181 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26776445 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26901867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53678312 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012469 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014136 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012480 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014127 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227743 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227086 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226204 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227880 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227092 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019447 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013630 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013638 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,19 +341,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682260 # number of writebacks -system.cpu0.dcache.writebacks::total 682260 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682284 # number of writebacks +system.cpu0.dcache.writebacks::total 682284 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699006 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341690 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1699220 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 145342961 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121641 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542038 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127365 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110422 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -364,44 +361,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740738 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740738 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955769 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71385921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341690 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955769 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71385921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341690 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955769 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71385921 # number of overall hits -system.cpu0.icache.overall_hits::total 145341690 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844069 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855455 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699524 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844069 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855455 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699524 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844069 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855455 # number of overall misses -system.cpu0.icache.overall_misses::total 1699524 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799838 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241376 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799838 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72241376 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799838 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72241376 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 148742437 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148742437 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73936562 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71406399 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145342961 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73936562 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71406399 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145342961 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73936562 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71406399 # number of overall hits +system.cpu0.icache.overall_hits::total 145342961 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844577 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855161 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699738 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844577 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855161 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699738 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844577 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855161 # number of overall misses +system.cpu0.icache.overall_misses::total 1699738 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74781139 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261560 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74781139 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72261560 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74781139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72261560 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011834 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011834 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011834 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,25 +431,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15527184 # DTB read hits -system.cpu1.dtb.read_misses 5393 # DTB read misses -system.cpu1.dtb.write_hits 11842180 # DTB write hits -system.cpu1.dtb.write_misses 794 # DTB write misses +system.cpu1.dtb.read_hits 15530019 # DTB read hits +system.cpu1.dtb.read_misses 5412 # DTB read misses +system.cpu1.dtb.write_hits 11838449 # DTB write hits +system.cpu1.dtb.write_misses 791 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3187 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15532577 # DTB read accesses -system.cpu1.dtb.write_accesses 11842974 # DTB write accesses +system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 15535431 # DTB read accesses +system.cpu1.dtb.write_accesses 11839240 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27369364 # DTB hits -system.cpu1.dtb.misses 6187 # DTB misses -system.cpu1.dtb.accesses 27375551 # DTB accesses +system.cpu1.dtb.hits 27368468 # DTB hits +system.cpu1.dtb.misses 6203 # DTB misses +system.cpu1.dtb.accesses 27374671 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -474,87 +471,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 72239267 # ITB inst hits -system.cpu1.itb.inst_misses 3050 # ITB inst misses +system.cpu1.itb.inst_hits 72259450 # ITB inst hits +system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2020 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72242317 # ITB inst accesses -system.cpu1.itb.hits 72239267 # DTB hits -system.cpu1.itb.misses 3050 # DTB misses -system.cpu1.itb.accesses 72242317 # DTB accesses -system.cpu1.numCycles 88015463 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72262490 # ITB inst accesses +system.cpu1.itb.hits 72259450 # DTB hits +system.cpu1.itb.misses 3040 # DTB misses +system.cpu1.itb.accesses 72262490 # DTB accesses +system.cpu1.numCycles 88040872 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70132196 # Number of instructions committed -system.cpu1.committedOps 85819687 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75669045 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses -system.cpu1.num_func_calls 8179506 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270587 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75669045 # number of integer instructions -system.cpu1.num_fp_insts 6195 # number of float instructions -system.cpu1.num_int_register_reads 140985974 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52730811 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261969583 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30530010 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028916 # number of memory refs -system.cpu1.num_load_insts 15690946 # Number of load instructions -system.cpu1.num_store_insts 12337970 # Number of store instructions -system.cpu1.num_idle_cycles 85360794.411583 # Number of idle cycles -system.cpu1.num_busy_cycles 2654668.588417 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17796134 # Number of branches fetched -system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59375218 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690946 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12337970 14.11% 100.00% # Class of executed instruction +system.cpu1.committedInsts 70146598 # Number of instructions committed +system.cpu1.committedOps 85830973 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75676981 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6212 # Number of float alu accesses +system.cpu1.num_func_calls 8181424 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9272106 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75676981 # number of integer instructions +system.cpu1.num_fp_insts 6212 # number of float instructions +system.cpu1.num_int_register_reads 140994581 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52737823 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4658 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 261999475 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30539263 # number of times the CC registers were written +system.cpu1.num_mem_refs 28027673 # number of memory refs +system.cpu1.num_load_insts 15693775 # Number of load instructions +system.cpu1.num_store_insts 12333898 # Number of store instructions +system.cpu1.num_idle_cycles 85385179.520823 # Number of idle cycles +system.cpu1.num_busy_cycles 2655692.479177 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles +system.cpu1.Branches 17799968 # Number of branches fetched +system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59388214 67.89% 67.89% # Class of executed instruction +system.cpu1.op_class::IntMult 57231 0.07% 67.96% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4163 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::MemRead 15693775 17.94% 85.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 12333898 14.10% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87465632 # Class of executed instruction +system.cpu1.op_class::total 87477429 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30171 # Transaction distribution @@ -613,23 +610,23 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses @@ -644,6 +641,8 @@ system.iocache.overall_accesses::realview.ide 240 system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -654,31 +653,33 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 36224 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.314991 # Cycle average of tags in use -system.l2c.tags.total_refs 2731075 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.309065 # Cycle average of tags in use +system.l2c.tags.total_refs 2731330 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.579258 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 15.580712 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.450285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.434420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.246320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.238679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.359026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.332054 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.302070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.174515 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4020.194257 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.086185 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076969 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.076971 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072164 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037599 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id @@ -690,144 +691,144 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26229756 # Number of tag accesses -system.l2c.tags.data_accesses 26229756 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833265 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847884 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 258778 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201051 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682260 # number of Writeback hits -system.l2c.Writeback_hits::total 682260 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 26231923 # Number of tag accesses +system.l2c.tags.data_accesses 26231923 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4699 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833747 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 847615 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 259132 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201281 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682284 # number of Writeback hits +system.l2c.Writeback_hits::total 682284 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72325 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151043 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847884 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337496 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352094 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4719 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833265 # number of overall hits -system.l2c.overall_hits::cpu0.data 319034 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847884 # number of overall hits -system.l2c.overall_hits::cpu1.data 337496 # number of overall hits -system.l2c.overall_hits::total 2352094 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 72504 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4699 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833747 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318852 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337686 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352339 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4699 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833747 # number of overall hits +system.l2c.overall_hits::cpu0.data 318852 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5000 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847615 # number of overall hits +system.l2c.overall_hits::cpu1.data 337686 # number of overall hits +system.l2c.overall_hits::total 2352339 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10820 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 7538 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5759 # number of ReadReq misses system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83894 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63963 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83901 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73720 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10820 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73733 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89673 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89660 # number of demand (read+write) misses system.l2c.demand_misses::total 181759 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses -system.l2c.overall_misses::cpu0.data 73720 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10820 # number of overall misses +system.l2c.overall_misses::cpu0.data 73733 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses -system.l2c.overall_misses::cpu1.data 89673 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7538 # number of overall misses +system.l2c.overall_misses::cpu1.data 89660 # number of overall misses system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844060 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256459 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855447 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264557 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682260 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682260 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4704 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844567 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256118 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855153 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264891 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2235176 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682284 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682284 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136295 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162612 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4724 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844060 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855447 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427169 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533853 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4724 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844060 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855447 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427169 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533853 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 136467 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162455 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844567 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392585 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855153 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427346 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534098 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4704 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2288 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844567 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392585 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855153 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427346 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534098 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038018 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021844 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.012811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008815 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021741 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469350 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515915 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for demand accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.516457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187700 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209924 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209807 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071725 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187700 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209924 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209807 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071725 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -836,14 +837,14 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101893 # number of writebacks -system.l2c.writebacks::total 101893 # number of writebacks +system.l2c.writebacks::writebacks 101892 # number of writebacks +system.l2c.writebacks::total 101892 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 74229 # Transaction distribution system.membus.trans_dist::ReadResp 74229 # Transaction distribution system.membus.trans_dist::WriteReq 27560 # Transaction distribution system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 101893 # Transaction distribution +system.membus.trans_dist::Writeback 138082 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -854,31 +855,31 @@ system.membus.trans_dist::ReadExResp 146085 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 715296 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22908547 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 322846 # Request fanout histogram +system.membus.snoop_fanout::samples 359035 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 322846 # Request fanout histogram +system.membus.snoop_fanout::total 359035 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -910,41 +911,41 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2291800 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291800 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291995 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291995 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682260 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682284 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444886 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41566 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924310 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322507 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83132 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205252795 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36632 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272095 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20800 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924754 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324555 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205268491 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 36631 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3272329 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011143 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235631 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3235865 98.89% 98.89% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272095 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272329 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 27931ceba..818a22f67 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,80 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.256536 # Number of seconds simulated -sim_ticks 47256535568000 # Number of ticks simulated -final_tick 47256535568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.177080 # Number of seconds simulated +sim_ticks 47177080006500 # Number of ticks simulated +final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272324 # Simulator instruction rate (inst/s) -host_op_rate 1496823 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61628014219 # Simulator tick rate (ticks/s) -host_mem_usage 661604 # Number of bytes of host memory used -host_seconds 766.80 # Real time elapsed on the host -sim_insts 975621413 # Number of instructions simulated -sim_ops 1147767763 # Number of ops (including micro ops) simulated +host_inst_rate 1024538 # Simulator instruction rate (inst/s) +host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49483118923 # Simulator tick rate (ticks/s) +host_mem_usage 669884 # Number of bytes of host memory used +host_seconds 953.40 # Real time elapsed on the host +sim_insts 976792036 # Number of instructions simulated +sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 442560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 277248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 420864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3534260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43570904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 363264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 549184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2429256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 46602048 # Number of bytes read from this memory -system.physmem.bytes_read::total 98189588 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3534260 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2429256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5963516 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 63972864 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 69325260 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 32048196 # Number of bytes written to this memory -system.physmem.bytes_written::total 172176912 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4332 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 680817 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5676 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 8581 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 728175 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1574766 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 999576 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1085484 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 500754 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2692542 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 9365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 5867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 922008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 7687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 11621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 986150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2077799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 126195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1353736 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144543 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1466998 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 678175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3643452 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1353736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 153908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 5867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2389006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 7687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 11621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1664325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5721251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory +system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -101,372 +98,13 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 626516 # Transaction distribution -system.membus.trans_dist::ReadResp 626516 # Transaction distribution -system.membus.trans_dist::WriteReq 38984 # Transaction distribution -system.membus.trans_dist::WriteResp 38984 # Transaction distribution -system.membus.trans_dist::Writeback 999576 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1690363 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1690363 # Transaction distribution -system.membus.trans_dist::UpgradeReq 306222 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 316965 # Transaction distribution -system.membus.trans_dist::UpgradeResp 140146 # Transaction distribution -system.membus.trans_dist::ReadExReq 1165491 # Transaction distribution -system.membus.trans_dist::ReadExResp 989253 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8247325 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 8398069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 231310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 8629379 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156015 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 263093540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 263305247 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7401728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7401728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 270706975 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5022881 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5022881 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5022881 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1283901 # number of replacements -system.l2c.tags.tagsinuse 62124.562993 # Cycle average of tags in use -system.l2c.tags.total_refs 3275357 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1342128 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.440421 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34388.760809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 79.804579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 112.289142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3576.253573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7600.803334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 295.890565 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 418.894238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2948.167503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 12703.699250 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.524731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001218 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001713 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.115979 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004515 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006392 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.193843 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947946 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 419 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 57808 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 357 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2958 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4258 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50148 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.006393 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.882080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65498174 # Number of tag accesses -system.l2c.tags.data_accesses 65498174 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5628 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 452773 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 684956 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4751 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2824 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 443971 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 629104 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2227532 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2009484 # number of Writeback hits -system.l2c.Writeback_hits::total 2009484 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14899 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10552 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 25451 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1377 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1186 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2563 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 159390 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 142180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 301570 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5628 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3525 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 452773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 844346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4751 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2824 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 443971 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 771284 # number of demand (read+write) hits -system.l2c.demand_hits::total 2529102 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5628 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3525 # number of overall hits -system.l2c.overall_hits::cpu0.inst 452773 # number of overall hits -system.l2c.overall_hits::cpu0.data 844346 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4751 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2824 # number of overall hits -system.l2c.overall_hits::cpu1.inst 443971 # number of overall hits -system.l2c.overall_hits::cpu1.data 771284 # number of overall hits -system.l2c.overall_hits::total 2529102 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4332 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6576 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 52529 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 192774 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5676 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 8581 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 37950 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 226922 # number of ReadReq misses -system.l2c.ReadReq_misses::total 535340 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 55008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 52026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 107034 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7689 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 15790 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 497215 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 509357 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 1006572 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 4332 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6576 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 52529 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 689989 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5676 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 8581 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 37950 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 736279 # number of demand (read+write) misses -system.l2c.demand_misses::total 1541912 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 4332 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6576 # number of overall misses -system.l2c.overall_misses::cpu0.inst 52529 # number of overall misses -system.l2c.overall_misses::cpu0.data 689989 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5676 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 8581 # number of overall misses -system.l2c.overall_misses::cpu1.inst 37950 # number of overall misses -system.l2c.overall_misses::cpu1.data 736279 # number of overall misses -system.l2c.overall_misses::total 1541912 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9960 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10101 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 505302 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 877730 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 11405 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 481921 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 856026 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2762872 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2009484 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2009484 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 69907 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 62578 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 132485 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9478 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8875 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18353 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 656605 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 651537 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1308142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10101 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 505302 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1534335 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 11405 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 481921 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1507563 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4071014 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10101 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 505302 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1534335 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 11405 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 481921 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1507563 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4071014 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.651025 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.103956 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.219628 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.752389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.078747 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.265088 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.193762 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.786874 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831378 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.807895 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.854716 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.866366 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.860350 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.757251 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.781778 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.769467 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.651025 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.103956 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.449699 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.752389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.078747 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.488390 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.378754 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.434940 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.651025 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.103956 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.449699 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.544356 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.752389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.078747 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.488390 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.378754 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 999576 # number of writebacks -system.l2c.writebacks::total 999576 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 3538474 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3538474 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38984 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38984 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2009484 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1583635 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1583635 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 314351 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 319528 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 633879 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1484380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1484380 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9022261 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7545927 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16568188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295040248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 251523687 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 546563935 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117027 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9283255 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012458 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110920 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9167600 98.75% 98.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115655 1.25% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9283255 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40365 # Transaction distribution -system.iobus.trans_dist::ReadResp 40365 # Transaction distribution -system.iobus.trans_dist::WriteReq 136744 # Transaction distribution -system.iobus.trans_dist::WriteResp 30016 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47974 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122908 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354218 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156015 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497037 # Cumulative packet size per connected master and slave (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -490,25 +128,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91995299 # DTB read hits -system.cpu0.dtb.read_misses 88130 # DTB read misses -system.cpu0.dtb.write_hits 85085254 # DTB write hits -system.cpu0.dtb.write_misses 36248 # DTB write misses +system.cpu0.dtb.read_hits 91355479 # DTB read hits +system.cpu0.dtb.read_misses 87819 # DTB read misses +system.cpu0.dtb.write_hits 84601943 # DTB write hits +system.cpu0.dtb.write_misses 36095 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36322 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5755 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92083429 # DTB read accesses -system.cpu0.dtb.write_accesses 85121502 # DTB write accesses +system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91443298 # DTB read accesses +system.cpu0.dtb.write_accesses 84638038 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 177080553 # DTB hits -system.cpu0.dtb.misses 124378 # DTB misses -system.cpu0.dtb.accesses 177204931 # DTB accesses +system.cpu0.dtb.hits 175957422 # DTB hits +system.cpu0.dtb.misses 123914 # DTB misses +system.cpu0.dtb.accesses 176081336 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -530,56 +168,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 494454438 # ITB inst hits -system.cpu0.itb.inst_misses 60733 # ITB inst misses +system.cpu0.itb.inst_hits 491372488 # ITB inst hits +system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 494515171 # ITB inst accesses -system.cpu0.itb.hits 494454438 # DTB hits -system.cpu0.itb.misses 60733 # DTB misses -system.cpu0.itb.accesses 494515171 # DTB accesses -system.cpu0.numCycles 94513084496 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses +system.cpu0.itb.hits 491372488 # DTB hits +system.cpu0.itb.misses 60226 # DTB misses +system.cpu0.itb.accesses 491432714 # DTB accesses +system.cpu0.numCycles 94354173207 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 494220811 # Number of instructions committed -system.cpu0.committedOps 581241865 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 532688106 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 523244 # Number of float alu accesses -system.cpu0.num_func_calls 28754565 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75974563 # number of instructions that are conditional controls -system.cpu0.num_int_insts 532688106 # number of integer instructions -system.cpu0.num_fp_insts 523244 # number of float instructions -system.cpu0.num_int_register_reads 780601008 # number of times the integer registers were read -system.cpu0.num_int_register_writes 422746088 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 843511 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 445224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132982110 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132652018 # number of times the CC registers were written -system.cpu0.num_mem_refs 177182019 # number of memory refs -system.cpu0.num_load_insts 92069289 # Number of load instructions -system.cpu0.num_store_insts 85112730 # Number of store instructions -system.cpu0.num_idle_cycles 93931506106.304367 # Number of idle cycles -system.cpu0.num_busy_cycles 581578389.695634 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles -system.cpu0.Branches 110567100 # Number of branches fetched +system.cpu0.committedInsts 491139120 # Number of instructions committed +system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses +system.cpu0.num_func_calls 28573576 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls +system.cpu0.num_int_insts 529301791 # number of integer instructions +system.cpu0.num_fp_insts 523058 # number of float instructions +system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read +system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written +system.cpu0.num_mem_refs 176058068 # number of memory refs +system.cpu0.num_load_insts 91428761 # Number of load instructions +system.cpu0.num_store_insts 84629307 # Number of store instructions +system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles +system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles +system.cpu0.Branches 109891880 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 403026584 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1232662 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59598 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction +system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction +system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction @@ -602,57 +240,149 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Cl system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 92069289 15.83% 85.37% # Class of executed instruction -system.cpu0.op_class::MemWrite 85112730 14.63% 100.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 581573977 # Class of executed instruction +system.cpu0.op_class::total 577906497 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13359 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 5478973 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 489030308 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5479485 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.247495 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 6189405 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits +system.cpu0.dcache.overall_hits::total 165054680 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses +system.cpu0.dcache.overall_misses::total 5485788 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks +system.cpu0.dcache.writebacks::total 4407988 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 5467768 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 994499086 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 994499086 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 489030308 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 489030308 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 489030308 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 489030308 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 489030308 # number of overall hits -system.cpu0.icache.overall_hits::total 489030308 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5479490 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5479490 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5479490 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5479490 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5479490 # number of overall misses -system.cpu0.icache.overall_misses::total 5479490 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 494509798 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 494509798 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 494509798 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 494509798 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 494509798 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 494509798 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011081 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011081 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011081 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011081 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011081 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011081 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits +system.cpu0.icache.overall_hits::total 485959047 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses +system.cpu0.icache.overall_misses::total 5468285 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -671,125 +401,132 @@ system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 2064608 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16133.195391 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11362943 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2080515 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.461601 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4425944000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5245.148106 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.593184 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.054087 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4630.109792 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6116.290221 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.320138 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003820 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004825 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.282599 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.373309 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984692 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15804 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 74 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 2648971 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4606 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5039 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5169 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.964600 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 268288822 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 268288822 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 268797 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139678 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4974188 # 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number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 268797 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 139678 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4974188 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3538402 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8921065 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12357 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10472 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 505302 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1208839 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1736970 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125739 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 125739 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158665 # 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number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5479490 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5526325 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11437119 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043951 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.069744 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.092217 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.288973 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.172079 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.970411 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.970411 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # 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number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.580063 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.580063 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043951 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.069744 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092217 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.359719 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.219990 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043951 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.069744 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092217 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.359719 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.219990 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -798,134 +535,47 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1036299 # number of writebacks -system.cpu0.l2cache.writebacks::total 1036299 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks +system.cpu0.l2cache.writebacks::total 1542533 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 6244160 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.112038 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 170764768 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6244672 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.345675 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.112038 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978734 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978734 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 360574457 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 360574457 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85562109 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85562109 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80321665 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80321665 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214579 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214579 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1082882 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1082882 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079487 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2079487 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2037790 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2037790 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165883774 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165883774 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 166098353 # number of overall hits -system.cpu0.dcache.overall_hits::total 166098353 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3290675 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3290675 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1472676 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1472676 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774388 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 774388 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 118159 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158665 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158665 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4763351 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4763351 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5537739 # number of overall misses -system.cpu0.dcache.overall_misses::total 5537739 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88852784 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88852784 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81794341 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81794341 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 988967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1082882 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1082882 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2196455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170647125 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 170647125 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171636092 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 171636092 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037035 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037035 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018005 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018005 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783027 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783027 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053766 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053766 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027913 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027913 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032264 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032264 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1082882 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3700491 # number of writebacks -system.cpu0.dcache.writebacks::total 3700491 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10282171 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10282171 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33363 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3700491 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1082882 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1082882 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 129573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158665 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 288238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1343103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1343103 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11045230 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17628413 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362824 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723538 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 29760005 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350859860 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 660019940 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1451296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2894152 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1015225248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3571522 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20011038 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.169428 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.375130 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 16620607 83.06% 83.06% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3390431 16.94% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20011038 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -949,25 +599,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90837844 # DTB read hits -system.cpu1.dtb.read_misses 112429 # DTB read misses -system.cpu1.dtb.write_hits 81788331 # DTB write hits -system.cpu1.dtb.write_misses 32675 # DTB write misses +system.cpu1.dtb.read_hits 91720002 # DTB read hits +system.cpu1.dtb.read_misses 112244 # DTB read misses +system.cpu1.dtb.write_hits 82499013 # DTB write hits +system.cpu1.dtb.write_misses 32608 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44635 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4658 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90950273 # DTB read accesses -system.cpu1.dtb.write_accesses 81821006 # DTB write accesses +system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91832246 # DTB read accesses +system.cpu1.dtb.write_accesses 82531621 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 172626175 # DTB hits -system.cpu1.dtb.misses 145104 # DTB misses -system.cpu1.dtb.accesses 172771279 # DTB accesses +system.cpu1.dtb.hits 174219015 # DTB hits +system.cpu1.dtb.misses 144852 # DTB misses +system.cpu1.dtb.accesses 174363867 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -989,129 +639,219 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 481654104 # ITB inst hits -system.cpu1.itb.inst_misses 61573 # ITB inst misses +system.cpu1.itb.inst_hits 485906850 # ITB inst hits +system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 481715677 # ITB inst accesses -system.cpu1.itb.hits 481654104 # DTB hits -system.cpu1.itb.misses 61573 # DTB misses -system.cpu1.itb.accesses 481715677 # DTB accesses -system.cpu1.numCycles 94513077342 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses +system.cpu1.itb.hits 485906850 # DTB hits +system.cpu1.itb.misses 61939 # DTB misses +system.cpu1.itb.accesses 485968789 # DTB accesses +system.cpu1.numCycles 94354166192 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 481400602 # Number of instructions committed -system.cpu1.committedOps 566525898 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 519925383 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses -system.cpu1.num_func_calls 28379756 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 73707085 # number of instructions that are conditional controls -system.cpu1.num_int_insts 519925383 # number of integer instructions -system.cpu1.num_fp_insts 376275 # number of float instructions -system.cpu1.num_int_register_reads 767883598 # number of times the integer registers were read -system.cpu1.num_int_register_writes 413862248 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 127269525 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 126984366 # number of times the CC registers were written -system.cpu1.num_mem_refs 172747819 # number of memory refs -system.cpu1.num_load_insts 90937276 # Number of load instructions -system.cpu1.num_store_insts 81810543 # Number of store instructions -system.cpu1.num_idle_cycles 93946237892.041718 # Number of idle cycles -system.cpu1.num_busy_cycles 566839449.958294 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles -system.cpu1.Branches 107245418 # Number of branches fetched +system.cpu1.committedInsts 485652916 # Number of instructions committed +system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses +system.cpu1.num_func_calls 28666071 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls +system.cpu1.num_int_insts 524558211 # number of integer instructions +system.cpu1.num_fp_insts 375128 # number of float instructions +system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read +system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written +system.cpu1.num_mem_refs 174340371 # number of memory refs +system.cpu1.num_load_insts 91819242 # Number of load instructions +system.cpu1.num_store_insts 82521129 # Number of store instructions +system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles +system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles +system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles +system.cpu1.Branches 108195111 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 392850961 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1138465 0.20% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 60868 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 90937276 16.04% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 81810543 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction +system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 566834606 # Class of executed instruction +system.cpu1.op_class::total 571821232 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6205 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 4804797 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 476903871 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4805309 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.245204 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 6025220 # number of replacements +system.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits +system.cpu1.dcache.overall_hits::total 163704556 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses +system.cpu1.dcache.overall_misses::total 5666805 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks +system.cpu1.dcache.writebacks::total 4091318 # number of writebacks +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 4818195 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 968223669 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 968223669 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 476903871 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 476903871 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 476903871 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 476903871 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 476903871 # number of overall hits -system.cpu1.icache.overall_hits::total 476903871 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4805309 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4805309 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4805309 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4805309 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4805309 # 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number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses +system.cpu1.icache.overall_misses::total 4818707 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1130,125 +870,133 @@ system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 2006739 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13469.548164 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10823103 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2022814 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.350518 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 47068377163500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5364.772438 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.646390 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 85.907417 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2770.929506 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5181.292411 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.327440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004068 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005243 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.169124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.316241 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.822116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15986 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 2333825 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4461 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4985 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.975708 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249408047 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249408047 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323614 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138529 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4323388 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3090792 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7876323 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3626404 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3626404 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 4173 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 4173 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 550904 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 550904 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323614 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138529 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4323388 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3641696 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8427227 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 323614 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138529 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4323388 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3641696 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8427227 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13437 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11832 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 481921 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1212062 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1719252 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 130320 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 130320 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160863 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 160863 # 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miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1257,180 +1005,143 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 973185 # number of writebacks -system.cpu1.l2cache.writebacks::total 973185 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks +system.cpu1.l2cache.writebacks::total 1212706 # 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number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3626404 # number of writebacks -system.cpu1.dcache.writebacks::total 3626404 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 9718709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9718709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3626404 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 500753 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 500753 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 134493 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 160863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 295356 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1314492 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1314492 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9610878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16476244 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27296266 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 307540296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 623681695 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364200 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 936058567 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4159575 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19448735 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.205617 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.404152 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15449740 79.44% 79.44% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 3998995 20.56% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19448735 # Request fanout histogram -system.iocache.tags.replacements 115596 # number of replacements -system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use +system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution +system.iobus.trans_dist::WriteReq 136741 # Transaction distribution +system.iobus.trans_dist::WriteResp 30013 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115586 # number of replacements +system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040892 # Number of tag accesses -system.iocache.tags.data_accesses 1040892 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040802 # Number of tag accesses +system.iocache.tags.data_accesses 1040802 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses -system.iocache.demand_misses::total 8927 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8887 # number of overall misses -system.iocache.overall_misses::total 8927 # number of overall misses +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1443,8 +1154,332 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1764050 # number of replacements +system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use +system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66315846 # Number of tag accesses +system.l2c.tags.data_accesses 66315846 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits +system.l2c.Writeback_hits::total 2755239 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 196550 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 177871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 374421 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5920 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4325 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 492739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 919680 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 496903 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 884882 # number of demand (read+write) hits +system.l2c.demand_hits::total 2813943 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5920 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4325 # number of overall hits +system.l2c.overall_hits::cpu0.inst 492739 # number of overall hits +system.l2c.overall_hits::cpu0.data 919680 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5730 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3764 # number of overall hits +system.l2c.overall_hits::cpu1.inst 496903 # number of overall hits +system.l2c.overall_hits::cpu1.data 884882 # number of overall hits +system.l2c.overall_hits::total 2813943 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2339 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1938 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 57739 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 182657 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3510 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 3482 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 42081 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 192722 # number of ReadReq misses +system.l2c.ReadReq_misses::total 486468 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 475939 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 161383 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 637322 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 57732 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 55051 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 112783 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7557 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7409 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 14966 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 376574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 420815 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 797389 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2339 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1938 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 57739 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 559231 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3510 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3482 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 42081 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 613537 # number of demand (read+write) misses +system.l2c.demand_misses::total 1283857 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2339 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1938 # number of overall misses +system.l2c.overall_misses::cpu0.inst 57739 # number of overall misses +system.l2c.overall_misses::cpu0.data 559231 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3510 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3482 # number of overall misses +system.l2c.overall_misses::cpu1.inst 42081 # number of overall misses +system.l2c.overall_misses::cpu1.data 613537 # number of overall misses +system.l2c.overall_misses::total 1283857 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8259 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6263 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 550478 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 905787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9240 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7246 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 538984 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 899733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2925990 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2755239 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2755239 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 591401 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 264308 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 855709 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71710 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 65794 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 137504 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9051 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8691 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17742 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 573124 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 598686 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1171810 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8259 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6263 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 550478 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1478911 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7246 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 538984 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1498419 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4097800 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8259 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6263 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 550478 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1478911 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9240 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7246 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 538984 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1498419 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4097800 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309436 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.104889 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.201656 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.480541 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.078075 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.214199 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.166258 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.804765 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.610587 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.744788 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805076 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836718 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.820216 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.834935 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.852491 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.843535 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.657055 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.702898 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680476 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.309436 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.104889 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.378137 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.480541 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.078075 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.409456 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.313304 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.309436 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.104889 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.378137 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.480541 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.078075 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.409456 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.313304 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 1467678 # number of writebacks +system.l2c.writebacks::total 1467678 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 577534 # Transaction distribution +system.membus.trans_dist::ReadResp 577534 # Transaction distribution +system.membus.trans_dist::WriteReq 38903 # Transaction distribution +system.membus.trans_dist::WriteResp 38903 # Transaction distribution +system.membus.trans_dist::Writeback 1574372 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution +system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution +system.membus.trans_dist::ReadExReq 961374 # Transaction distribution +system.membus.trans_dist::ReadExResp 780321 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4407750 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 4407750 # Request fanout histogram +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117315 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 3343b5f3d..09df20817 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,59 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167186000 # Number of ticks simulated -final_tick 51111167186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111151 # Number of seconds simulated +sim_ticks 51111150553500 # Number of ticks simulated +final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1374172 # Simulator instruction rate (inst/s) -host_op_rate 1614949 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71508211345 # Simulator tick rate (ticks/s) -host_mem_usage 650720 # Number of bytes of host memory used -host_seconds 714.76 # Real time elapsed on the host -sim_insts 982202425 # Number of instructions simulated -sim_ops 1154300154 # Number of ops (including micro ops) simulated +host_inst_rate 1176583 # Simulator instruction rate (inst/s) +host_op_rate 1382679 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61065327647 # Simulator tick rate (ticks/s) +host_mem_usage 656288 # Number of bytes of host memory used +host_seconds 836.99 # Real time elapsed on the host +sim_insts 984789519 # Number of instructions simulated +sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 441600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 674240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 976256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5095732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90778056 # Number of bytes read from this memory -system.physmem.bytes_read::total 97965884 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5095732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5095732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65987904 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 101336100 # Number of bytes written to this memory -system.physmem.bytes_written::total 174150500 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 10535 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 15254 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 120028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1418420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1571137 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1031061 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 1585628 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2723353 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 13192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 19101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 99699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1776090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1916722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 99699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1291066 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 133562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1982661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3407289 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1291066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 142202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 19101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 99699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3758751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5324010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory +system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -70,141 +67,12 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 581631 # Transaction distribution -system.membus.trans_dist::ReadResp 581631 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1031061 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1689719 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1689719 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40041 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40042 # Transaction distribution -system.membus.trans_dist::ReadExReq 1025075 # Transaction distribution -system.membus.trans_dist::ReadExResp 1025075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7410875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7540385 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 231034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7771419 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 264848480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 265017848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7392896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7392896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 272410744 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4290796 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4290796 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4290796 # Request fanout histogram -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492262 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -229,25 +97,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183545113 # DTB read hits -system.cpu.dtb.read_misses 195347 # DTB read misses -system.cpu.dtb.write_hits 167775000 # DTB write hits -system.cpu.dtb.write_misses 71236 # DTB write misses +system.cpu.dtb.read_hits 184057973 # DTB read hits +system.cpu.dtb.read_misses 194269 # DTB read misses +system.cpu.dtb.write_hits 168276300 # DTB write hits +system.cpu.dtb.write_misses 71349 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9078 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183740460 # DTB read accesses -system.cpu.dtb.write_accesses 167846236 # DTB write accesses +system.cpu.dtb.read_accesses 184252242 # DTB read accesses +system.cpu.dtb.write_accesses 168347649 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351320113 # DTB hits -system.cpu.dtb.misses 266583 # DTB misses -system.cpu.dtb.accesses 351586696 # DTB accesses +system.cpu.dtb.hits 352334273 # DTB hits +system.cpu.dtb.misses 265618 # DTB misses +system.cpu.dtb.accesses 352599891 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -269,8 +137,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 982679430 # ITB inst hits -system.cpu.itb.inst_misses 126834 # ITB inst misses +system.cpu.itb.inst_hits 985266544 # ITB inst hits +system.cpu.itb.inst_misses 126829 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -279,119 +147,210 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982806264 # ITB inst accesses -system.cpu.itb.hits 982679430 # DTB hits -system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982806264 # DTB accesses -system.cpu.numCycles 102222351148 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 985393373 # ITB inst accesses +system.cpu.itb.hits 985266544 # DTB hits +system.cpu.itb.misses 126829 # DTB misses +system.cpu.itb.accesses 985393373 # DTB accesses +system.cpu.numCycles 102222317883 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 982202425 # Number of instructions committed -system.cpu.committedOps 1154300154 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057881248 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56834159 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151623535 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057881248 # number of integer instructions -system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560758600 # number of times the integer registers were read -system.cpu.num_int_register_writes 840516230 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read -system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264018450 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263440675 # number of times the CC registers were written -system.cpu.num_mem_refs 351539543 # number of memory refs -system.cpu.num_load_insts 183712417 # Number of load instructions -system.cpu.num_store_insts 167827126 # Number of store instructions -system.cpu.num_idle_cycles 101067404227.616409 # Number of idle cycles -system.cpu.num_busy_cycles 1154946920.383593 # Number of busy cycles -system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219533477 # Number of branches fetched +system.cpu.committedInsts 984789519 # Number of instructions committed +system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses +system.cpu.num_func_calls 57075493 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls +system.cpu.num_int_insts 1060698532 # number of integer instructions +system.cpu.num_fp_insts 880773 # number of float instructions +system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read +system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read +system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written +system.cpu.num_mem_refs 352552781 # number of memory refs +system.cpu.num_load_insts 184224242 # Number of load instructions +system.cpu.num_store_insts 168328539 # Number of store instructions +system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles +system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles +system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988672 # Percentage of idle cycles +system.cpu.Branches 220135160 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800832645 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183712417 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167827126 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction +system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction +system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154934980 # Class of executed instruction +system.cpu.op_class::total 1157924802 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 14265263 # number of replacements +system.cpu.dcache.tags.replacements 11615783 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.343227 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999718 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1421519854 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1421519854 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171606610 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171606610 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159566138 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159566138 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424146 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424146 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337798 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310377 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4310377 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4563246 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 331172748 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 331172748 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 331596894 # number of overall hits +system.cpu.dcache.overall_hits::total 331596894 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6013361 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6013361 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2569466 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2569466 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1584813 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1584813 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245259 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 254671 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 254671 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8582827 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8582827 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10167640 # number of overall misses +system.cpu.dcache.overall_misses::total 10167640 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177619971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 162135604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008959 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2008959 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583057 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4565048 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4563247 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 339755575 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 341764534 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 341764534 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788873 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788873 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786617 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029750 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 8923646 # number of writebacks +system.cpu.dcache.writebacks::total 8923646 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 14287218 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968528346 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265775 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891744 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 971093500 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997059906 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997059906 # 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miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,124 +360,130 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1249729 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64613.042707 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29358469 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1311519 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.385089 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13800320247500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36056.727460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 328.031175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 484.456162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6427.999826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21315.828084 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.550182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005005 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007392 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.325254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.985917 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 450 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 439 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4810 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53977 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.006866 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.935974 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 283403664 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 283403664 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 505204 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 246769 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14188853 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7449612 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22390438 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7859784 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7859784 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11730 # 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Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37844.065183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 274.121350 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 368.710071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6273.950851 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20500.608627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.577455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004183 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095733 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.312814 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62491 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953537 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 290358067 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 290358067 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 511193 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 258912 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14203603 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7508372 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22482080 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8923646 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8923646 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 697316 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 697316 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 11232 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 11232 # 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number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5836 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 84132 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 344473 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 440865 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 547943 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 547943 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 40028 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 40028 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1025635 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1025635 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14265780 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7842945 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22886487 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7859784 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7859784 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51208 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51208 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 833603 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 833603 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6424 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5836 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84132 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1178076 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1274468 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6424 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5836 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84132 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1178076 # number of overall misses +system.cpu.l2cache.overall_misses::total 1274468 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 517617 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 264748 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 14287735 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7852845 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516994 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515739 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 262023 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265780 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359939 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25403481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515739 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 262023 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265780 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359939 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25403481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.020427 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.058216 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050151 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021674 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.770934 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.770934 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2518206 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 517617 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 264748 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14287735 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10371051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25441151 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 517617 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 264748 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14287735 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10371051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25441151 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022044 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043866 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019232 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.440023 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.440023 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780882 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780882 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.407484 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.407484 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.020427 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.058216 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005392 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.136967 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059901 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.020427 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.058216 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005392 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.136967 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059901 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331031 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012411 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022044 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005888 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.113593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.050095 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012411 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022044 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005888 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.113593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.050095 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -527,181 +492,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1031061 # number of writebacks -system.cpu.l2cache.writebacks::total 1031061 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1507081 # number of writebacks +system.cpu.l2cache.writebacks::total 1507081 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 11606184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339855980 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281027 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417457465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417457465 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171111123 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171111123 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159073587 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159073587 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424480 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424480 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1583055 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 1583055 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303648 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303648 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555648 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555648 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330184710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330184710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330609190 # number of overall hits -system.cpu.dcache.overall_hits::total 330609190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002953 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002953 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2568202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2568202 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586188 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586188 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253804 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253804 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8571155 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8571155 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10157343 # number of overall misses -system.cpu.dcache.overall_misses::total 10157343 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177114076 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177114076 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641789 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641789 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583055 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583055 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557452 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557452 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555649 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555649 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 338755865 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 338755865 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 340766533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 340766533 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788886 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788886 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025302 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025302 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029807 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029807 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1583055 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7859784 # number of writebacks -system.cpu.dcache.writebacks::total 7859784 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23338761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23368238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23368238 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7859784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1583055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1583055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51260 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516994 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28617810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31982828 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548400 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 62907246 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 913182420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267567780 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2189976632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116124 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 35388588 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003264 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057040 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28661720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32393426 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 63356998 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 116335 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 35273071 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115517 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35388588 # Request fanout histogram -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use +system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40296 # Transaction distribution +system.iobus.trans_dist::ReadResp 40296 # Transaction distribution +system.iobus.trans_dist::WriteReq 136621 # Transaction distribution +system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115460 # number of replacements +system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -714,8 +641,92 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 526448 # Transaction distribution +system.membus.trans_dist::ReadResp 526448 # Transaction distribution +system.membus.trans_dist::WriteReq 33712 # Transaction distribution +system.membus.trans_dist::WriteResp 33712 # Transaction distribution +system.membus.trans_dist::Writeback 1613712 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution +system.membus.trans_dist::ReadExReq 833043 # Transaction distribution +system.membus.trans_dist::ReadExResp 833043 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3591670 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3591670 # Request fanout histogram +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 36c2b5576..2d0abc648 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,175 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.566016 # Number of seconds simulated -sim_ticks 47566015848000 # Number of ticks simulated -final_tick 47566015848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.398431 # Number of seconds simulated +sim_ticks 47398431268500 # Number of ticks simulated +final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 675626 # Simulator instruction rate (inst/s) -host_op_rate 794684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35963293075 # Simulator tick rate (ticks/s) -host_mem_usage 873656 # Number of bytes of host memory used -host_seconds 1322.63 # Real time elapsed on the host -sim_insts 893600449 # Number of instructions simulated -sim_ops 1051070162 # Number of ops (including micro ops) simulated +host_inst_rate 671569 # Simulator instruction rate (inst/s) +host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37657329129 # Simulator tick rate (ticks/s) +host_mem_usage 861000 # Number of bytes of host memory used +host_seconds 1258.68 # Real time elapsed on the host +sim_insts 845288376 # Number of instructions simulated +sim_ops 994755388 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 233408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 408704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 743028 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13616152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 28206528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 271488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 437568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 534776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13513568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 26761152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 461312 # Number of bytes read from this memory -system.physmem.bytes_read::total 85187684 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 743028 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 534776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1277804 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 43935424 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 56825292 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 43859652 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6846976 # Number of bytes written to this memory -system.physmem.bytes_written::total 151467344 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 212774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 440727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4242 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 6837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 211164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 418143 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7208 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1371589 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 686491 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 890172 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 685308 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106984 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2368955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 8592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 15621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 286258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 592997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 5708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 284101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 562611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1790936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 15621 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11243 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 26864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 923673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1194662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 922080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 143947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3184361 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 923673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 8592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 15621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1480920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 592997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 5708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1206181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 562611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 153645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4975296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1371589 # Number of read requests accepted -system.physmem.writeReqs 2368955 # Number of write requests accepted -system.physmem.readBursts 1371589 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2368955 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 87480576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 301120 # Total number of bytes read from write queue -system.physmem.bytesWritten 145871552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85187684 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 151467344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4705 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 89687 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 96177 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 85059 # Per bank write bursts -system.physmem.perBankRdBursts::1 83413 # Per bank write bursts -system.physmem.perBankRdBursts::2 77756 # Per bank write bursts -system.physmem.perBankRdBursts::3 83623 # Per bank write bursts -system.physmem.perBankRdBursts::4 79267 # Per bank write bursts -system.physmem.perBankRdBursts::5 92440 # Per bank write bursts -system.physmem.perBankRdBursts::6 79265 # Per bank write bursts -system.physmem.perBankRdBursts::7 88179 # Per bank write bursts -system.physmem.perBankRdBursts::8 75468 # Per bank write bursts -system.physmem.perBankRdBursts::9 124700 # Per bank write bursts -system.physmem.perBankRdBursts::10 77875 # Per bank write bursts -system.physmem.perBankRdBursts::11 89966 # Per bank write bursts -system.physmem.perBankRdBursts::12 78954 # Per bank write bursts -system.physmem.perBankRdBursts::13 87199 # Per bank write bursts -system.physmem.perBankRdBursts::14 85039 # Per bank write bursts -system.physmem.perBankRdBursts::15 78681 # Per bank write bursts -system.physmem.perBankWrBursts::0 146127 # Per bank write bursts -system.physmem.perBankWrBursts::1 131230 # Per bank write bursts -system.physmem.perBankWrBursts::2 144620 # Per bank write bursts -system.physmem.perBankWrBursts::3 127213 # Per bank write bursts -system.physmem.perBankWrBursts::4 148937 # Per bank write bursts -system.physmem.perBankWrBursts::5 150009 # Per bank write bursts -system.physmem.perBankWrBursts::6 182023 # Per bank write bursts -system.physmem.perBankWrBursts::7 144700 # Per bank write bursts -system.physmem.perBankWrBursts::8 124458 # Per bank write bursts -system.physmem.perBankWrBursts::9 140305 # Per bank write bursts -system.physmem.perBankWrBursts::10 119798 # Per bank write bursts -system.physmem.perBankWrBursts::11 155853 # Per bank write bursts -system.physmem.perBankWrBursts::12 153554 # Per bank write bursts -system.physmem.perBankWrBursts::13 129042 # Per bank write bursts -system.physmem.perBankWrBursts::14 144270 # Per bank write bursts -system.physmem.perBankWrBursts::15 137104 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory +system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1359566 # Number of read requests accepted +system.physmem.writeReqs 1139623 # Number of write requests accepted +system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue +system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 81504 # Per bank write bursts +system.physmem.perBankRdBursts::1 94599 # Per bank write bursts +system.physmem.perBankRdBursts::2 79086 # Per bank write bursts +system.physmem.perBankRdBursts::3 89082 # Per bank write bursts +system.physmem.perBankRdBursts::4 90127 # Per bank write bursts +system.physmem.perBankRdBursts::5 94039 # Per bank write bursts +system.physmem.perBankRdBursts::6 78740 # Per bank write bursts +system.physmem.perBankRdBursts::7 79772 # Per bank write bursts +system.physmem.perBankRdBursts::8 80197 # Per bank write bursts +system.physmem.perBankRdBursts::9 124149 # Per bank write bursts +system.physmem.perBankRdBursts::10 71869 # Per bank write bursts +system.physmem.perBankRdBursts::11 83577 # Per bank write bursts +system.physmem.perBankRdBursts::12 73174 # Per bank write bursts +system.physmem.perBankRdBursts::13 83519 # Per bank write bursts +system.physmem.perBankRdBursts::14 78794 # Per bank write bursts +system.physmem.perBankRdBursts::15 76558 # Per bank write bursts +system.physmem.perBankWrBursts::0 70549 # Per bank write bursts +system.physmem.perBankWrBursts::1 76959 # Per bank write bursts +system.physmem.perBankWrBursts::2 69527 # Per bank write bursts +system.physmem.perBankWrBursts::3 76268 # Per bank write bursts +system.physmem.perBankWrBursts::4 71760 # Per bank write bursts +system.physmem.perBankWrBursts::5 76111 # Per bank write bursts +system.physmem.perBankWrBursts::6 67646 # Per bank write bursts +system.physmem.perBankWrBursts::7 68141 # Per bank write bursts +system.physmem.perBankWrBursts::8 69345 # Per bank write bursts +system.physmem.perBankWrBursts::9 72887 # Per bank write bursts +system.physmem.perBankWrBursts::10 65485 # Per bank write bursts +system.physmem.perBankWrBursts::11 73987 # Per bank write bursts +system.physmem.perBankWrBursts::12 65828 # Per bank write bursts +system.physmem.perBankWrBursts::13 73935 # Per bank write bursts +system.physmem.perBankWrBursts::14 66021 # Per bank write bursts +system.physmem.perBankWrBursts::15 67418 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 47566012867000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 47398428076000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1328352 # Read request sizes (log2) +system.physmem.readPktSize::6 1316329 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2366352 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 854051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 158360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1137020 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -191,157 +188,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 89303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 97776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 118763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 123056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 124315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 149365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 128880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 131405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 133820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 133411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 132599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 131583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 133798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 128352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 124285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 123534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 832768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.211728 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.211424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.275385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 413524 49.66% 49.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 160093 19.22% 68.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 57236 6.87% 75.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29306 3.52% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24972 3.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16042 1.93% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12534 1.51% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12228 1.47% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 106833 12.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 832768 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 117976 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.586017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 192.972695 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 117973 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 117976 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 117976 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.319548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.993188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.933657 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 75459 63.96% 63.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36712 31.12% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3025 2.56% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 865 0.73% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 773 0.66% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 198 0.17% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 143 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 73 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 88 0.07% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 383 0.32% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 46 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 9 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 117976 # Writes before turning the bus around for reads -system.physmem.totQLat 39242427762 # Total ticks spent queuing -system.physmem.totMemAccLat 64871502762 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6834420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28709.41 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads +system.physmem.totQLat 69966976258 # Total ticks spent queuing +system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47459.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing -system.physmem.readRowHits 1063781 # Number of row buffer hits during reads -system.physmem.writeRowHits 1749574 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes -system.physmem.avgGap 12716335.61 # Average gap between requests -system.physmem.pageHitRate 77.16 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45509072189751 # Time in different power states -system.physmem.memoryStateTime::REF 1588333760000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 1114788 # Number of row buffer hits during reads +system.physmem.writeRowHits 726958 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes +system.physmem.avgGap 18965523.65 # Average gap between requests +system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states +system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 468608703999 # Time in different power states +system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3171472920 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3124253160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1730466375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1704701625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5218192200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5443409400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 7613086320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7156408320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3106780834560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3106780834560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1266482203425 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1265693181210 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27428659482750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27429351607500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31819655738550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31819254395775 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.957784 # Core power per rank (mW) -system.physmem.averagePower::1 668.949346 # Core power per rank (mW) +system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.625157 # Core power per rank (mW) +system.physmem.averagePower::1 668.587872 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -371,9 +369,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -398,25 +396,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86716512 # DTB read hits -system.cpu0.dtb.read_misses 82712 # DTB read misses -system.cpu0.dtb.write_hits 78633728 # DTB write hits -system.cpu0.dtb.write_misses 28389 # DTB write misses +system.cpu0.dtb.read_hits 74706058 # DTB read hits +system.cpu0.dtb.read_misses 64792 # DTB read misses +system.cpu0.dtb.write_hits 67192400 # DTB write hits +system.cpu0.dtb.write_misses 21129 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34135 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4682 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9159 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86799224 # DTB read accesses -system.cpu0.dtb.write_accesses 78662117 # DTB write accesses +system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 74770850 # DTB read accesses +system.cpu0.dtb.write_accesses 67213529 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165350240 # DTB hits -system.cpu0.dtb.misses 111101 # DTB misses -system.cpu0.dtb.accesses 165461341 # DTB accesses +system.cpu0.dtb.hits 141898458 # DTB hits +system.cpu0.dtb.misses 85921 # DTB misses +system.cpu0.dtb.accesses 141984379 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -438,283 +436,295 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 459685693 # ITB inst hits -system.cpu0.itb.inst_misses 60045 # ITB inst misses +system.cpu0.itb.inst_hits 397874920 # ITB inst hits +system.cpu0.itb.inst_misses 49120 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24187 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 459745738 # ITB inst accesses -system.cpu0.itb.hits 459685693 # DTB hits -system.cpu0.itb.misses 60045 # DTB misses -system.cpu0.itb.accesses 459745738 # DTB accesses -system.cpu0.numCycles 95132031682 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses +system.cpu0.itb.hits 397874920 # DTB hits +system.cpu0.itb.misses 49120 # DTB misses +system.cpu0.itb.accesses 397924040 # DTB accesses +system.cpu0.numCycles 94796862537 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 459439593 # Number of instructions committed -system.cpu0.committedOps 539347874 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 495403687 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 451172 # Number of float alu accesses -system.cpu0.num_func_calls 27064307 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69711991 # number of instructions that are conditional controls -system.cpu0.num_int_insts 495403687 # number of integer instructions -system.cpu0.num_fp_insts 451172 # number of float instructions -system.cpu0.num_int_register_reads 715734727 # number of times the integer registers were read -system.cpu0.num_int_register_writes 392523746 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 749199 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 337216 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119686995 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119275623 # number of times the CC registers were written -system.cpu0.num_mem_refs 165340768 # number of memory refs -system.cpu0.num_load_insts 86711184 # Number of load instructions -system.cpu0.num_store_insts 78629584 # Number of store instructions -system.cpu0.num_idle_cycles 94014587829.536469 # Number of idle cycles -system.cpu0.num_busy_cycles 1117443852.463529 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011746 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988254 # Percentage of idle cycles -system.cpu0.Branches 102470244 # Number of branches fetched +system.cpu0.committedInsts 397643174 # Number of instructions committed +system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses +system.cpu0.num_func_calls 23930039 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 429030148 # number of integer instructions +system.cpu0.num_fp_insts 322477 # number of float instructions +system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read +system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written +system.cpu0.num_mem_refs 141893093 # number of memory refs +system.cpu0.num_load_insts 74704433 # Number of load instructions +system.cpu0.num_store_insts 67188660 # Number of store instructions +system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles +system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles +system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles +system.cpu0.Branches 88352328 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 373021399 69.12% 69.12% # Class of executed instruction -system.cpu0.op_class::IntMult 1165287 0.22% 69.34% # Class of executed instruction -system.cpu0.op_class::IntDiv 62749 0.01% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 46895 0.01% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu0.op_class::MemRead 86711184 16.07% 85.43% # Class of executed instruction -system.cpu0.op_class::MemWrite 78629584 14.57% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction +system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction +system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 539637098 # Class of executed instruction +system.cpu0.op_class::total 466910423 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5368 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5553236 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.463915 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159572063 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5553747 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.732325 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 4859280 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.463915 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991140 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.991140 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 336276505 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 336276505 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80841388 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80841388 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74354122 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74354122 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186421 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 186421 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 887570 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 887570 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1858688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1858688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1820106 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1820106 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155195510 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155195510 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155381931 # number of overall hits -system.cpu0.dcache.overall_hits::total 155381931 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3020518 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3020518 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1355895 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1355895 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 638649 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 638649 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156836 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 156836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194186 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194186 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4376413 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4376413 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5015062 # number of overall misses -system.cpu0.dcache.overall_misses::total 5015062 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44235181893 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 44235181893 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23644478419 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23644478419 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2243299062 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2243299062 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4135736633 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4135736633 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1563000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1563000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 67879660312 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 67879660312 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 67879660312 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 67879660312 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83861906 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83861906 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75710017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75710017 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825070 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 825070 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 887570 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 887570 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015524 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2015524 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014292 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2014292 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159571923 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159571923 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 160396993 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 160396993 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036018 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036018 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774054 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774054 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077814 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077814 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096404 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096404 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027426 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027426 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031267 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031267 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # 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number of overall hits +system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # 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number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 887570 # number of fast writes performed +system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3048439 # number of writebacks -system.cpu0.dcache.writebacks::total 3048439 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28957 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 28957 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21342 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21342 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43075 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 50299 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 50299 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 50299 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 50299 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2991561 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2991561 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1334553 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1334553 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 637409 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 637409 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113761 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113761 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194186 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194186 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4326114 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4326114 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4963523 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4963523 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36853741584 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36853741584 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 20599874090 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 20599874090 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14249969925 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14249969925 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 39555111210 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39555111210 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1322683967 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1322683967 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3736995367 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3736995367 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1491000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1491000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 57453615674 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 57453615674 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 71703585599 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 71703585599 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2269904707 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2269904707 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2228690449 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2228690449 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4498595156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4498595156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017627 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017627 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.772551 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.772551 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056442 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056442 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096404 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096404 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027111 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027111 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030945 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030945 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks +system.cpu0.dcache.writebacks::total 3276433 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21424 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 36174 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 42252 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 42252 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 42252 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 42252 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2601941 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2601941 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1164183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1164183 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 551435 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 551435 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 697992 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 697992 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108847 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108847 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3766124 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3766124 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4317559 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4317559 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30561578872 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30561578872 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 15647124797 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 15647124797 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11524265112 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11524265112 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10542114896 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 10542114896 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1234908207 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1234908207 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3440508666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3440508666 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2386757695 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2386757695 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -722,58 +732,59 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5136279 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921269 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 454548902 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5136791 # 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Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 924508177 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8707.427163 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits +system.cpu0.icache.overall_hits::total 393605012 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4269908 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010732 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010732 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010732 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010732 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010732 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8815.966432 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8815.966432 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8815.966432 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8815.966432 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -782,365 +793,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 37020068050 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4269908 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4269908 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4269908 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4269908 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4269908 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4269908 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31235618425 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31235618425 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31235618425 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31235618425 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31235618425 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31235618425 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011175 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011175 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011175 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011175 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7206.847242 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7206.847242 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7206.847242 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010732 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010732 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7315.290733 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 47709911 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 798067 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44351595 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8146 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 467 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2551636 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3941553 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3159231 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16263.767973 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10999510 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3175316 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.464068 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 20647851500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 3883.106993 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 48.905367 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.754013 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 900.341601 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2586.177603 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8789.482396 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.237006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002985 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003403 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.054952 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.157848 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.536467 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.992662 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8304 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7669 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 543 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2171 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5264 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 3291824 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.318465 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003049 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003575 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044390 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3430 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3305 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 150 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.506836 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.468079 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 240919913 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 240919913 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 231031 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 134927 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4959117 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2742170 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8067245 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3048439 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3048439 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 86825 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 86825 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33826 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33826 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 910939 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 910939 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 231031 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 134927 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4959117 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3653109 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8978184 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 231031 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 134927 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4959117 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3653109 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8978184 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12665 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11145 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 177674 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000560 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1202044 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 109590 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 109590 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160357 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 160357 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 232216 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 232216 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12665 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11145 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 177674 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1232776 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1434260 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12665 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11145 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 177674 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1232776 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1434260 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 536996706 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 703824955 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 4673573829 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32218538016 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 38132933506 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2159798630 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2159798630 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3254740509 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3254740509 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1454999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1454999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10558981803 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 10558981803 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 536996706 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 703824955 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4673573829 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 42777519819 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 48691915309 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 536996706 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 703824955 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4673573829 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 42777519819 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 48691915309 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 243696 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146072 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5136791 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3742730 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 9269289 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3048439 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3048439 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 196415 # 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mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.198807 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.198807 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134182 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.051970 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.076298 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.029376 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.250201 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.172158 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.172158 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135483 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.379230 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1150,58 +1180,58 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 12709886 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9530898 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15163 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3048439 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 3732092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 887570 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 380241 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 457079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1289201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1150842 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10359832 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15601688 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 325277 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 566209 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 26853006 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 328927124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 571100341 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1168576 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1949568 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 903145609 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8562261 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 23134597 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.358060 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.479430 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 14851033 64.19% 64.19% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8283564 35.81% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 23134597 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 11405856452 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183601993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7759954717 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8048372726 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 179758799 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 322845049 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1226,25 +1256,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 81769828 # DTB read hits -system.cpu1.dtb.read_misses 79673 # DTB read misses -system.cpu1.dtb.write_hits 74311746 # DTB write hits -system.cpu1.dtb.write_misses 27355 # DTB write misses +system.cpu1.dtb.read_hits 84980512 # DTB read hits +system.cpu1.dtb.read_misses 74547 # DTB read misses +system.cpu1.dtb.write_hits 77969612 # DTB write hits +system.cpu1.dtb.write_misses 26781 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 41105 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4547 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10770 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81849501 # DTB read accesses -system.cpu1.dtb.write_accesses 74339101 # DTB write accesses +system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 85055059 # DTB read accesses +system.cpu1.dtb.write_accesses 77996393 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 156081574 # DTB hits -system.cpu1.dtb.misses 107028 # DTB misses -system.cpu1.dtb.accesses 156188602 # DTB accesses +system.cpu1.dtb.hits 162950124 # DTB hits +system.cpu1.dtb.misses 101328 # DTB misses +system.cpu1.dtb.accesses 163051452 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1266,283 +1296,295 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 434473512 # ITB inst hits -system.cpu1.itb.inst_misses 57336 # ITB inst misses +system.cpu1.itb.inst_hits 447940407 # ITB inst hits +system.cpu1.itb.inst_misses 68561 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28749 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 434530848 # ITB inst accesses -system.cpu1.itb.hits 434473512 # DTB hits -system.cpu1.itb.misses 57336 # DTB misses -system.cpu1.itb.accesses 434530848 # DTB accesses -system.cpu1.numCycles 95132031696 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses +system.cpu1.itb.hits 447940407 # DTB hits +system.cpu1.itb.misses 68561 # DTB misses +system.cpu1.itb.accesses 448008968 # DTB accesses +system.cpu1.numCycles 94796862537 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 434160856 # Number of instructions committed -system.cpu1.committedOps 511722288 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 470175639 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 456535 # Number of float alu accesses -system.cpu1.num_func_calls 26230713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66122636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 470175639 # number of integer instructions -system.cpu1.num_fp_insts 456535 # number of float instructions -system.cpu1.num_int_register_reads 688104482 # number of times the integer registers were read -system.cpu1.num_int_register_writes 373632663 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 726332 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 408756 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113709240 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113476936 # number of times the CC registers were written -system.cpu1.num_mem_refs 156073929 # number of memory refs -system.cpu1.num_load_insts 81768358 # Number of load instructions -system.cpu1.num_store_insts 74305571 # Number of store instructions -system.cpu1.num_idle_cycles 94082707842.004028 # Number of idle cycles -system.cpu1.num_busy_cycles 1049323853.995978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988970 # Percentage of idle cycles -system.cpu1.Branches 96877428 # Number of branches fetched +system.cpu1.committedInsts 447645202 # Number of instructions committed +system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses +system.cpu1.num_func_calls 27450761 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls +system.cpu1.num_int_insts 486291398 # number of integer instructions +system.cpu1.num_fp_insts 624474 # number of float instructions +system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read +system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written +system.cpu1.num_mem_refs 162934099 # number of memory refs +system.cpu1.num_load_insts 84972579 # Number of load instructions +system.cpu1.num_store_insts 77961520 # Number of store instructions +system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles +system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles +system.cpu1.Branches 100081816 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 354755827 69.28% 69.28% # Class of executed instruction -system.cpu1.op_class::IntMult 1081291 0.21% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 57437 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 66526 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 81768358 15.97% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 74305571 14.51% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction +system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction +system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction +system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction +system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 512035053 # Class of executed instruction +system.cpu1.op_class::total 528415149 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13728 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5229569 # number of replacements -system.cpu1.dcache.tags.tagsinuse 446.555743 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 150635340 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5230081 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.801722 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 446.555743 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.872179 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.872179 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5194711 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 317363377 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 317363377 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76086699 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76086699 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70396756 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70396756 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188905 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188905 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 685307 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 685307 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1701097 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1701097 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1676869 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1676869 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 146483455 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 146483455 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 146672360 # number of overall hits -system.cpu1.dcache.overall_hits::total 146672360 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2949268 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2949268 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1324938 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1324938 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648778 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 648778 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170596 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170596 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193531 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193531 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4274206 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4274206 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4922984 # number of overall misses -system.cpu1.dcache.overall_misses::total 4922984 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43925732439 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43925732439 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22816644952 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 22816644952 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2487645065 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2487645065 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4103865813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4103865813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1896000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1896000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 66742377391 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 66742377391 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 66742377391 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 66742377391 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79035967 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79035967 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71721694 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71721694 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 837683 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 837683 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685307 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 685307 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1871693 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1871693 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1870400 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1870400 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 150757661 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 150757661 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 151595344 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 151595344 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037316 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037316 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018473 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018473 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.774491 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.774491 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091145 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091145 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103470 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103470 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028352 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028352 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032475 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.032475 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits +system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses +system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 685307 # number of fast writes performed +system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 2978181 # number of writebacks -system.cpu1.dcache.writebacks::total 2978181 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23865 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 23865 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 515 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 515 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45192 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45192 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 24380 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 24380 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 24380 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 24380 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2925403 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2925403 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1324423 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1324423 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648778 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 648778 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125404 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125404 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193531 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193531 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4249826 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4249826 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4898604 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4898604 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36900792539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36900792539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20082419307 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20082419307 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13833136236 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13833136236 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 30583171682 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30583171682 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1453819204 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1453819204 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3706136187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3706136187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1808000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1808000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 56983211846 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 56983211846 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 70816348082 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 70816348082 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4114514480 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4114514480 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3994198470 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3994198470 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8108712950 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8108712950 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037014 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037014 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018466 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.774491 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.774491 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067000 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067000 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103470 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103470 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028190 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028190 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032314 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032314 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks +system.cpu1.dcache.writebacks::total 3397427 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 15143 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 185528 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 185528 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4214807 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4214807 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4786705 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4786705 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34665979416 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34665979416 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 16693598628 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 16693598628 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11612454284 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1550,59 +1592,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4838786 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.335132 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 429634209 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4839298 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.780275 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.335132 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969405 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969405 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5786522 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # 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Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 873786327 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 873786327 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 429634209 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 429634209 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 429634209 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 429634209 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 429634209 # number of overall hits -system.cpu1.icache.overall_hits::total 429634209 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4839303 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4839303 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4839303 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4839303 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4839303 # 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miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1611,367 +1653,384 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # 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number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9075250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9075250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9075250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9075250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012919 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.012919 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.012919 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7148.511456 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 45129085 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 818764 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 41906843 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8141 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 55302288 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 976452 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 51578919 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9282 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 514 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2394823 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3842139 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 584 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2737051 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4557576 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3029134 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13674.379805 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10606046 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3045261 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.482804 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10454752865000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4179.016177 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.517433 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 70.326677 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 591.513668 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3188.927208 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5590.078642 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.255067 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003327 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004292 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036103 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.341191 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.834618 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8556 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7510 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 438 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3359 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4072 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 611 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2836 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3841 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 307 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.522217 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.458374 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 230495604 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 230495604 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 221576 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 129888 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4667071 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2714218 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7732753 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 2978176 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 2978176 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 79936 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 79936 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35720 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35720 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 908771 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 908771 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 221576 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 129888 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4667071 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3622989 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8641524 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 221576 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 129888 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4667071 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3622989 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8641524 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12665 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11221 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 172232 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 985367 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1181485 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 109801 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 109801 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157805 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 157805 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 226147 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 226147 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12665 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11221 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 172232 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1211514 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1407632 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12665 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11221 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 172232 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1211514 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1407632 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 578928201 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 733432437 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4494366580 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32191641510 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 37998368728 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2189702140 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2189702140 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3225705678 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3225705678 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1763999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1763999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10153420884 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10153420884 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 578928201 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 733432437 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4494366580 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 42345062394 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 48151789612 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 578928201 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 733432437 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4494366580 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 42345062394 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 48151789612 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 234241 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 141109 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4839303 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3699585 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 8914238 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 2978176 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 2978176 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 189737 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 189737 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 193525 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134918 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1134918 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 234241 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 141109 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4839303 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4834503 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10049156 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 234241 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 141109 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4839303 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4834503 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10049156 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.054068 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079520 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.035590 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.266345 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.132539 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.578701 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.578701 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.815424 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.815424 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 3265247 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13732.593717 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11929802 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 3281353 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.635635 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9719592338000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 3548.297662 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 58.425503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # 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mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.375030 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1981,65 +2040,65 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12427806 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9137324 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 2978176 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3478890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 685307 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 370922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353849 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 446809 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1290596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1141918 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9678826 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15042396 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 312565 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544877 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25578664 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 309715832 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 550341480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1128872 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1873928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 863060112 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8621982 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22555543 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.370325 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482892 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14202655 62.97% 62.97% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8352888 37.03% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22555543 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10801104660 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 179932994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7260511142 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7881710673 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 172097315 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 311084554 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40536 # Transaction distribution -system.iobus.trans_dist::ReadResp 40536 # Transaction distribution -system.iobus.trans_dist::WriteReq 137093 # Transaction distribution -system.iobus.trans_dist::WriteResp 137147 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48328 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40487 # Transaction distribution +system.iobus.trans_dist::ReadResp 40487 # Transaction distribution +system.iobus.trans_dist::WriteReq 137083 # Transaction distribution +system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2049,18 +2108,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123470 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231816 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231816 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355366 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48348 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2070,18 +2129,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7514187 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36745000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2101,7 +2160,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2109,678 +2168,707 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 984235192 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93310000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179557795 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115889 # number of replacements -system.iocache.tags.tagsinuse 11.315870 # Cycle average of tags in use +system.iocache.tags.replacements 115786 # number of replacements +system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115905 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9130394779000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.824342 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.491528 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239021 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.468221 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.707242 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043961 # Number of tag accesses -system.iocache.tags.data_accesses 1043961 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106984 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106984 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1042467 # Number of tag accesses +system.iocache.tags.data_accesses 1042467 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8924 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8961 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 54 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 54 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8924 # number of demand (read+write) misses -system.iocache.demand_misses::total 8964 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses +system.iocache.demand_misses::total 8910 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8924 # number of overall misses -system.iocache.overall_misses::total 8964 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1957100855 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1962807855 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8870 # number of overall misses +system.iocache.overall_misses::total 8910 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1957100855 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1963164855 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1957100855 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1963164855 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8924 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8961 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 107038 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 107038 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8924 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8964 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8924 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8964 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000504 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000504 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219038.930365 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219005.450134 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219307.581242 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219005.450134 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 53861 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.810747 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106984 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106886 # number of writebacks +system.iocache.writebacks::total 106886 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8924 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8961 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8924 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8964 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8924 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8964 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492924359 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1496707359 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6628374628 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6628374628 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1492924359 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1496908359 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1492924359 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1496908359 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166991.115462 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1086855 # number of replacements -system.l2c.tags.tagsinuse 64099.647179 # Cycle average of tags in use -system.l2c.tags.total_refs 6672114 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1148598 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.808920 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9469.927163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 51.211523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 68.031290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 696.373428 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3179.738420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 291.904824 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 401.470147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 563.131009 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10017.603756 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.144500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.010626 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273804 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006126 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008593 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.152857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.326786 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.978083 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31587 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 29847 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1585 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25743 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1360 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 19154 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.481979 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.455429 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 80637866 # Number of tag accesses -system.l2c.tags.data_accesses 80637866 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 142068 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 620262 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1618371 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6096 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4059 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 137369 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 611754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1545913 # number of ReadReq hits -system.l2c.ReadReq_hits::total 4696463 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1994497 # number of Writeback hits -system.l2c.Writeback_hits::total 1994497 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 23769 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 27954 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 51723 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7971 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7653 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15624 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52432 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49853 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 102285 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4321 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 142068 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 672694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1618371 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4059 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 137369 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 661607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1545913 # number of demand (read+write) hits -system.l2c.demand_hits::total 4798748 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6250 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4321 # number of overall hits -system.l2c.overall_hits::cpu0.inst 142068 # number of overall hits -system.l2c.overall_hits::cpu0.data 672694 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1618371 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6096 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4059 # number of overall hits -system.l2c.overall_hits::cpu1.inst 137369 # number of overall hits -system.l2c.overall_hits::cpu1.data 661607 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1545913 # number of overall hits -system.l2c.overall_hits::total 4798748 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3647 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 6386 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8946 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 136148 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 441016 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4242 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 6837 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8364 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 140626 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 418325 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1174537 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 34627 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 36381 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 71008 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10699 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11055 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21754 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 78297 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 150579 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3647 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 6386 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8946 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 214445 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 441016 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4242 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 6837 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8364 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 212908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 418325 # number of demand (read+write) misses -system.l2c.demand_misses::total 1325116 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3647 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 6386 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8946 # number of overall misses -system.l2c.overall_misses::cpu0.data 214445 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 441016 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4242 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 6837 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8364 # number of overall misses -system.l2c.overall_misses::cpu1.data 212908 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 418325 # number of overall misses -system.l2c.overall_misses::total 1325116 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 290095498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 510585994 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 795450996 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11077065870 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 335992750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 542306996 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 742040494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 11432821383 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 116290930305 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 147041544 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 142085765 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 289127309 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51916806 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56203152 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 108119958 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5726616061 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5297244481 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11023860542 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 290095498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 510585994 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 795450996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 16803681931 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 335992750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 542306996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 742040494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 16730065864 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 127314790847 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 290095498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 510585994 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 795450996 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 16803681931 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 46140706698 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 335992750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 542306996 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 742040494 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 16730065864 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 44423863626 # number of overall miss cycles -system.l2c.overall_miss_latency::total 127314790847 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9897 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 151014 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 756410 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2059387 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 10338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 10896 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 145733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 752380 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 1964238 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 5871000 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1994497 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1994497 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 58396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 64335 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 122731 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 18670 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 18708 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 37378 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 130729 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 122135 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 252864 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9897 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 151014 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 887139 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2059387 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10338 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 10896 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 145733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 874515 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 1964238 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 6123864 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9897 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 151014 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 887139 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2059387 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10338 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 10896 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 145733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 874515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 1964238 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6123864 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.596432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.059240 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.179992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.214149 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.410331 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.627478 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.057393 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.186908 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.212971 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.200057 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.592969 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.565493 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.578566 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.573058 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590924 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.582000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.598926 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.591821 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.595494 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.368496 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.596432 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.059240 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 88718.375658 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78578.850320 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 96078.223225 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 2524 # number of cycles access was blocked +system.l2c.tags.replacements 1310456 # number of replacements +system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use +system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152562 # 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Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 74054042 # Number of tag accesses +system.l2c.tags.data_accesses 74054042 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 7096 # 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number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 812177995 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 7981910698 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 155563490387 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1840421 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2071411 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 3911832 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 134255920 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 141850516 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 276106436 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 49268414 # 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mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.598926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.591821 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.595494 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.216296 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.368496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.596432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059041 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.241699 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.214009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.410331 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.627478 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057297 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.243445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.212878 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.216296 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68819.320502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005699250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6158750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6627525497 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12885580747 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.137025 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.141222 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.199502 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.732133 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.473677 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.635819 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.493322 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.474793 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.483820 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.577482 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.527650 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.551922 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.455967 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.384956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417997 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.205710 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093539 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129567 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.066329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.174375 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.297121 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155238 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.058976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.205710 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2795,58 +2883,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1264717 # Transaction distribution -system.membus.trans_dist::ReadResp 1264717 # Transaction distribution -system.membus.trans_dist::WriteReq 38516 # Transaction distribution -system.membus.trans_dist::WriteResp 38516 # Transaction distribution -system.membus.trans_dist::Writeback 686491 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1679861 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1679861 # Transaction distribution -system.membus.trans_dist::UpgradeReq 316703 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302467 # Transaction distribution -system.membus.trans_dist::UpgradeResp 96183 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 163141 # Transaction distribution -system.membus.trans_dist::ReadExResp 147161 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123470 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1327465 # Transaction distribution +system.membus.trans_dist::ReadResp 1327465 # Transaction distribution +system.membus.trans_dist::WriteReq 37863 # Transaction distribution +system.membus.trans_dist::WriteResp 37863 # Transaction distribution +system.membus.trans_dist::Writeback 1017207 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution +system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution +system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 87184 # Transaction distribution +system.membus.trans_dist::ReadExResp 72708 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7297543 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 7446435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 230140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 230140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7676575 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229346740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 229554089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7308288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7308288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 236862377 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 540732 # Total snoops (count) -system.membus.snoop_fanout::samples 4331622 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581037 # Total snoops (count) +system.membus.snoop_fanout::samples 3119395 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4331622 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4331622 # Request fanout histogram -system.membus.reqLayer0.occupancy 101146499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3119395 # Request fanout histogram +system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22031996 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 23154905719 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 14237686781 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187996205 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2857,11 +2945,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2890,45 +2978,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 6727338 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 6719778 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38516 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38516 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1994497 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1572877 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 365008 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 318091 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 683099 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301724 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301724 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10020344 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9267363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 19287707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 322818441 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 297911776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 620730217 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1454894 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11304872 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010257 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.100757 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1532220 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11188916 98.97% 98.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115956 1.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11304872 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 19960086799 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6306000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16653624789 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15972471023 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index c88d045b6..e087cdc41 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,140 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.781056 # Number of seconds simulated -sim_ticks 51781056074000 # Number of ticks simulated -final_tick 51781056074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821204 # Number of seconds simulated +sim_ticks 51821203872000 # Number of ticks simulated +final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717486 # Simulator instruction rate (inst/s) -host_op_rate 843154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44175728553 # Simulator tick rate (ticks/s) -host_mem_usage 650840 # Number of bytes of host memory used -host_seconds 1172.16 # Real time elapsed on the host -sim_insts 841009423 # Number of instructions simulated -sim_ops 988312418 # Number of ops (including micro ops) simulated +host_inst_rate 797175 # Simulator instruction rate (inst/s) +host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46008450754 # Simulator tick rate (ticks/s) +host_mem_usage 656028 # Number of bytes of host memory used +host_seconds 1126.34 # Real time elapsed on the host +sim_insts 897890420 # Number of instructions simulated +sim_ops 1055061464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 385216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 437760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 790272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4324596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 53060296 # Number of bytes read from this memory -system.physmem.bytes_read::total 58998140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4324596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4324596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 30687936 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 99485540 # Number of bytes written to this memory -system.physmem.bytes_written::total 136999972 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 6840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 12348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 107979 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 829080 # Number of read requests responded to by this memory -system.physmem.num_reads::total 962266 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 479499 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 1556713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2142876 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 7439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 8454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 15262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 83517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1024705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1139377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 83517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 83517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 592648 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 131834 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1921273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2645755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 592648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 139273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 15262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 83517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2945978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3785132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 962266 # Number of read requests accepted -system.physmem.writeReqs 2142876 # Number of write requests accepted -system.physmem.readBursts 962266 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2142876 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61369728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 215296 # Total number of bytes read from write queue -system.physmem.bytesWritten 132432768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58998140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136999972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 3364 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 73592 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 33443 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65026 # Per bank write bursts -system.physmem.perBankRdBursts::1 59757 # Per bank write bursts -system.physmem.perBankRdBursts::2 57697 # Per bank write bursts -system.physmem.perBankRdBursts::3 55201 # Per bank write bursts -system.physmem.perBankRdBursts::4 59686 # Per bank write bursts -system.physmem.perBankRdBursts::5 66424 # Per bank write bursts -system.physmem.perBankRdBursts::6 54909 # Per bank write bursts -system.physmem.perBankRdBursts::7 46752 # Per bank write bursts -system.physmem.perBankRdBursts::8 56185 # Per bank write bursts -system.physmem.perBankRdBursts::9 105428 # Per bank write bursts -system.physmem.perBankRdBursts::10 56738 # Per bank write bursts -system.physmem.perBankRdBursts::11 56925 # Per bank write bursts -system.physmem.perBankRdBursts::12 52656 # Per bank write bursts -system.physmem.perBankRdBursts::13 52461 # Per bank write bursts -system.physmem.perBankRdBursts::14 54958 # Per bank write bursts -system.physmem.perBankRdBursts::15 58099 # Per bank write bursts -system.physmem.perBankWrBursts::0 127089 # Per bank write bursts -system.physmem.perBankWrBursts::1 113639 # Per bank write bursts -system.physmem.perBankWrBursts::2 227284 # Per bank write bursts -system.physmem.perBankWrBursts::3 120346 # Per bank write bursts -system.physmem.perBankWrBursts::4 128596 # Per bank write bursts -system.physmem.perBankWrBursts::5 124885 # Per bank write bursts -system.physmem.perBankWrBursts::6 105979 # Per bank write bursts -system.physmem.perBankWrBursts::7 88244 # Per bank write bursts -system.physmem.perBankWrBursts::8 113178 # Per bank write bursts -system.physmem.perBankWrBursts::9 146103 # Per bank write bursts -system.physmem.perBankWrBursts::10 105873 # Per bank write bursts -system.physmem.perBankWrBursts::11 119118 # Per bank write bursts -system.physmem.perBankWrBursts::12 106014 # Per bank write bursts -system.physmem.perBankWrBursts::13 144894 # Per bank write bursts -system.physmem.perBankWrBursts::14 168059 # Per bank write bursts -system.physmem.perBankWrBursts::15 129961 # Per bank write bursts +system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory +system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959683 # Number of read requests accepted +system.physmem.writeReqs 1860672 # Number of write requests accepted +system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue +system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56975 # Per bank write bursts +system.physmem.perBankRdBursts::1 58359 # Per bank write bursts +system.physmem.perBankRdBursts::2 58716 # Per bank write bursts +system.physmem.perBankRdBursts::3 57264 # Per bank write bursts +system.physmem.perBankRdBursts::4 61545 # Per bank write bursts +system.physmem.perBankRdBursts::5 66145 # Per bank write bursts +system.physmem.perBankRdBursts::6 57228 # Per bank write bursts +system.physmem.perBankRdBursts::7 52937 # Per bank write bursts +system.physmem.perBankRdBursts::8 52189 # Per bank write bursts +system.physmem.perBankRdBursts::9 99547 # Per bank write bursts +system.physmem.perBankRdBursts::10 57680 # Per bank write bursts +system.physmem.perBankRdBursts::11 61393 # Per bank write bursts +system.physmem.perBankRdBursts::12 54506 # Per bank write bursts +system.physmem.perBankRdBursts::13 60286 # Per bank write bursts +system.physmem.perBankRdBursts::14 51564 # Per bank write bursts +system.physmem.perBankRdBursts::15 52667 # Per bank write bursts +system.physmem.perBankWrBursts::0 114739 # Per bank write bursts +system.physmem.perBankWrBursts::1 115397 # Per bank write bursts +system.physmem.perBankWrBursts::2 117633 # Per bank write bursts +system.physmem.perBankWrBursts::3 119136 # Per bank write bursts +system.physmem.perBankWrBursts::4 120318 # Per bank write bursts +system.physmem.perBankWrBursts::5 121968 # Per bank write bursts +system.physmem.perBankWrBursts::6 116613 # Per bank write bursts +system.physmem.perBankWrBursts::7 113695 # Per bank write bursts +system.physmem.perBankWrBursts::8 109286 # Per bank write bursts +system.physmem.perBankWrBursts::9 116370 # Per bank write bursts +system.physmem.perBankWrBursts::10 115629 # Per bank write bursts +system.physmem.perBankWrBursts::11 118249 # Per bank write bursts +system.physmem.perBankWrBursts::12 111968 # Per bank write bursts +system.physmem.perBankWrBursts::13 117797 # Per bank write bursts +system.physmem.perBankWrBursts::14 110347 # Per bank write bursts +system.physmem.perBankWrBursts::15 113912 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 51781053518000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 51821201316000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 919150 # Read request sizes (log2) +system.physmem.readPktSize::6 916567 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2140303 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 916619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1858099 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -162,158 +159,157 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 84352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 107983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 131098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 115210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 123261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 119542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 117814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 132602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 122703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 125765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 114111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 113634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 111086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 107145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 106644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 107279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 104685 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 577071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.837219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.071808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 364.354794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 225600 39.09% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 129681 22.47% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48337 8.38% 69.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25344 4.39% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16032 2.78% 77.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12773 2.21% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9903 1.72% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10527 1.82% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 98874 17.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 577071 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 103651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.251131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 174.136795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 103646 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 103651 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 103651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.963744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.612401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.068688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 47209 45.55% 45.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51400 49.59% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1703 1.64% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1371 1.32% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 882 0.85% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 145 0.14% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 167 0.16% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 75 0.07% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 86 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.01% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.01% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.01% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 393 0.38% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 40 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 32 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 31 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 103651 # Writes before turning the bus around for reads -system.physmem.totQLat 10497513500 # Total ticks spent queuing -system.physmem.totMemAccLat 28476926000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4794510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10947.43 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads +system.physmem.totQLat 12714966775 # Total ticks spent queuing +system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29697.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 723659 # Number of row buffer hits during reads -system.physmem.writeRowHits 1727431 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 16675905.17 # Average gap between requests -system.physmem.pageHitRate 80.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49473510377000 # Time in different power states -system.physmem.memoryStateTime::REF 1729083200000 # Time in different power states +system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing +system.physmem.readRowHits 722338 # Number of row buffer hits during reads +system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes +system.physmem.avgGap 18373999.48 # Average gap between requests +system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states +system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 578461163500 # Time in different power states +system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2226745080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2135911680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1214989875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1165428000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3630494400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3848871000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6713681760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 6695136000 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3382086739200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3382086739200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1381227557085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1374892031880 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29857029495750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29862586974000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34634129703150 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34633411091760 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.857174 # Core power per rank (mW) -system.physmem.averagePower::1 668.843296 # Core power per rank (mW) +system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.686370 # Core power per rank (mW) +system.physmem.averagePower::1 668.663363 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -330,191 +326,12 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 445419 # Transaction distribution -system.membus.trans_dist::ReadResp 445419 # Transaction distribution -system.membus.trans_dist::WriteReq 33871 # Transaction distribution -system.membus.trans_dist::WriteResp 33871 # Transaction distribution -system.membus.trans_dist::Writeback 479499 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1660804 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1660804 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33447 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33449 # Transaction distribution -system.membus.trans_dist::ReadExReq 553497 # Transaction distribution -system.membus.trans_dist::ReadExResp 553497 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5572311 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5702495 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 228222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5930717 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 188786400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 188956724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7211712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 196168436 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2862 # Total snoops (count) -system.membus.snoop_fanout::samples 3095773 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3095773 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3095773 # Request fanout histogram -system.membus.reqLayer0.occupancy 106099500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5682499 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21134514240 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 11065598028 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599963 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 40401 # Transaction distribution -system.iobus.trans_dist::ReadResp 40401 # Transaction distribution -system.iobus.trans_dist::WriteReq 136730 # Transaction distribution -system.iobus.trans_dist::WriteResp 136733 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230998 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334424 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334424 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492830 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 981107027 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179038037 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -539,25 +356,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 158219223 # DTB read hits -system.cpu.dtb.read_misses 140465 # DTB read misses -system.cpu.dtb.write_hits 143634632 # DTB write hits -system.cpu.dtb.write_misses 49220 # DTB write misses +system.cpu.dtb.read_hits 168646043 # DTB read hits +system.cpu.dtb.read_misses 158497 # DTB read misses +system.cpu.dtb.write_hits 153371607 # DTB write hits +system.cpu.dtb.write_misses 56347 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71391 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7071 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18891 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 158359688 # DTB read accesses -system.cpu.dtb.write_accesses 143683852 # DTB write accesses +system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168804540 # DTB read accesses +system.cpu.dtb.write_accesses 153427954 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 301853855 # DTB hits -system.cpu.dtb.misses 189685 # DTB misses -system.cpu.dtb.accesses 302043540 # DTB accesses +system.cpu.dtb.hits 322017650 # DTB hits +system.cpu.dtb.misses 214844 # DTB misses +system.cpu.dtb.accesses 322232494 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -579,142 +396,348 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 841528845 # ITB inst hits -system.cpu.itb.inst_misses 119634 # ITB inst misses +system.cpu.itb.inst_hits 898442559 # ITB inst hits +system.cpu.itb.inst_misses 123457 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 51154 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 841648479 # ITB inst accesses -system.cpu.itb.hits 841528845 # DTB hits -system.cpu.itb.misses 119634 # DTB misses -system.cpu.itb.accesses 841648479 # DTB accesses -system.cpu.numCycles 103562112148 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898566016 # ITB inst accesses +system.cpu.itb.hits 898442559 # DTB hits +system.cpu.itb.misses 123457 # DTB misses +system.cpu.itb.accesses 898566016 # DTB accesses +system.cpu.numCycles 103642407744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 841009423 # Number of instructions committed -system.cpu.committedOps 988312418 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 908272324 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899019 # Number of float alu accesses -system.cpu.num_func_calls 50313277 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 127741607 # number of instructions that are conditional controls -system.cpu.num_int_insts 908272324 # number of integer instructions -system.cpu.num_fp_insts 899019 # number of float instructions -system.cpu.num_int_register_reads 1317064952 # number of times the integer registers were read -system.cpu.num_int_register_writes 720072212 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450897 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759632 # number of times the floating registers were written -system.cpu.num_cc_register_reads 218662872 # number of times the CC registers were read -system.cpu.num_cc_register_writes 218058310 # number of times the CC registers were written -system.cpu.num_mem_refs 301832909 # number of memory refs -system.cpu.num_load_insts 158209551 # Number of load instructions -system.cpu.num_store_insts 143623358 # Number of store instructions -system.cpu.num_idle_cycles 100527171614.894058 # Number of idle cycles -system.cpu.num_busy_cycles 3034940533.105942 # Number of busy cycles -system.cpu.not_idle_fraction 0.029306 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970694 # Percentage of idle cycles -system.cpu.Branches 187669847 # Number of branches fetched +system.cpu.committedInsts 897890420 # Number of instructions committed +system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses +system.cpu.num_func_calls 53165114 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls +system.cpu.num_int_insts 968615704 # number of integer instructions +system.cpu.num_fp_insts 900077 # number of float instructions +system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read +system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written +system.cpu.num_mem_refs 322001322 # number of memory refs +system.cpu.num_load_insts 168639088 # Number of load instructions +system.cpu.num_store_insts 153362234 # Number of store instructions +system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles +system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969412 # Percentage of idle cycles +system.cpu.Branches 200577010 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 684692132 69.24% 69.24% # Class of executed instruction -system.cpu.op_class::IntMult 2140683 0.22% 69.46% # Class of executed instruction -system.cpu.op_class::IntDiv 96951 0.01% 69.47% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 112246 0.01% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::MemRead 158209551 16.00% 85.48% # Class of executed instruction -system.cpu.op_class::MemWrite 143623358 14.52% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 988874964 # Class of executed instruction +system.cpu.op_class::total 1055656727 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16062 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 13492469 # number of replacements -system.cpu.icache.tags.tagsinuse 511.894753 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 828035859 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13492981 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 61.367896 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31319075250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.894753 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999794 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10282368 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits +system.cpu.dcache.overall_hits::total 303464910 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7580753 # 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average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7918344 # number of writebacks +system.cpu.dcache.writebacks::total 7918344 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7198 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7198 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21104 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21104 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72465482990 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59129774715 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59129774715 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19473134500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19473134500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25050592494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25050592494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2902318500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2902318500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 243499 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 243499 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 131595257705 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151068392205 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151068392205 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727938750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727938750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573388000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573388000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301326750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301326750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014996 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014996 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.785363 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.785363 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058856 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058856 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024312 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028368 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13578.225627 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13578.225627 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26688.386385 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 60874.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17424.178946 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17424.178946 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17048.946040 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17048.946040 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 13856298 # number of replacements +system.cpu.icache.tags.tagsinuse 511.892935 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 884585744 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13856810 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.837618 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31832974250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.892935 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 855021831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 855021831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 828035859 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 828035859 # 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185267091485 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185267091485 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185267091485 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185267091485 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185267091485 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185267091485 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 898442559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 898442559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 898442559 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 898442559 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 898442559 # 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average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 628827 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64292.510551 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 25964475 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 690318 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 37.612340 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13963583388500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36090.515742 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 282.968665 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 462.557574 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8120.436200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19336.032370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.550698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004318 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123908 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.295044 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.981026 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 448 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61043 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 436 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1832 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53784 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.931442 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 245315088 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1216524124 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1216524124 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148096939 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148096939 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 136359357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 136359357 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 375583 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 375583 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1554140 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 1554140 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3367107 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3367107 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3654437 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3654437 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 284456296 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 284456296 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 284831879 # number of overall hits -system.cpu.dcache.overall_hits::total 284831879 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4902764 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4902764 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2016394 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2016394 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1154103 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1154103 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 288962 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 288962 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6919158 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6919158 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8073261 # number of overall misses -system.cpu.dcache.overall_misses::total 8073261 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76779469503 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76779469503 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60928492192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60928492192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4073605250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4073605250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137707961695 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137707961695 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137707961695 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137707961695 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 152999703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 152999703 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 138375751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 138375751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1529686 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1529686 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1554140 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1554140 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3656069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3656069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3654439 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3654439 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291375454 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291375454 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292905140 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292905140 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014572 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014572 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754471 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.754471 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023747 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023747 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15660.445721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15660.445721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30216.560946 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30216.560946 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14097.373530 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14097.373530 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19902.416117 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19902.416117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17057.290938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17057.290938 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 1554140 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 6407423 # number of writebacks -system.cpu.dcache.writebacks::total 6407423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5098 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5098 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21192 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21192 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69202 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69202 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 26290 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 26290 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 26290 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 26290 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4897666 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4897666 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1995202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1995202 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1152860 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1152860 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 219760 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 219760 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 6892868 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 6892868 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8045728 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8045728 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66593476247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 66593476247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56238194808 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 56238194808 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 17420344250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 17420344250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 50499536991 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 50499536991 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2639848250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2639848250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 122831671055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 122831671055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 140252015305 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 140252015305 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5728170249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728170249 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573361000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573361000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301531249 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301531249 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753658 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753658 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060108 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060108 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027469 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027469 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13596.981960 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13596.981960 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.717339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.717339 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15110.546163 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15110.546163 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12012.414680 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12012.414680 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17820.110737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17820.110737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17431.861393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17431.861393 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 20761818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20753624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6407423 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1660819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1554140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 42524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 42526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1952681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1952681 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27072222 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 26182676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 874780 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 54730977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 863723604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1036044256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1950336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2556184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1904274380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 465684 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 30748357 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.061188 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 474114 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 30632803 99.62% 99.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115554 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 30748357 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23350352499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1018500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20304235714 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13344056707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 358207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 555725500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115481 # number of replacements -system.iocache.tags.tagsinuse 10.454792 # Cycle average of tags in use +system.iobus.trans_dist::ReadReq 40402 # Transaction distribution +system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::WriteReq 136733 # Transaction distribution +system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115480 # number of replacements +system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115497 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153677258000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.509713 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945079 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219357 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434067 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653424 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039872 # Number of tag accesses -system.iocache.tags.data_accesses 1039872 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039857 # Number of tag accesses +system.iocache.tags.data_accesses 1039857 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8835 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8835 # number of demand (read+write) misses -system.iocache.demand_misses::total 8875 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses +system.iocache.demand_misses::total 8876 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8835 # number of overall misses -system.iocache.overall_misses::total 8875 # number of overall misses +system.iocache.overall_misses::realview.ide 8836 # number of overall misses +system.iocache.overall_misses::total 8876 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1898661362 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1904146362 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1898661362 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1904485362 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1898661362 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1904485362 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8835 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106667 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106667 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8835 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8875 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8835 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8875 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000028 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000028 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -1344,53 +1271,61 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 214902.248104 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 214624.251803 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214589.899944 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214589.899944 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51753 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.426776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106629 # number of writebacks +system.iocache.writebacks::total 106629 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8835 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8872 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8835 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8875 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8835 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8875 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1439157862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1442718862 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6525754202 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6525754202 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1439157862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1442901862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1439157862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1442901862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses @@ -1398,18 +1333,112 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 162892.797057 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 162614.840171 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 462201 # Transaction distribution +system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::WriteReq 33872 # Transaction distribution +system.membus.trans_dist::WriteResp 33872 # Transaction distribution +system.membus.trans_dist::Writeback 1241967 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution +system.membus.trans_dist::ReadExReq 534513 # Transaction distribution +system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3244 # Total snoops (count) +system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2814199 # Request fanout histogram +system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index a57c553a7..72bc2e01a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,18 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167186000 # Number of ticks simulated -final_tick 51111167186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111151 # Number of seconds simulated +sim_ticks 51111150553500 # Number of ticks simulated +final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1245007 # Simulator instruction rate (inst/s) -host_op_rate 1463153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64786832406 # Simulator tick rate (ticks/s) -host_mem_usage 666372 # Number of bytes of host memory used -host_seconds 788.91 # Real time elapsed on the host -sim_insts 982202425 # Number of instructions simulated -sim_ops 1154300154 # Number of ops (including micro ops) simulated +host_inst_rate 1088550 # Simulator instruction rate (inst/s) +host_op_rate 1279225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56496360239 # Simulator tick rate (ticks/s) +host_mem_usage 672572 # Number of bytes of host memory used +host_seconds 904.68 # Real time elapsed on the host +sim_insts 984789519 # Number of instructions simulated +sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.dtb.walker 200576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 185152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3380276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37995016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 209984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 187968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2175808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 37325312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory +system.physmem.bytes_read::total 82097788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3380276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2175808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5556084 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 103298276 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 93224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 593685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3281 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 33997 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 583208 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1323198 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613714 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616287 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 66136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 743380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 730277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1606260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 66136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108706 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020649 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2021052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 66136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 743783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 730277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3627311 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -29,435 +85,13 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 441600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 336512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 497152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3037748 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 46051464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 337024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 478912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2057984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 44726784 # Number of bytes read from this memory -system.physmem.bytes_read::total 97965180 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3037748 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2057984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5095732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65987776 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 57990628 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 43345472 # Number of bytes written to this memory -system.physmem.bytes_written::total 174150372 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 6900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 5258 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 7768 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 87872 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 719567 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5266 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7483 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 32156 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 698856 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1571126 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1031059 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 908355 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 677273 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2723351 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 8640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 6584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 9727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 59434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 901006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 6594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 40265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 875088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1916708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 59434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 40265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1291064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 133562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1134598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 848063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3407286 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1291064 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 142202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 6584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 9727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 59434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2035604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 6594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 40265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1723151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5323994 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 581619 # Transaction distribution -system.membus.trans_dist::ReadResp 581619 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1031059 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1689719 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1689719 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40044 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40045 # Transaction distribution -system.membus.trans_dist::ReadExReq 1025076 # Transaction distribution -system.membus.trans_dist::ReadExResp 1025076 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7410857 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 7540367 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 231034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7771401 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 264847648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 265017016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7392896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7392896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 272409912 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4290786 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4290786 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4290786 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1249718 # number of replacements -system.l2c.tags.tagsinuse 64613.042702 # Cycle average of tags in use -system.l2c.tags.total_refs 29438941 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1311508 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 22.446635 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 13800320247500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36057.882399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 161.314219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 260.482704 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3661.102067 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9854.563004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 162.816685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 224.976066 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2766.895079 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11463.010480 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.550200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055864 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003433 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042219 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.174912 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.985917 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 446 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61344 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 435 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2192 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4810 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53981 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.006805 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.936035 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 284052655 # Number of tag accesses -system.l2c.tags.data_accesses 284052655 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 278747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 141162 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7094152 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3728500 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 275483 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 137718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7094701 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3721109 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22471572 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7859784 # number of Writeback hits -system.l2c.Writeback_hits::total 7859784 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 6010 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5720 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11730 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 752229 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 739129 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1491358 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 278747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 141162 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7094152 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4480729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 275483 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 137718 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7094701 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4460238 # number of demand (read+write) hits -system.l2c.demand_hits::total 23962930 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 278747 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 141162 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7094152 # number of overall hits -system.l2c.overall_hits::cpu0.data 4480729 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 275483 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 137718 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7094701 # number of overall hits -system.l2c.overall_hits::cpu1.data 4460238 # number of overall hits -system.l2c.overall_hits::total 23962930 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5258 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 7768 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 44771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 202781 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5266 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7483 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 32156 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 190554 # number of ReadReq misses -system.l2c.ReadReq_misses::total 496037 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 20061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19420 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 39481 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 517033 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 508603 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 1025636 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5258 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 7768 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 44771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 719814 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5266 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 7483 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 32156 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 699157 # number of demand (read+write) misses -system.l2c.demand_misses::total 1521673 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5258 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 7768 # number of overall misses -system.l2c.overall_misses::cpu0.inst 44771 # number of overall misses -system.l2c.overall_misses::cpu0.data 719814 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5266 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 7483 # number of overall misses -system.l2c.overall_misses::cpu1.inst 32156 # number of overall misses -system.l2c.overall_misses::cpu1.data 699157 # number of overall misses -system.l2c.overall_misses::total 1521673 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 284005 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 148930 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 7138923 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3931281 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 280749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 145201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 7126857 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3911663 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 22967609 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7859784 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7859784 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26071 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25140 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51211 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1269262 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1247732 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2516994 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 284005 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 148930 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7138923 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 5200543 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 280749 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 145201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7126857 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 5159395 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25484603 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 284005 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 148930 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7138923 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 5200543 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 280749 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 145201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7126857 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 5159395 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25484603 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.052159 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.006271 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.051581 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.051535 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004512 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.048714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.021597 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.769476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.772474 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.770948 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.407349 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.407622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.407484 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.052159 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006271 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.138411 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.051535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004512 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.135511 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.059710 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.018514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.052159 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006271 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.138411 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.018757 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.051535 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004512 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.135511 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.059710 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1031059 # number of writebacks -system.l2c.writebacks::total 1031059 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 18 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 23429115 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23429115 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7859784 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1583055 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1583055 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51211 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51212 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2516994 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2516994 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28617810 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31982832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830190 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 63087960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 913182420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1267567716 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2190699408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 116124 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 35478945 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003256 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056968 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 35363428 99.67% 99.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115517 0.33% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 35478945 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492262 # Cumulative packet size per connected master and slave (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -481,25 +115,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91814340 # DTB read hits -system.cpu0.dtb.read_misses 108240 # DTB read misses -system.cpu0.dtb.write_hits 84018556 # DTB write hits -system.cpu0.dtb.write_misses 37258 # DTB write misses -system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 91965302 # DTB read hits +system.cpu0.dtb.read_misses 107321 # DTB read misses +system.cpu0.dtb.write_hits 84365950 # DTB write hits +system.cpu0.dtb.write_misses 37661 # DTB write misses +system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25424 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56720 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56687 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4774 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4951 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10954 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91922580 # DTB read accesses -system.cpu0.dtb.write_accesses 84055814 # DTB write accesses +system.cpu0.dtb.perms_faults 11060 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92072623 # DTB read accesses +system.cpu0.dtb.write_accesses 84403611 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175832896 # DTB hits -system.cpu0.dtb.misses 145498 # DTB misses -system.cpu0.dtb.accesses 175978394 # DTB accesses +system.cpu0.dtb.hits 176331252 # DTB hits +system.cpu0.dtb.misses 144982 # DTB misses +system.cpu0.dtb.accesses 176476234 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -521,269 +155,275 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 492376635 # ITB inst hits -system.cpu0.itb.inst_misses 70812 # ITB inst misses +system.cpu0.itb.inst_hits 493804573 # ITB inst hits +system.cpu0.itb.inst_misses 70785 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25424 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40507 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40296 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 492447447 # ITB inst accesses -system.cpu0.itb.hits 492376635 # DTB hits -system.cpu0.itb.misses 70812 # DTB misses -system.cpu0.itb.accesses 492447447 # DTB accesses -system.cpu0.numCycles 98037034508 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493875358 # ITB inst accesses +system.cpu0.itb.hits 493804573 # DTB hits +system.cpu0.itb.misses 70785 # DTB misses +system.cpu0.itb.accesses 493875358 # DTB accesses +system.cpu0.numCycles 98036815347 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 492157902 # Number of instructions committed -system.cpu0.committedOps 578109926 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 529630902 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 450855 # Number of float alu accesses -system.cpu0.num_func_calls 28493711 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76041471 # number of instructions that are conditional controls -system.cpu0.num_int_insts 529630902 # number of integer instructions -system.cpu0.num_fp_insts 450855 # number of float instructions -system.cpu0.num_int_register_reads 782881083 # number of times the integer registers were read -system.cpu0.num_int_register_writes 420743584 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 732582 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 369632 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132702849 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132381135 # number of times the CC registers were written -system.cpu0.num_mem_refs 175956600 # number of memory refs -system.cpu0.num_load_insts 91908955 # Number of load instructions -system.cpu0.num_store_insts 84047645 # Number of store instructions -system.cpu0.num_idle_cycles 96929537952.996140 # Number of idle cycles -system.cpu0.num_busy_cycles 1107496555.003859 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles -system.cpu0.Branches 110099418 # Number of branches fetched +system.cpu0.committedInsts 493589418 # Number of instructions committed +system.cpu0.committedOps 579610206 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 531010156 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 454321 # Number of float alu accesses +system.cpu0.num_func_calls 28538505 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76169999 # number of instructions that are conditional controls +system.cpu0.num_int_insts 531010156 # number of integer instructions +system.cpu0.num_fp_insts 454321 # number of float instructions +system.cpu0.num_int_register_reads 784912346 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421695474 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 742936 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362460 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132983142 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132661017 # number of times the CC registers were written +system.cpu0.num_mem_refs 176454648 # number of memory refs +system.cpu0.num_load_insts 92059270 # Number of load instructions +system.cpu0.num_store_insts 84395378 # Number of store instructions +system.cpu0.num_idle_cycles 96925999292.039536 # Number of idle cycles +system.cpu0.num_busy_cycles 1110816054.960464 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011331 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988669 # Percentage of idle cycles +system.cpu0.Branches 110347037 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 401202102 69.36% 69.36% # Class of executed instruction -system.cpu0.op_class::IntMult 1174212 0.20% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 49936 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53534 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::MemRead 91908955 15.89% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 84047645 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 402205176 69.35% 69.35% # Class of executed instruction +system.cpu0.op_class::IntMult 1169973 0.20% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 50634 0.01% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52759 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 92059270 15.87% 85.45% # Class of executed instruction +system.cpu0.op_class::MemWrite 84395378 14.55% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 578436384 # Class of executed instruction +system.cpu0.op_class::total 579933190 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 14265263 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 968528346 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14265775 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.891744 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.596875 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.387725 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524603 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475367 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 997059906 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 997059906 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 485302312 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 483226034 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 968528346 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 485302312 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 483226034 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 968528346 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 485302312 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 483226034 # number of overall hits -system.cpu0.icache.overall_hits::total 968528346 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7138923 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7126857 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14265780 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7138923 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7126857 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14265780 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7138923 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7126857 # number of overall misses -system.cpu0.icache.overall_misses::total 14265780 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 492441235 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 490352891 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 982794126 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 492441235 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 490352891 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 982794126 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 492441235 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 490352891 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 982794126 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014534 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014534 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014534 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 11606183 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 339855525 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11606695 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.280990 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 11615783 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 340859093 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.343185 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 263.642084 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 248.357636 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.514926 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.485074 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 265.932740 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 246.066978 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.519400 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.480600 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1417455640 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1417455640 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85601256 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85509652 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171110908 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79544795 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79528789 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159073584 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209342 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 424330 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 905782 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 677273 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1583055 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2149143 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2154415 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4303558 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2275069 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280579 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4555648 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165146051 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165038441 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 330184492 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165355393 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165253429 # number of overall hits -system.cpu0.dcache.overall_hits::total 330608822 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3016346 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2986822 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6003168 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1295333 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1272872 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2568205 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788110 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797772 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 126825 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127069 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 253894 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1421517922 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1421517922 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85766676 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85839710 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171606386 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79896763 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79669373 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159566136 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208546 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215430 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 423976 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146337 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191461 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2132895 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2177393 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4310288 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2256573 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2306673 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165663439 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165509083 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 331172522 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165871985 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165724513 # number of overall hits +system.cpu0.dcache.overall_hits::total 331596498 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3019403 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2994182 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6013585 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1302154 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1267314 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2569468 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789306 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 795194 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1584500 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766302 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 478957 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 124586 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 130174 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 254760 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4311679 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4259694 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 8571373 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5099789 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5057466 # number of overall misses -system.cpu0.dcache.overall_misses::total 10157255 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88617602 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496474 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177114076 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 80840128 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80801661 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 161641789 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997452 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1012760 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2010212 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 905782 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 677273 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583055 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2275968 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2281484 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4557452 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275069 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280580 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4555649 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169457730 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 169298135 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 338755865 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170455182 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 170310895 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 340766077 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033751 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016023 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790123 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787721 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788913 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055696 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055710 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 4321557 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4261496 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 8583053 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5110863 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5056690 # number of overall misses +system.cpu0.dcache.overall_misses::total 10167553 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88786079 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88833892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81198917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80936687 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997852 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1010624 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 2008476 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 912639 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 670418 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2257481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2307567 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2256573 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2306674 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169984996 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169770579 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170982848 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170781203 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 341764051 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033705 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033856 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016037 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015658 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791005 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786835 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788907 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839655 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714415 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055188 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056412 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055807 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025444 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025161 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029919 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029695 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029807 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025423 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025101 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029891 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029609 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1583055 # number of fast writes performed +system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7859784 # number of writebacks -system.cpu0.dcache.writebacks::total 7859784 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8923646 # number of writebacks +system.cpu0.dcache.writebacks::total 8923646 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 14287218 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 971093500 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 267.813987 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 244.170612 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523074 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 999668970 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 999668970 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486710504 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 484382996 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 971093500 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486710504 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 484382996 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 971093500 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486710504 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 484382996 # number of overall hits +system.cpu0.icache.overall_hits::total 971093500 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7158773 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7128962 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14287735 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7158773 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7128962 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14287735 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7158773 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7128962 # number of overall misses +system.cpu0.icache.overall_misses::total 14287735 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493869277 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 491511958 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493869277 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 491511958 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493869277 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 491511958 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014495 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014504 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014495 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014504 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014495 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014504 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -807,25 +447,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91711295 # DTB read hits -system.cpu1.dtb.read_misses 106129 # DTB read misses -system.cpu1.dtb.write_hits 83753398 # DTB write hits -system.cpu1.dtb.write_misses 37024 # DTB write misses -system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 92072581 # DTB read hits +system.cpu1.dtb.read_misses 106555 # DTB read misses +system.cpu1.dtb.write_hits 83907281 # DTB write hits +system.cpu1.dtb.write_misses 36757 # DTB write misses +system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24347 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56316 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56101 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4760 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4637 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10697 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91817424 # DTB read accesses -system.cpu1.dtb.write_accesses 83790422 # DTB write accesses +system.cpu1.dtb.perms_faults 10591 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92179136 # DTB read accesses +system.cpu1.dtb.write_accesses 83944038 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175464693 # DTB hits -system.cpu1.dtb.misses 143153 # DTB misses -system.cpu1.dtb.accesses 175607846 # DTB accesses +system.cpu1.dtb.hits 175979862 # DTB hits +system.cpu1.dtb.misses 143312 # DTB misses +system.cpu1.dtb.accesses 176123174 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -847,136 +487,185 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 490289476 # ITB inst hits -system.cpu1.itb.inst_misses 69341 # ITB inst misses +system.cpu1.itb.inst_hits 491448225 # ITB inst hits +system.cpu1.itb.inst_misses 69790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24347 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40524 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40454 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 490358817 # ITB inst accesses -system.cpu1.itb.hits 490289476 # DTB hits -system.cpu1.itb.misses 69341 # DTB misses -system.cpu1.itb.accesses 490358817 # DTB accesses -system.cpu1.numCycles 97462079825 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 491518015 # ITB inst accesses +system.cpu1.itb.hits 491448225 # DTB hits +system.cpu1.itb.misses 69790 # DTB misses +system.cpu1.itb.accesses 491518015 # DTB accesses +system.cpu1.numCycles 97463256917 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 490044523 # Number of instructions committed -system.cpu1.committedOps 576190228 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 528250346 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 430494 # Number of float alu accesses -system.cpu1.num_func_calls 28340448 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75582064 # number of instructions that are conditional controls -system.cpu1.num_int_insts 528250346 # number of integer instructions -system.cpu1.num_fp_insts 430494 # number of float instructions -system.cpu1.num_int_register_reads 777877517 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419772646 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 687185 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 378928 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131315601 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131059540 # number of times the CC registers were written -system.cpu1.num_mem_refs 175582943 # number of memory refs -system.cpu1.num_load_insts 91803462 # Number of load instructions -system.cpu1.num_store_insts 83779481 # Number of store instructions -system.cpu1.num_idle_cycles 96357524268.359177 # Number of idle cycles -system.cpu1.num_busy_cycles 1104555556.640824 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011333 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988667 # Percentage of idle cycles -system.cpu1.Branches 109434059 # Number of branches fetched +system.cpu1.committedInsts 491200101 # Number of instructions committed +system.cpu1.committedOps 577679755 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 529688376 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 426452 # Number of float alu accesses +system.cpu1.num_func_calls 28536988 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75796446 # number of instructions that are conditional controls +system.cpu1.num_int_insts 529688376 # number of integer instructions +system.cpu1.num_fp_insts 426452 # number of float instructions +system.cpu1.num_int_register_reads 779402047 # number of times the integer registers were read +system.cpu1.num_int_register_writes 420937852 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 676063 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 385332 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131460069 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131204494 # number of times the CC registers were written +system.cpu1.num_mem_refs 176098133 # number of memory refs +system.cpu1.num_load_insts 92164972 # Number of load instructions +system.cpu1.num_store_insts 83933161 # Number of store instructions +system.cpu1.num_idle_cycles 96357264034.410416 # Number of idle cycles +system.cpu1.num_busy_cycles 1105992882.589586 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles +system.cpu1.Branches 109788123 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 399630543 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 1180172 0.20% 69.53% # Class of executed instruction -system.cpu1.op_class::IntDiv 50607 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 54288 0.01% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::MemRead 91803462 15.92% 85.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 83779481 14.53% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 400601727 69.31% 69.31% # Class of executed instruction +system.cpu1.op_class::IntMult 1185429 0.21% 69.51% # Class of executed instruction +system.cpu1.op_class::IntDiv 51217 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55063 0.01% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::MemRead 92164972 15.95% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 83933161 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 576498596 # Class of executed instruction +system.cpu1.op_class::total 577991612 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use +system.iobus.trans_dist::ReadReq 40296 # Transaction distribution +system.iobus.trans_dist::ReadResp 40296 # Transaction distribution +system.iobus.trans_dist::WriteReq 136621 # Transaction distribution +system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115460 # number of replacements +system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -989,8 +678,333 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1726938 # number of replacements +system.l2c.tags.tagsinuse 65261.456077 # Cycle average of tags in use +system.l2c.tags.total_refs 30061688 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1789677 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 16.797270 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37843.446470 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.851039 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 182.256334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3658.181664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9398.442867 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.187628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 187.456005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2615.769048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11103.865022 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.577445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.055819 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.143409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002109 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.039913 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.169432 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62493 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54021 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.953568 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 291022560 # Number of tag accesses +system.l2c.tags.data_accesses 291022560 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 283104 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 147368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7108650 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3755195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 278245 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 144464 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7094952 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3753176 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22565154 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8923646 # number of Writeback hits +system.l2c.Writeback_hits::total 8923646 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 347701 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 349614 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 697315 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 5665 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11232 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 860452 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 824150 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1684602 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 283104 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 147368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7108650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4615647 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 278245 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 144464 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7094952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4577326 # number of demand (read+write) hits +system.l2c.demand_hits::total 24249756 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 283104 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 147368 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7108650 # number of overall hits +system.l2c.overall_hits::cpu0.data 4615647 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 278245 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 144464 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7094952 # number of overall hits +system.l2c.overall_hits::cpu1.data 4577326 # number of overall hits +system.l2c.overall_hits::total 24249756 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3134 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2893 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 50123 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 178100 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3281 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2937 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 34010 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 166374 # number of ReadReq misses +system.l2c.ReadReq_misses::total 440852 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 418601 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 129343 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 547944 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 19998 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20032 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 40030 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 416039 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 417565 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 833604 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3134 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2893 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 50123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 594139 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2937 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34010 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 583939 # number of demand (read+write) misses +system.l2c.demand_misses::total 1274456 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3134 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2893 # number of overall misses +system.l2c.overall_misses::cpu0.inst 50123 # number of overall misses +system.l2c.overall_misses::cpu0.data 594139 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3281 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2937 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34010 # number of overall misses +system.l2c.overall_misses::cpu1.data 583939 # number of overall misses +system.l2c.overall_misses::total 1274456 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 286238 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 150261 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 7158773 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3933295 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 281526 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 147401 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 7128962 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3919550 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 23006006 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 766302 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 478957 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25663 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25599 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51262 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1276491 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1241715 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 286238 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 150261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7158773 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5209786 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 281526 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 147401 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7128962 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5161265 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25524212 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 286238 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 150261 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7158773 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5209786 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 281526 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 147401 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7128962 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5161265 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25524212 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.007002 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019925 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004771 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.042447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019162 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.546261 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.270051 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.440024 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779254 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782531 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780890 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.325924 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.336281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019253 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.007002 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114043 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019925 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004771 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.113139 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049931 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019253 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.007002 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114043 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019925 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004771 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.113139 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049931 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 1507083 # number of writebacks +system.l2c.writebacks::total 1507083 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 526435 # Transaction distribution +system.membus.trans_dist::ReadResp 526435 # Transaction distribution +system.membus.trans_dist::WriteReq 33712 # Transaction distribution +system.membus.trans_dist::WriteResp 33712 # Transaction distribution +system.membus.trans_dist::Writeback 1613714 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 654603 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 654603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40598 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40599 # Transaction distribution +system.membus.trans_dist::ReadExReq 833044 # Transaction distribution +system.membus.trans_dist::ReadExResp 833044 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5323323 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5452833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5790500 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213243872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 213413240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227630584 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3591663 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3591663 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3591663 # Request fanout histogram +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 23461417 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23461417 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51262 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51263 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28661720 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32393430 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832700 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 63543360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3330800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6622040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2239287552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 116335 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36238577 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003188 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056370 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 36123059 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36238577 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 2aea37e39..42cd6a730 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,87 +1,84 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112155 # Number of seconds simulated -sim_ticks 5112155173500 # Number of ticks simulated -final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112156 # Number of seconds simulated +sim_ticks 5112155738500 # Number of ticks simulated +final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1977176 # Simulator instruction rate (inst/s) -host_op_rate 4047982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50529549296 # Simulator tick rate (ticks/s) -host_mem_usage 594968 # Number of bytes of host memory used -host_seconds 101.17 # Real time elapsed on the host -sim_insts 200033988 # Number of instructions simulated -sim_ops 409540726 # Number of ops (including micro ops) simulated +host_inst_rate 1511003 # Simulator instruction rate (inst/s) +host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38615908446 # Simulator tick rate (ticks/s) +host_mem_usage 595640 # Number of bytes of host memory used +host_seconds 132.38 # Real time elapsed on the host +sim_insts 200033669 # Number of instructions simulated +sim_ops 409539941 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory -system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory +system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory +system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory -system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224314318 # number of cpu cycles simulated +system.cpu.numCycles 10224315447 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 200033988 # Number of instructions committed -system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses +system.cpu.committedInsts 200033669 # Number of instructions committed +system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2308777 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls -system.cpu.num_int_insts 374550150 # number of integer instructions +system.cpu.num_func_calls 2308749 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls +system.cpu.num_int_insts 374549395 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read -system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written +system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read +system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written -system.cpu.num_mem_refs 35680563 # number of memory refs -system.cpu.num_load_insts 27249389 # Number of load instructions -system.cpu.num_store_insts 8431174 # Number of store instructions -system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles -system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles +system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written +system.cpu.num_mem_refs 35680406 # number of memory refs +system.cpu.num_load_insts 27249300 # Number of load instructions +system.cpu.num_store_insts 8431106 # Number of store instructions +system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles +system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955601 # Percentage of idle cycles -system.cpu.Branches 43145769 # Number of branches fetched -system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction -system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction +system.cpu.Branches 43145649 # Number of branches fetched +system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction @@ -108,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409541761 # Class of executed instruction +system.cpu.op_class::total 409540976 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1623441 # number of replacements +system.cpu.dcache.tags.replacements 1623460 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -129,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits -system.cpu.dcache.overall_hits::total 20190999 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses -system.cpu.dcache.overall_misses::total 1626230 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits +system.cpu.dcache.overall_hits::total 20190819 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses +system.cpu.dcache.overall_misses::total 1626249 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks -system.cpu.dcache.writebacks::total 1536849 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks +system.cpu.dcache.writebacks::total 1536867 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits +system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,11 +230,11 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 791952 # number of replacements +system.cpu.icache.tags.replacements 791846 # number of replacements system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy @@ -248,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 134 system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits -system.cpu.icache.overall_hits::total 243645979 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses -system.cpu.icache.overall_misses::total 792471 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits +system.cpu.icache.overall_hits::total 243645674 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses +system.cpu.icache.overall_misses::total 792365 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses @@ -284,12 +281,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id @@ -339,17 +336,17 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 106197 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 106199 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -360,32 +357,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits -system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits +system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses @@ -393,58 +390,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses -system.cpu.l2cache.overall_misses::total 180453 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses +system.cpu.l2cache.overall_misses::total 180454 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,42 +450,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks -system.cpu.l2cache.writebacks::total 98349 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks +system.cpu.l2cache.writebacks::total 98351 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 48008 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution system.iobus.trans_dist::WriteReq 57692 # Transaction distribution @@ -545,12 +542,12 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -558,10 +555,10 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 428652 # Number of tag accesses system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses system.iocache.demand_misses::total 908 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses @@ -576,6 +573,8 @@ system.iocache.overall_accesses::pc.south_bridge.ide 908 system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses @@ -586,52 +585,54 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 13903768 # Transaction distribution system.membus.trans_dist::ReadResp 13903768 # Transaction distribution system.membus.trans_dist::WriteReq 13911 # Transaction distribution system.membus.trans_dist::WriteResp 13911 # Transaction distribution -system.membus.trans_dist::Writeback 98349 # Transaction distribution +system.membus.trans_dist::Writeback 145018 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution -system.membus.trans_dist::ReadExReq 134620 # Transaction distribution -system.membus.trans_dist::ReadExResp 134615 # Transaction distribution +system.membus.trans_dist::ReadExReq 134621 # Transaction distribution +system.membus.trans_dist::ReadExResp 134616 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution system.membus.trans_dist::MessageResp 1696 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 328677 # Request fanout histogram +system.membus.snoop_fanout::samples 375347 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 328677 # Request fanout histogram +system.membus.snoop_fanout::total 375347 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index f23e1bb1d..e0cd774db 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,123 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.194411 # Number of seconds simulated -sim_ticks 5194410635000 # Number of ticks simulated -final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196466 # Number of seconds simulated +sim_ticks 5196466347000 # Number of ticks simulated +final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1318005 # Simulator instruction rate (inst/s) -host_op_rate 2540682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53310327218 # Simulator tick rate (ticks/s) -host_mem_usage 594964 # Number of bytes of host memory used -host_seconds 97.44 # Real time elapsed on the host -sim_insts 128422722 # Number of instructions simulated -sim_ops 247557000 # Number of ops (including micro ops) simulated +host_inst_rate 596082 # Simulator instruction rate (inst/s) +host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24120553188 # Simulator tick rate (ticks/s) +host_mem_usage 596696 # Number of bytes of host memory used +host_seconds 215.44 # Real time elapsed on the host +sim_insts 128418244 # Number of instructions simulated +sim_ops 247550593 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory -system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory +system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory +system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory -system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155585 # Number of read requests accepted -system.physmem.writeReqs 127186 # Number of write requests accepted -system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue -system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10087 # Per bank write bursts -system.physmem.perBankRdBursts::1 9924 # Per bank write bursts -system.physmem.perBankRdBursts::2 10111 # Per bank write bursts -system.physmem.perBankRdBursts::3 9612 # Per bank write bursts -system.physmem.perBankRdBursts::4 10046 # Per bank write bursts -system.physmem.perBankRdBursts::5 9507 # Per bank write bursts -system.physmem.perBankRdBursts::6 9544 # Per bank write bursts -system.physmem.perBankRdBursts::7 9545 # Per bank write bursts -system.physmem.perBankRdBursts::8 9177 # Per bank write bursts -system.physmem.perBankRdBursts::9 9299 # Per bank write bursts -system.physmem.perBankRdBursts::10 9268 # Per bank write bursts -system.physmem.perBankRdBursts::11 9485 # Per bank write bursts -system.physmem.perBankRdBursts::12 9621 # Per bank write bursts -system.physmem.perBankRdBursts::13 9970 # Per bank write bursts -system.physmem.perBankRdBursts::14 10158 # Per bank write bursts -system.physmem.perBankRdBursts::15 10001 # Per bank write bursts -system.physmem.perBankWrBursts::0 8060 # Per bank write bursts -system.physmem.perBankWrBursts::1 7801 # Per bank write bursts -system.physmem.perBankWrBursts::2 7998 # Per bank write bursts -system.physmem.perBankWrBursts::3 7765 # Per bank write bursts -system.physmem.perBankWrBursts::4 8116 # Per bank write bursts -system.physmem.perBankWrBursts::5 7896 # Per bank write bursts -system.physmem.perBankWrBursts::6 7662 # Per bank write bursts -system.physmem.perBankWrBursts::7 7717 # Per bank write bursts -system.physmem.perBankWrBursts::8 7519 # Per bank write bursts -system.physmem.perBankWrBursts::9 7838 # Per bank write bursts -system.physmem.perBankWrBursts::10 7675 # Per bank write bursts -system.physmem.perBankWrBursts::11 7654 # Per bank write bursts -system.physmem.perBankWrBursts::12 8493 # Per bank write bursts -system.physmem.perBankWrBursts::13 8626 # Per bank write bursts -system.physmem.perBankWrBursts::14 8402 # Per bank write bursts -system.physmem.perBankWrBursts::15 7944 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154566 # Number of read requests accepted +system.physmem.writeReqs 173500 # Number of write requests accepted +system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9833 # Per bank write bursts +system.physmem.perBankRdBursts::1 9504 # Per bank write bursts +system.physmem.perBankRdBursts::2 9844 # Per bank write bursts +system.physmem.perBankRdBursts::3 9497 # Per bank write bursts +system.physmem.perBankRdBursts::4 9570 # Per bank write bursts +system.physmem.perBankRdBursts::5 9679 # Per bank write bursts +system.physmem.perBankRdBursts::6 9540 # Per bank write bursts +system.physmem.perBankRdBursts::7 9680 # Per bank write bursts +system.physmem.perBankRdBursts::8 9214 # Per bank write bursts +system.physmem.perBankRdBursts::9 9453 # Per bank write bursts +system.physmem.perBankRdBursts::10 9241 # Per bank write bursts +system.physmem.perBankRdBursts::11 9575 # Per bank write bursts +system.physmem.perBankRdBursts::12 9600 # Per bank write bursts +system.physmem.perBankRdBursts::13 10182 # Per bank write bursts +system.physmem.perBankRdBursts::14 10246 # Per bank write bursts +system.physmem.perBankRdBursts::15 9812 # Per bank write bursts +system.physmem.perBankWrBursts::0 10679 # Per bank write bursts +system.physmem.perBankWrBursts::1 10594 # Per bank write bursts +system.physmem.perBankWrBursts::2 10884 # Per bank write bursts +system.physmem.perBankWrBursts::3 10241 # Per bank write bursts +system.physmem.perBankWrBursts::4 10237 # Per bank write bursts +system.physmem.perBankWrBursts::5 10759 # Per bank write bursts +system.physmem.perBankWrBursts::6 10579 # Per bank write bursts +system.physmem.perBankWrBursts::7 10814 # Per bank write bursts +system.physmem.perBankWrBursts::8 10762 # Per bank write bursts +system.physmem.perBankWrBursts::9 11220 # Per bank write bursts +system.physmem.perBankWrBursts::10 10499 # Per bank write bursts +system.physmem.perBankWrBursts::11 10145 # Per bank write bursts +system.physmem.perBankWrBursts::12 11054 # Per bank write bursts +system.physmem.perBankWrBursts::13 11426 # Per bank write bursts +system.physmem.perBankWrBursts::14 10852 # Per bank write bursts +system.physmem.perBankWrBursts::15 10376 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5194410571500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5196466283500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155585 # Read request sizes (log2) +system.physmem.readPktSize::6 154566 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127186 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173500 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see @@ -159,183 +156,207 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads -system.physmem.totQLat 1472209750 # Total ticks spent queuing -system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads +system.physmem.totQLat 1460181000 # Total ticks spent queuing +system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing -system.physmem.readRowHits 127796 # Number of row buffer hits during reads -system.physmem.writeRowHits 98753 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing +system.physmem.readRowHits 127064 # Number of row buffer hits during reads +system.physmem.writeRowHits 139994 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes -system.physmem.avgGap 18369672.18 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states -system.physmem.memoryStateTime::REF 173452760000 # Time in different power states +system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes +system.physmem.avgGap 15839697.75 # Average gap between requests +system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states +system.physmem.memoryStateTime::REF 173521400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states +system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.751736 # Core power per rank (mW) -system.physmem.averagePower::1 668.747452 # Core power per rank (mW) +system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.773676 # Core power per rank (mW) +system.physmem.averagePower::1 668.783065 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10388821270 # number of cpu cycles simulated +system.cpu.numCycles 10392932694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128422722 # Number of instructions committed -system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses +system.cpu.committedInsts 128418244 # Number of instructions committed +system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2301199 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls -system.cpu.num_int_insts 232138334 # number of integer instructions +system.cpu.num_func_calls 2300917 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls +system.cpu.num_int_insts 232131886 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read -system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written +system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read +system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written -system.cpu.num_mem_refs 22258678 # number of memory refs -system.cpu.num_load_insts 13887993 # Number of load instructions -system.cpu.num_store_insts 8370685 # Number of store instructions -system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles -system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942533 # Percentage of idle cycles -system.cpu.Branches 26323220 # Number of branches fetched -system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction +system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written +system.cpu.num_mem_refs 22255642 # number of memory refs +system.cpu.num_load_insts 13887148 # Number of load instructions +system.cpu.num_store_insts 8368494 # Number of store instructions +system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles +system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942560 # Percentage of idle cycles +system.cpu.Branches 26322824 # Number of branches fetched +system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction +system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction @@ -362,150 +383,150 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247558577 # Class of executed instruction +system.cpu.op_class::total 247552167 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1622351 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1622836 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035174 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19973448 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20032670 # number of overall hits +system.cpu.dcache.overall_hits::total 20032670 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907502 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907502 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325247 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325247 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402429 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402429 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232749 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8358069 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8358069 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21206197 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21206197 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21667848 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21667848 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070633 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.662651 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks -system.cpu.dcache.writebacks::total 1538923 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9540 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337559000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21121080129 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21121080129 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26458639129 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26458639129 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -513,58 +534,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,86 +594,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 791372 # number of replacements -system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 791291 # number of replacements +system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.714106 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.349956 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits -system.cpu.icache.overall_hits::total 144679417 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses -system.cpu.icache.overall_misses::total 791891 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits +system.cpu.icache.overall_hits::total 144673577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses +system.cpu.icache.overall_misses::total 791810 # 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number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,88 +682,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791810 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791810 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791810 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791810 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791810 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791810 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9531495383 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9531495383 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9531495383 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9531495383 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9531495383 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9531495383 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12037.604202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12037.604202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 29095 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29095 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7743 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7743 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7745 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7745 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7745 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7745 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4535 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4535 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4535 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4535 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4535 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4535 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45208750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45208750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12280 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12280 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12280 # 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average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,177 +772,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 825 # 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number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049511 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169778 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987960 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64704 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2830 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57717 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987305 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32214708 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32214708 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6577 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3185 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778918 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1279822 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068502 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988129 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32220029 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32220029 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6582 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2969 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 778852 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1280153 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2068556 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1543232 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1543232 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200337 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063968 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,57 +1042,57 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 52938 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53212 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230267 # Transaction distribution -system.iobus.trans_dist::ReadResp 230267 # Transaction distribution -system.iobus.trans_dist::WriteReq 57693 # Transaction distribution -system.iobus.trans_dist::WriteResp 57694 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.trans_dist::ReadReq 230264 # Transaction distribution +system.iobus.trans_dist::ReadResp 230264 # Transaction distribution +system.iobus.trans_dist::WriteReq 57694 # Transaction distribution +system.iobus.trans_dist::WriteResp 10974 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.iobus.trans_dist::MessageReq 1655 # Transaction distribution system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) @@ -1093,11 +1114,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1117,11 +1138,11 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) @@ -1158,161 +1179,169 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 421906845 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47512 # number of replacements -system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use +system.iocache.tags.replacements 47510 # number of replacements +system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428111 # Number of tag accesses -system.iocache.tags.data_accesses 428111 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses -system.iocache.ReadReq_misses::total 847 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses -system.iocache.demand_misses::total 847 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses -system.iocache.overall_misses::total 847 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428076 # Number of tag accesses +system.iocache.tags.data_accesses 428076 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses +system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses +system.iocache.demand_misses::total 844 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses +system.iocache.overall_misses::total 844 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624009 # Transaction distribution -system.membus.trans_dist::ReadResp 624009 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 80466 # Transaction distribution +system.membus.trans_dist::ReadReq 624001 # Transaction distribution +system.membus.trans_dist::ReadResp 624001 # Transaction distribution +system.membus.trans_dist::WriteReq 13890 # Transaction distribution +system.membus.trans_dist::WriteResp 13890 # Transaction distribution +system.membus.trans_dist::Writeback 126780 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution -system.membus.trans_dist::ReadExReq 113541 # Transaction distribution -system.membus.trans_dist::ReadExResp 113541 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution +system.membus.trans_dist::ReadExReq 113178 # Transaction distribution +system.membus.trans_dist::ReadExResp 113178 # Transaction distribution system.membus.trans_dist::MessageReq 1655 # Transaction distribution system.membus.trans_dist::MessageResp 1655 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 943 # Total snoops (count) -system.membus.snoop_fanout::samples 285344 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1607 # Total snoops (count) +system.membus.snoop_fanout::samples 331268 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 285344 # Request fanout histogram +system.membus.snoop_fanout::total 331268 # Request fanout histogram system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index a15c23d57..c9524dba5 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35024500 # Number of ticks simulated -final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 35022500 # Number of ticks simulated +final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72507 # Simulator instruction rate (inst/s) -host_op_rate 72491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 396631772 # Simulator tick rate (ticks/s) -host_mem_usage 236200 # Number of bytes of host memory used +host_inst_rate 71946 # Simulator instruction rate (inst/s) +host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 393524726 # Simulator tick rate (ticks/s) +host_mem_usage 237176 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34926000 # Total gap between requests +system.physmem.totGap 34924000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3928000 # Total ticks spent queuing -system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3887500 # Total ticks spent queuing +system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.61 # Data bus utilization in percentage @@ -216,12 +216,12 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65527.20 # Average gap between requests +system.physmem.avgGap 65523.45 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 15500 # Time in different power states system.physmem.memoryStateTime::REF 1040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30394500 # Time in different power states +system.physmem.memoryStateTime::ACT 30393500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) @@ -234,66 +234,43 @@ system.physmem.writeEnergy::1 0 # En system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) system.physmem.averagePower::0 827.295718 # Core power per rank (mW) -system.physmem.averagePower::1 815.802457 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 460 # Transaction distribution -system.membus.trans_dist::ReadResp 460 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 533 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1959 # Number of BP lookups -system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted +system.physmem.averagePower::1 815.785757 # Core power per rank (mW) +system.cpu.branchPred.lookups 1972 # Number of BP lookups +system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups -system.cpu.branchPred.BTBHits 381 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups +system.cpu.branchPred.BTBHits 385 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1368 # DTB read hits +system.cpu.dtb.read_hits 1370 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1379 # DTB read accesses +system.cpu.dtb.read_accesses 1381 # DTB read accesses system.cpu.dtb.write_hits 884 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2252 # DTB hits +system.cpu.dtb.data_hits 2254 # DTB hits system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2266 # DTB accesses -system.cpu.itb.fetch_hits 2630 # ITB hits +system.cpu.dtb.data_accesses 2268 # DTB accesses +system.cpu.itb.fetch_hits 2642 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2647 # ITB accesses +system.cpu.itb.fetch_accesses 2659 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,68 +284,180 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70049 # number of cpu cycles simulated +system.cpu.numCycles 70045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.945156 # CPI: cycles per instruction -system.cpu.ipc 0.091365 # IPC: instructions per cycle -system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.944531 # CPI: cycles per instruction +system.cpu.ipc 0.091370 # IPC: instructions per cycle +system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits +system.cpu.dcache.overall_hits::total 1973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses +system.cpu.dcache.overall_misses::total 227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5625 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits -system.cpu.icache.overall_hits::total 2265 # number of overall hits +system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5649 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits +system.cpu.icache.overall_hits::total 2277 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id @@ -459,14 +520,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 # system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -483,14 +544,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,14 +568,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -523,126 +584,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits -system.cpu.dcache.overall_hits::total 1968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 460 # Transaction distribution +system.membus.trans_dist::ReadResp 460 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 533 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 533 # Request fanout histogram +system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index cff801d36..0513960dd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18662000 # Number of ticks simulated -final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18733500 # Number of ticks simulated +final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40123 # Simulator instruction rate (inst/s) -host_op_rate 40110 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 289474844 # Simulator tick rate (ticks/s) -host_mem_usage 234892 # Number of bytes of host memory used +host_inst_rate 41421 # Simulator instruction rate (inst/s) +host_op_rate 41407 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 299977624 # Simulator tick rate (ticks/s) +host_mem_usage 235900 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 14272 # Nu system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056264066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1056264066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 764762619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 764762619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056264066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1056264066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1052232631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18580000 # Total gap between requests +system.physmem.totGap 18651500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -182,118 +182,95 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 411.636364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 270.438338 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.932860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7 15.91% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 9.09% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 6.82% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 13.64% 70.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 11.36% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation -system.physmem.totQLat 1719250 # Total ticks spent queuing -system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation +system.physmem.totQLat 1958750 # Total ticks spent queuing +system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.25 # Data bus utilization in percentage -system.physmem.busUtilRead 8.25 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.22 # Data bus utilization in percentage +system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 256 # Number of row buffer hits during reads +system.physmem.readRowHits 257 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 60324.68 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem.avgGap 60556.82 # Average gap between requests +system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 15500 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15310750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 90720 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 49500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ) system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1302600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10733670 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ) system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 84000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ) system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12770610 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13448430 # Total energy per rank (pJ) -system.physmem.averagePower::0 806.607295 # Core power per rank (mW) -system.physmem.averagePower::1 849.419233 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 281 # Transaction distribution -system.membus.trans_dist::ReadResp 281 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 308 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 15.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 786 # Number of BP lookups -system.cpu.branchPred.condPredicted 393 # Number of conditional branches predicted +system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ) +system.physmem.averagePower::0 806.306964 # Core power per rank (mW) +system.physmem.averagePower::1 848.926575 # Core power per rank (mW) +system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 558 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.394265 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 508 # DTB read hits +system.cpu.dtb.read_hits 509 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 515 # DTB read accesses +system.cpu.dtb.read_accesses 516 # DTB read accesses system.cpu.dtb.write_hits 307 # DTB write hits system.cpu.dtb.write_misses 6 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 815 # DTB hits +system.cpu.dtb.data_hits 816 # DTB hits system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 828 # DTB accesses -system.cpu.itb.fetch_hits 962 # ITB hits +system.cpu.dtb.data_accesses 829 # DTB accesses +system.cpu.itb.fetch_hits 974 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 975 # ITB accesses +system.cpu.itb.fetch_accesses 987 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,68 +284,180 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 37324 # number of cpu cycles simulated +system.cpu.numCycles 37467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 635 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.438685 # CPI: cycles per instruction -system.cpu.ipc 0.069258 # IPC: instructions per cycle -system.cpu.tickCycles 5337 # Number of cycles that the object actually ticked -system.cpu.idleCycles 31987 # Total number of cycles that the object has spent stopped +system.cpu.cpi 14.494004 # CPI: cycles per instruction +system.cpu.ipc 0.068994 # IPC: instructions per cycle +system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked +system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 441 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 692 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 692 # number of overall hits +system.cpu.dcache.overall_hits::total 692 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 104 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses +system.cpu.dcache.overall_misses::total 104 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 16 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.813999 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 739 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.313901 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.813999 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058015 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2147 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2147 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 739 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 739 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 739 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 739 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 739 # number of overall hits -system.cpu.icache.overall_hits::total 739 # number of overall hits +system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2171 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits +system.cpu.icache.overall_hits::total 751 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15454750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15454750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15454750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15454750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15454750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15454750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 962 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231809 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.231809 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.231809 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.231809 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.231809 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.231809 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69303.811659 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69303.811659 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69303.811659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69303.811659 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14914250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14914250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14914250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14914250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231809 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231809 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231809 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231809 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66880.044843 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66880.044843 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 136250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.987026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.987026 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004486 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id @@ -453,14 +514,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 308 # system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18929750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18929750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 1803250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1803250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20733000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20733000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20733000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20733000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) @@ -477,14 +538,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67365.658363 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67365.658363 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66787.037037 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66787.037037 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.935065 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67314.935065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.935065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67314.935065 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,14 +562,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 308 system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15410750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15410750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1471750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1471750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16882500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16882500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16882500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16882500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -517,126 +578,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54842.526690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54842.526690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54509.259259 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54509.259259 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54813.311688 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54813.311688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54813.311688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54813.311688 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.699994 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 687 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.082353 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.699994 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011890 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011890 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1667 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1667 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 687 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 687 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 687 # number of overall hits -system.cpu.dcache.overall_hits::total 687 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 104 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses -system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4631500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4631500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3005500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3005500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 7637000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 7637000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 791 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 791 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 791 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 791 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.122736 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.122736 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.131479 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.131479 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.131479 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.131479 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75926.229508 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75926.229508 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69895.348837 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69895.348837 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73432.692308 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73432.692308 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 16 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4297000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4297000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1830750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1830750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6127750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6127750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6127750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6127750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.116700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.107459 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.107459 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74086.206897 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74086.206897 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67805.555556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67805.555556 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 281 # Transaction distribution +system.membus.trans_dist::ReadResp 281 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 308 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 308 # Request fanout histogram +system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 15.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index d08d4e917..1f9a90b5a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27911000 # Number of ticks simulated -final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27981000 # Number of ticks simulated +final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3437 # Simulator instruction rate (inst/s) -host_op_rate 4023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20833659 # Simulator tick rate (ticks/s) -host_mem_usage 251612 # Number of bytes of host memory used -host_seconds 1.34 # Real time elapsed on the host +host_inst_rate 65720 # Simulator instruction rate (inst/s) +host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399296424 # Simulator tick rate (ticks/s) +host_mem_usage 250660 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory -system.physmem.bytes_read::total 26880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 420 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 420 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory +system.physmem.bytes_read::total 26944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory +system.physmem.num_reads::total 421 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 91 # Per bank write bursts -system.physmem.perBankRdBursts::1 51 # Per bank write bursts +system.physmem.perBankRdBursts::1 52 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 42 # Per bank write bursts -system.physmem.perBankRdBursts::4 23 # Per bank write bursts +system.physmem.perBankRdBursts::3 43 # Per bank write bursts +system.physmem.perBankRdBursts::4 22 # Per bank write bursts system.physmem.perBankRdBursts::5 41 # Per bank write bursts system.physmem.perBankRdBursts::6 36 # Per bank write bursts system.physmem.perBankRdBursts::7 12 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27825500 # Total gap between requests +system.physmem.totGap 27895500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 420 # Read request sizes (log2) +system.physmem.readPktSize::6 421 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -87,7 +87,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,28 +182,28 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation -system.physmem.totQLat 2575500 # Total ticks spent queuing -system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2478000 # Total ticks spent queuing +system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.52 # Data bus utilization in percentage @@ -211,20 +211,20 @@ system.physmem.busUtilRead 7.52 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.readRowHits 350 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66251.19 # Average gap between requests -system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined +system.physmem.avgGap 66260.10 # Average gap between requests +system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 12000 # Time in different power states system.physmem.memoryStateTime::REF 780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22840500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) @@ -232,47 +232,24 @@ system.physmem.writeEnergy::0 0 # En system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ) -system.physmem.averagePower::0 856.166817 # Core power per rank (mW) -system.physmem.averagePower::1 786.636676 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 377 # Transaction distribution -system.membus.trans_dist::ReadResp 377 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 420 # Request fanout histogram -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1903 # Number of BP lookups -system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted +system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) +system.physmem.averagePower::0 856.107753 # Core power per rank (mW) +system.physmem.averagePower::1 786.272135 # Core power per rank (mW) +system.cpu.branchPred.lookups 1926 # Number of BP lookups +system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups -system.cpu.branchPred.BTBHits 325 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups +system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -358,268 +335,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 55822 # number of cpu cycles simulated +system.cpu.numCycles 55962 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedOps 5390 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.124674 # CPI: cycles per instruction -system.cpu.ipc 0.082476 # IPC: instructions per cycle -system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4799 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits -system.cpu.icache.overall_hits::total 1918 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses -system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses -system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.cpi 12.155083 # CPI: cycles per instruction +system.cpu.ipc 0.082270 # IPC: instructions per cycle +system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked +system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits -system.cpu.dcache.overall_hits::total 1897 # number of overall hits +system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits +system.cpu.dcache.overall_hits::total 1900 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses @@ -628,42 +381,42 @@ system.cpu.dcache.demand_misses::cpu.inst 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,30 +441,277 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4804 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits +system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses +system.cpu.icache.overall_misses::total 322 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 39 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses +system.cpu.l2cache.overall_misses::total 429 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26149000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2814500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 28963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 28963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.membus.trans_dist::ReadResp 378 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 421 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 421 # Request fanout histogram +system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |