diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-21 16:42:04 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-21 16:42:04 +0100 |
| commit | 9c8710430eb671b5e89f291b9f0a10b6156ac633 (patch) | |
| tree | d25fd7e25b7a326ddbfeb812ec4603eb5a5f2719 /tests/quick | |
| parent | 1fac3a292ad53811fec534d8a3e49cb86a70aeb8 (diff) | |
| download | gem5-9c8710430eb671b5e89f291b9f0a10b6156ac633.tar.xz | |
stats: Update stats to reflect ARM changes
Diffstat (limited to 'tests/quick')
7 files changed, 57 insertions, 57 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 48c46d88c..d386c51e7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1481321 # Simulator instruction rate (inst/s) -host_op_rate 1803271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28883760858 # Simulator tick rate (ticks/s) -host_mem_usage 624788 # Number of bytes of host memory used -host_seconds 96.38 # Real time elapsed on the host +host_inst_rate 829938 # Simulator instruction rate (inst/s) +host_op_rate 1010316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16182659197 # Simulator tick rate (ticks/s) +host_mem_usage 581892 # Number of bytes of host memory used +host_seconds 172.03 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -134,7 +134,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -204,7 +204,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 7ad483453..999575681 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802882797500 # Number of ticks simulated final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371763 # Simulator instruction rate (inst/s) -host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26186322462 # Simulator tick rate (ticks/s) -host_mem_usage 640448 # Number of bytes of host memory used -host_seconds 107.04 # Real time elapsed on the host +host_inst_rate 808897 # Simulator instruction rate (inst/s) +host_op_rate 985629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15441476365 # Simulator tick rate (ticks/s) +host_mem_usage 596572 # Number of bytes of host memory used +host_seconds 181.52 # Real time elapsed on the host sim_insts 146828219 # Number of instructions simulated sim_ops 178907974 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -153,7 +153,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -223,7 +223,7 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -683,7 +683,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -753,7 +753,7 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 6ed5da9b4..e85c0f849 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1429089 # Simulator instruction rate (inst/s) -host_op_rate 1739687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27865307050 # Simulator tick rate (ticks/s) -host_mem_usage 619548 # Number of bytes of host memory used -host_seconds 99.90 # Real time elapsed on the host +host_inst_rate 972221 # Simulator instruction rate (inst/s) +host_op_rate 1183523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18956985191 # Simulator tick rate (ticks/s) +host_mem_usage 578524 # Number of bytes of host memory used +host_seconds 146.85 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -134,7 +134,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -204,7 +204,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index b4dd1649b..3db65ab48 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.869789 # Nu sim_ticks 2869788970000 # Number of ticks simulated final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 932940 # Simulator instruction rate (inst/s) -host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20351712140 # Simulator tick rate (ticks/s) -host_mem_usage 661084 # Number of bytes of host memory used -host_seconds 141.01 # Real time elapsed on the host +host_inst_rate 540600 # Simulator instruction rate (inst/s) +host_op_rate 653886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11792964574 # Simulator tick rate (ticks/s) +host_mem_usage 618088 # Number of bytes of host memory used +host_seconds 243.35 # Real time elapsed on the host sim_insts 131553574 # Number of instructions simulated sim_ops 159121622 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -440,7 +440,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3392 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -526,7 +526,7 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1383,7 +1383,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1980 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1472,7 +1472,7 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 034b36479..118399814 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 987334 # Simulator instruction rate (inst/s) -host_op_rate 1190416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25545157236 # Simulator tick rate (ticks/s) -host_mem_usage 619552 # Number of bytes of host memory used -host_seconds 113.90 # Real time elapsed on the host +host_inst_rate 567099 # Simulator instruction rate (inst/s) +host_op_rate 683745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14672489619 # Simulator tick rate (ticks/s) +host_mem_usage 579808 # Number of bytes of host memory used +host_seconds 198.30 # Real time elapsed on the host sim_insts 112457035 # Number of instructions simulated sim_ops 135588119 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -404,7 +404,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -484,7 +484,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 5b86ad370..cb49bb6de 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783854 # Nu sim_ticks 2783853866500 # Number of ticks simulated final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1399722 # Simulator instruction rate (inst/s) -host_op_rate 1703936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27292901384 # Simulator tick rate (ticks/s) -host_mem_usage 623636 # Number of bytes of host memory used -host_seconds 102.00 # Real time elapsed on the host +host_inst_rate 812896 # Simulator instruction rate (inst/s) +host_op_rate 989570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15850505887 # Simulator tick rate (ticks/s) +host_mem_usage 582360 # Number of bytes of host memory used +host_seconds 175.63 # Real time elapsed on the host sim_insts 142770436 # Number of instructions simulated sim_ops 173800089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -151,7 +151,7 @@ system.cpu0.dtb.flush_tlb 2813 # Nu system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3231 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3167 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -221,7 +221,7 @@ system.cpu0.itb.flush_tlb 2813 # Nu system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1843 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -543,7 +543,7 @@ system.cpu1.dtb.flush_tlb 2817 # Nu system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3189 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3135 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -613,7 +613,7 @@ system.cpu1.itb.flush_tlb 2817 # Nu system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1961 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index b8ac8a573..e9a2fc5f7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.903880 # Nu sim_ticks 2903879904500 # Number of ticks simulated final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 952808 # Simulator instruction rate (inst/s) -host_op_rate 1148802 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24600165137 # Simulator tick rate (ticks/s) -host_mem_usage 624836 # Number of bytes of host memory used -host_seconds 118.04 # Real time elapsed on the host +host_inst_rate 551812 # Simulator instruction rate (inst/s) +host_op_rate 665321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14247014061 # Simulator tick rate (ticks/s) +host_mem_usage 583128 # Number of bytes of host memory used +host_seconds 203.82 # Real time elapsed on the host sim_insts 112472358 # Number of instructions simulated sim_ops 135608167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -436,7 +436,7 @@ system.cpu0.dtb.flush_tlb 2937 # Nu system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4577 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4513 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 883 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -518,7 +518,7 @@ system.cpu0.itb.flush_tlb 2937 # Nu system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2718 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2654 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1071,7 +1071,7 @@ system.cpu1.dtb.flush_tlb 2933 # Nu system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3948 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1153,7 +1153,7 @@ system.cpu1.itb.flush_tlb 2933 # Nu system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2384 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2325 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |