diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
| commit | a7e27f9a82300f213b268264e1dede222d26bd4d (patch) | |
| tree | 905f84d6e06111d4a243c18a1899e932646bdced /tests/quick | |
| parent | 2342aa2ebbb9dfe232eafcd20f01a8dd95ebfcc0 (diff) | |
| download | gem5-a7e27f9a82300f213b268264e1dede222d26bd4d.tar.xz | |
tests: updates for stat name change
Diffstat (limited to 'tests/quick')
19 files changed, 185 insertions, 185 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index fb1ddd9ef..41814d32d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:00:29 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:14:52 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 6483a471a..4a581cbe3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 150919 # Simulator instruction rate (inst/s) -host_mem_usage 203704 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 290889761 # Simulator tick rate (ticks/s) +host_inst_rate 96993 # Simulator instruction rate (inst/s) +host_mem_usage 206980 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 187197945 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -252,16 +252,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index fc9118372..8a87312b4 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:04:56 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:15:23 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index e80a12bfa..b8b5c99cd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106844 # Simulator instruction rate (inst/s) -host_mem_usage 202600 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 323591910 # Simulator tick rate (ticks/s) +host_inst_rate 66320 # Simulator instruction rate (inst/s) +host_mem_usage 205872 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 201598879 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -251,16 +251,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index ca0b775a3..f5ea06dc5 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:32:41 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 15:18:29 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index d620e2c6d..1ac2ece63 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117635 # Simulator instruction rate (inst/s) -host_mem_usage 212912 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 220680920 # Simulator tick rate (ticks/s) +host_inst_rate 81044 # Simulator instruction rate (inst/s) +host_mem_usage 215360 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 152195453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1171 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 560 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1171 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 560 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 5852e6d08..095fea48a 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:18:54 -M5 started Apr 19 2011 12:19:08 +M5 compiled Apr 21 2011 13:26:02 +M5 started Apr 21 2011 13:26:16 M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index cdb83d87c..57f562650 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109180 # Simulator instruction rate (inst/s) -host_mem_usage 204504 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 269299917 # Simulator tick rate (ticks/s) +host_inst_rate 83007 # Simulator instruction rate (inst/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 204865540 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -245,16 +245,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 945 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 202 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index e5517f525..7f3c6560c 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 32051064. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 34160904. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 5a9dfcd0e..cc20667bc 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:26 -M5 started Apr 19 2011 12:19:32 +M5 compiled Apr 21 2011 13:26:57 +M5 started Apr 21 2011 13:27:10 M5 executing on maize command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 7ecc0010b..082e541b8 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146379 # Simulator instruction rate (inst/s) -host_mem_usage 202304 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 293581871 # Simulator tick rate (ticks/s) +host_inst_rate 98738 # Simulator instruction rate (inst/s) +host_mem_usage 204672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 198408181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -245,16 +245,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 704 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 390 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 704 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 390 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 79df40ec6..f23e1efe6 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:38:12 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 14:05:23 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 177a37ea2..71886c36a 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 147922 # Simulator instruction rate (inst/s) -host_mem_usage 208856 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 171003814 # Simulator tick rate (ticks/s) +host_inst_rate 99680 # Simulator instruction rate (inst/s) +host_mem_usage 212240 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 115331857 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -232,16 +232,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 69 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1026 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 683 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1026 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 683 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 138b08408..5cdcc3460 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:00:40 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:15:44 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 93b62df2d..fe96eb65d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136040 # Simulator instruction rate (inst/s) -host_mem_usage 204288 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 149415554 # Simulator tick rate (ticks/s) +host_inst_rate 78127 # Simulator instruction rate (inst/s) +host_mem_usage 207556 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 85893759 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -388,26 +388,26 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1178 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 386 # Number of stores squashed -system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1143 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 334 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1178 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 386 # Number of stores squashed +system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread1.squashedLoads 1143 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedStores 334 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 1dc2f9c34..67bff692e 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:19:52 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:28:40 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 89a5a939e..db37ab210 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 110747 # Simulator instruction rate (inst/s) -host_mem_usage 203956 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 142631877 # Simulator tick rate (ticks/s) +host_inst_rate 79158 # Simulator instruction rate (inst/s) +host_mem_usage 209796 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 101982426 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 818 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 446 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 818 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 446 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index c40feed46..a126d9514 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:19:52 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:27:31 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 2fc95f0fc..6a03641e3 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 211769 # Simulator instruction rate (inst/s) -host_mem_usage 214500 # Number of bytes of host memory used -host_seconds 5.45 # Real time elapsed on the host -host_tick_rate 21567548 # Simulator tick rate (ticks/s) +host_inst_rate 107432 # Simulator instruction rate (inst/s) +host_mem_usage 220336 # Number of bytes of host memory used +host_seconds 10.73 # Real time elapsed on the host +host_tick_rate 10941647 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1153138 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated @@ -244,16 +244,16 @@ system.cpu0.iew.iewIdleCycles 0 # Nu system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewSquashCycles 2044 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 85880 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1671 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 1054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.forwLoads 85880 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.squashedLoads 1671 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedStores 1054 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 817 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly @@ -639,16 +639,16 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 37142 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 1440 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 770 # Number of stores squashed +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.forwLoads 37142 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.squashedLoads 1440 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedStores 770 # Number of stores squashed system.cpu1.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 196 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 990 # Number of branches that were predicted taken incorrectly @@ -1033,16 +1033,16 @@ system.cpu2.iew.iewIdleCycles 0 # Nu system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking -system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 40852 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 1554 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 772 # Number of stores squashed +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.forwLoads 40852 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.squashedLoads 1554 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedStores 772 # Number of stores squashed system.cpu2.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu2.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.predictedTakenIncorrect 996 # Number of branches that were predicted taken incorrectly @@ -1427,16 +1427,16 @@ system.cpu3.iew.iewIdleCycles 0 # Nu system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu3.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 24834 # Number of loads that had data forwarded from stores -system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 1517 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 742 # Number of stores squashed +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.forwLoads 24834 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.squashedLoads 1517 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedStores 742 # Number of stores squashed system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu3.iew.predictedNotTakenIncorrect 182 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.predictedTakenIncorrect 1011 # Number of branches that were predicted taken incorrectly |