diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
| commit | b006ad26d45dae3e336d7fc422adab0a330ba24a (patch) | |
| tree | 306fd2f75944fe4ad8f19f0a374d7c72ad97a5cc /tests/quick | |
| parent | 5a1dea51d2d4e2798eade7bbe3362098fc5f7f91 (diff) | |
| download | gem5-b006ad26d45dae3e336d7fc422adab0a330ba24a.tar.xz | |
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
Diffstat (limited to 'tests/quick')
50 files changed, 3878 insertions, 4678 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 41f61bd3d..90f1f17e3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu sim_ticks 1869357988000 # Number of ticks simulated final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1993950 # Simulator instruction rate (inst/s) -host_op_rate 1993950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57344769220 # Simulator tick rate (ticks/s) -host_mem_usage 333724 # Number of bytes of host memory used -host_seconds 32.60 # Real time elapsed on the host +host_inst_rate 1670594 # Simulator instruction rate (inst/s) +host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48045239456 # Simulator tick rate (ticks/s) +host_mem_usage 332628 # Number of bytes of host memory used +host_seconds 38.91 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -301,11 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks system.cpu0.dcache.writebacks::total 633127 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -352,11 +349,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks system.cpu0.icache.writebacks::total 618292 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -589,11 +583,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks system.cpu1.dcache.writebacks::total 144536 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 380647 # number of replacements system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. @@ -639,11 +630,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks system.cpu1.icache.writebacks::total 380647 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -704,18 +692,18 @@ system.iocache.ReadReq_misses::tsunami.ide 179 # system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses -system.iocache.demand_misses::total 179 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 179 # number of overall misses -system.iocache.overall_misses::total 179 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -730,11 +718,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 999922 # number of replacements system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. @@ -875,11 +860,8 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 80923 # number of writebacks system.l2c.writebacks::total 80923 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 25be00c51..84bdf9ee5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829331993500 # Number of ticks simulated final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1828258 # Simulator instruction rate (inst/s) -host_op_rate 1828257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55705727715 # Simulator tick rate (ticks/s) -host_mem_usage 331420 # Number of bytes of host memory used -host_seconds 32.84 # Real time elapsed on the host +host_inst_rate 1840131 # Simulator instruction rate (inst/s) +host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56067507873 # Simulator tick rate (ticks/s) +host_mem_usage 330836 # Number of bytes of host memory used +host_seconds 32.63 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -282,11 +282,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks system.cpu.dcache.writebacks::total 833475 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919603 # number of replacements system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. @@ -333,11 +330,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 919603 # number of writebacks system.cpu.icache.writebacks::total 919603 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 992419 # number of replacements system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks. @@ -430,11 +424,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks system.cpu.l2cache.writebacks::total 74359 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -532,18 +523,18 @@ system.iocache.ReadReq_misses::tsunami.ide 174 # system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -558,11 +549,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7184 # Transaction distribution system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3cac0b91e..e58364a4b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.982593 # Nu sim_ticks 1982592736000 # Number of ticks simulated final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753764 # Simulator instruction rate (inst/s) -host_op_rate 753764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24497172234 # Simulator tick rate (ticks/s) -host_mem_usage 320072 # Number of bytes of host memory used -host_seconds 80.93 # Real time elapsed on the host +host_inst_rate 1178528 # Simulator instruction rate (inst/s) +host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38301918928 # Simulator tick rate (ticks/s) +host_mem_usage 332884 # Number of bytes of host memory used +host_seconds 51.76 # Real time elapsed on the host sim_insts 61003209 # Number of instructions simulated sim_ops 61003209 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -580,8 +580,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks system.cpu0.dcache.writebacks::total 672790 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses @@ -616,10 +614,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses @@ -646,11 +642,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 686545 # number of replacements system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. @@ -708,8 +701,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks system.cpu0.icache.writebacks::total 686545 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses @@ -736,7 +727,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -989,8 +979,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks system.cpu1.dcache.writebacks::total 119726 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses @@ -1025,10 +1013,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses @@ -1055,11 +1041,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 331529 # number of replacements system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. @@ -1119,8 +1102,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks system.cpu1.icache.writebacks::total 331529 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses @@ -1147,7 +1128,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1232,26 +1212,26 @@ system.iocache.ReadReq_misses::tsunami.ide 175 # system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1264,36 +1244,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1306,11 +1284,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency system.l2c.tags.replacements 342136 # number of replacements system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. @@ -1501,8 +1478,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 79408 # number of writebacks system.l2c.writebacks::total 79408 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits @@ -1575,12 +1550,9 @@ system.l2c.overall_mshr_miss_latency::total 47046710502 # system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses @@ -1636,13 +1608,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 7201 # Transaction distribution system.membus.trans_dist::ReadResp 292681 # Transaction distribution system.membus.trans_dist::WriteReq 14131 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 04e45bbeb..b4533a137 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1255554 # Simulator instruction rate (inst/s) -host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43383023327 # Simulator tick rate (ticks/s) -host_mem_usage 332188 # Number of bytes of host memory used -host_seconds 44.75 # Real time elapsed on the host +host_inst_rate 1048317 # Simulator instruction rate (inst/s) +host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36222399744 # Simulator tick rate (ticks/s) +host_mem_usage 330588 # Number of bytes of host memory used +host_seconds 53.59 # Real time elapsed on the host sim_insts 56182685 # Number of instructions simulated sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -560,8 +560,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks system.cpu.dcache.writebacks::total 834944 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses @@ -592,10 +590,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses @@ -618,11 +614,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency system.cpu.icache.tags.replacements 928931 # number of replacements system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. @@ -682,8 +675,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 928931 # number of writebacks system.cpu.icache.writebacks::total 928931 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses @@ -710,7 +701,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 336393 # number of replacements system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. @@ -831,8 +821,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks system.cpu.l2cache.writebacks::total 74281 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses @@ -871,10 +859,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses @@ -905,11 +891,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1040,26 +1023,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 # system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1072,36 +1055,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1114,11 +1095,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292274 # Transaction distribution system.membus.trans_dist::WriteReq 9653 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index f7d0d7b39..b93cd163b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1852974 # Simulator instruction rate (inst/s) -host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36130480826 # Simulator tick rate (ticks/s) -host_mem_usage 581484 # Number of bytes of host memory used -host_seconds 77.05 # Real time elapsed on the host +host_inst_rate 1211130 # Simulator instruction rate (inst/s) +host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23615387886 # Simulator tick rate (ticks/s) +host_mem_usage 581436 # Number of bytes of host memory used +host_seconds 117.88 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1698998 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu.icache.writebacks::total 1698998 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. @@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index df10533fc..4464ff885 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu sim_ticks 2802882879000 # Number of ticks simulated final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1272297 # Simulator instruction rate (inst/s) -host_op_rate 1550275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24287502010 # Simulator tick rate (ticks/s) -host_mem_usage 596572 # Number of bytes of host memory used -host_seconds 115.40 # Real time elapsed on the host +host_inst_rate 1338296 # Simulator instruction rate (inst/s) +host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25547394462 # Simulator tick rate (ticks/s) +host_mem_usage 592020 # Number of bytes of host memory used +host_seconds 109.71 # Real time elapsed on the host sim_insts 146828562 # Number of instructions simulated sim_ops 178908371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -365,11 +365,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks system.cpu0.dcache.writebacks::total 693475 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109624 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. @@ -416,11 +413,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks system.cpu0.icache.writebacks::total 1109624 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue @@ -555,11 +549,8 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.fast_writes 0 # number of fast writes performed -system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks system.cpu0.l2cache.writebacks::total 193020 # number of writebacks -system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -876,11 +867,8 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks system.cpu1.dcache.writebacks::total 191946 # number of writebacks -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523401 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. @@ -926,11 +914,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks system.cpu1.icache.writebacks::total 523401 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue @@ -1064,11 +1049,8 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.fast_writes 0 # number of fast writes performed -system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks system.cpu1.l2cache.writebacks::total 32706 # number of writebacks -system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1178,18 +1160,18 @@ system.iocache.ReadReq_misses::realview.ide 252 # system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses -system.iocache.demand_misses::total 252 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 252 # number of overall misses -system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses +system.iocache.demand_misses::total 36476 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36476 # number of overall misses +system.iocache.overall_misses::total 36476 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1204,11 +1186,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 107729 # number of replacements system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. @@ -1384,11 +1363,8 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 96268 # number of writebacks system.l2c.writebacks::total 96268 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43996 # Transaction distribution system.membus.trans_dist::ReadResp 75724 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ef75cc834..d5c7e4211 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1173204 # Simulator instruction rate (inst/s) -host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22875895912 # Simulator tick rate (ticks/s) -host_mem_usage 581200 # Number of bytes of host memory used -host_seconds 121.69 # Real time elapsed on the host +host_inst_rate 1225194 # Simulator instruction rate (inst/s) +host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23889629831 # Simulator tick rate (ticks/s) +host_mem_usage 578692 # Number of bytes of host memory used +host_seconds 116.53 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -346,11 +346,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks system.cpu.dcache.writebacks::total 682017 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1698998 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -398,11 +395,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu.icache.writebacks::total 1698998 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. @@ -536,11 +530,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks system.cpu.l2cache.writebacks::total 101950 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -651,18 +642,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -677,11 +668,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index abcd4eac1..28d366488 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.871806 # Nu sim_ticks 2871806231000 # Number of ticks simulated final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 937604 # Simulator instruction rate (inst/s) -host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20478123685 # Simulator tick rate (ticks/s) -host_mem_usage 614632 # Number of bytes of host memory used -host_seconds 140.24 # Real time elapsed on the host +host_inst_rate 717242 # Simulator instruction rate (inst/s) +host_op_rate 867543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15665668571 # Simulator tick rate (ticks/s) +host_mem_usage 616200 # Number of bytes of host memory used +host_seconds 183.32 # Real time elapsed on the host sim_insts 131483712 # Number of instructions simulated sim_ops 159036662 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -687,8 +687,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks system.cpu0.dcache.writebacks::total 733230 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits @@ -739,10 +737,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses @@ -775,11 +771,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1147026 # number of replacements system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks. @@ -838,8 +831,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks system.cpu0.icache.writebacks::total 1147026 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses @@ -878,7 +869,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue @@ -1080,8 +1070,6 @@ system.cpu0.l2cache.blocked::no_mshrs 0 # nu system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.fast_writes 0 # number of fast writes performed -system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks system.cpu0.l2cache.writebacks::total 231848 # number of writebacks @@ -1160,11 +1148,9 @@ system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses @@ -1224,12 +1210,9 @@ system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency -system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1629,8 +1612,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks system.cpu1.dcache.writebacks::total 148452 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits @@ -1679,10 +1660,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses @@ -1715,11 +1694,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 463484 # number of replacements system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. @@ -1778,8 +1754,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks system.cpu1.icache.writebacks::total 463484 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses @@ -1818,7 +1792,6 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue @@ -2015,8 +1988,6 @@ system.cpu1.l2cache.blocked::no_mshrs 0 # nu system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.fast_writes 0 # number of fast writes performed -system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks system.cpu1.l2cache.writebacks::total 26072 # number of writebacks @@ -2093,11 +2064,9 @@ system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses @@ -2157,12 +2126,9 @@ system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency -system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -2333,26 +2299,26 @@ system.iocache.ReadReq_misses::realview.ide 255 # system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses +system.iocache.demand_misses::total 36479 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36479 # number of overall misses +system.iocache.overall_misses::total 36479 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2365,36 +2331,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2407,11 +2371,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency system.l2c.tags.replacements 124374 # number of replacements system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. @@ -2693,8 +2656,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 97172 # number of writebacks system.l2c.writebacks::total 97172 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits @@ -2798,14 +2759,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses @@ -2885,15 +2843,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 44095 # Transaction distribution system.membus.trans_dist::ReadResp 214453 # Transaction distribution system.membus.trans_dist::WriteReq 30922 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 913ae877a..da0ada0fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 929184 # Simulator instruction rate (inst/s) -host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24040663881 # Simulator tick rate (ticks/s) -host_mem_usage 581600 # Number of bytes of host memory used -host_seconds 121.03 # Real time elapsed on the host +host_inst_rate 812558 # Simulator instruction rate (inst/s) +host_op_rate 979692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21023218607 # Simulator tick rate (ticks/s) +host_mem_usage 578440 # Number of bytes of host memory used +host_seconds 138.40 # Real time elapsed on the host sim_insts 112457033 # Number of instructions simulated sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -651,8 +651,6 @@ system.cpu.dcache.blocked::no_mshrs 20 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks system.cpu.dcache.writebacks::total 683846 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits @@ -699,10 +697,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6278149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6278149500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses @@ -733,11 +729,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143 system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106903.970916 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106903.970916 # average overall mshr uncacheable latency system.cpu.icache.tags.replacements 1695721 # number of replacements system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. @@ -797,8 +790,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1695721 # number of writebacks system.cpu.icache.writebacks::total 1695721 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696239 # number of ReadReq MSHR misses @@ -837,7 +828,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 87565 # number of replacements system.cpu.l2cache.tags.tagsinuse 64865.223598 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4544536 # Total number of references to valid blocks. @@ -1017,8 +1007,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks system.cpu.l2cache.writebacks::total 81185 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses @@ -1078,11 +1066,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total 18759768500 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888804000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918570000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772572500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772572500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661376500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691142500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5888804000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6918570000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses @@ -1132,12 +1118,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100274.217992 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 102120.621707 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1305,26 +1288,26 @@ system.iocache.ReadReq_misses::realview.ide 228 # system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses -system.iocache.demand_misses::total 228 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 228 # number of overall misses -system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses +system.iocache.demand_misses::total 36452 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36452 # number of overall misses +system.iocache.overall_misses::total 36452 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4577313527 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577313527 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577313527 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577313527 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1337,36 +1320,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125570.984500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125570.984500 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125570.984500 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753302003 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753302003 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753302003 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753302003 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1379,11 +1360,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75532.261687 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75532.261687 # average overall mshr miss latency system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index e0084d588..254a8cf36 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1278958 # Simulator instruction rate (inst/s) -host_op_rate 1556926 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24937950041 # Simulator tick rate (ticks/s) -host_mem_usage 579412 # Number of bytes of host memory used -host_seconds 111.63 # Real time elapsed on the host +host_inst_rate 1181524 # Simulator instruction rate (inst/s) +host_op_rate 1438316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23038118447 # Simulator tick rate (ticks/s) +host_mem_usage 579724 # Number of bytes of host memory used +host_seconds 120.84 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -391,11 +391,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks system.cpu0.dcache.writebacks::total 682241 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1698998 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. @@ -457,11 +454,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks system.cpu0.icache.writebacks::total 1698998 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -728,18 +722,18 @@ system.iocache.ReadReq_misses::realview.ide 240 # system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses -system.iocache.demand_misses::total 240 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 240 # number of overall misses -system.iocache.overall_misses::total 240 # number of overall misses +system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses +system.iocache.demand_misses::total 36464 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36464 # number of overall misses +system.iocache.overall_misses::total 36464 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -754,11 +748,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. @@ -948,11 +939,8 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 101944 # number of writebacks system.l2c.writebacks::total 101944 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cd3a72dfc..e91a37dbe 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909645 # Nu sim_ticks 2909644861500 # Number of ticks simulated final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 955579 # Simulator instruction rate (inst/s) -host_op_rate 1152126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24724694945 # Simulator tick rate (ticks/s) -host_mem_usage 580436 # Number of bytes of host memory used -host_seconds 117.68 # Real time elapsed on the host +host_inst_rate 753896 # Simulator instruction rate (inst/s) +host_op_rate 908960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19506336140 # Simulator tick rate (ticks/s) +host_mem_usage 580236 # Number of bytes of host memory used +host_seconds 149.16 # Real time elapsed on the host sim_insts 112454211 # Number of instructions simulated sim_ops 135584166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -721,8 +721,6 @@ system.cpu0.dcache.blocked::no_mshrs 22 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.727273 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 683901 # number of writebacks system.cpu0.dcache.writebacks::total 683901 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 477 # number of ReadReq MSHR hits @@ -789,12 +787,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2495078000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594854500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089932500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5543496500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824550500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368047000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3048418500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3229696000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278114500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses @@ -838,13 +833,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1695677 # number of replacements system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. @@ -924,8 +915,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1695677 # number of writebacks system.cpu0.icache.writebacks::total 1695677 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840174 # number of ReadReq MSHR misses @@ -982,7 +971,6 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1315,26 +1303,26 @@ system.iocache.ReadReq_misses::realview.ide 228 # system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses -system.iocache.demand_misses::total 228 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 228 # number of overall misses -system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses +system.iocache.demand_misses::total 36452 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36452 # number of overall misses +system.iocache.overall_misses::total 36452 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28181877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28181877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28181877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28181877 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 4577089020 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577089020 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577089020 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577089020 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1347,36 +1335,34 @@ system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123604.723684 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125564.825524 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125564.825524 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16781877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16781877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16781877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16781877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753072506 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753072506 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753072506 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753072506 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1389,11 +1375,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency system.l2c.tags.replacements 87562 # number of replacements system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. @@ -1651,8 +1636,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 81183 # number of writebacks system.l2c.writebacks::total 81183 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses @@ -1741,14 +1724,11 @@ system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2860870000 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3027916000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 6918904000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2341022000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431506500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4772528500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5201892000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2860870000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459422500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11691432500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3027916000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6918904000 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for ReadReq accesses @@ -1822,15 +1802,11 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 926ea5f21..422618199 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112151729000 # Number of ticks simulated final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1266983 # Simulator instruction rate (inst/s) -host_op_rate 2593792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32374197845 # Simulator tick rate (ticks/s) -host_mem_usage 659352 # Number of bytes of host memory used -host_seconds 157.91 # Real time elapsed on the host +host_inst_rate 1369712 # Simulator instruction rate (inst/s) +host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34999130987 # Simulator tick rate (ticks/s) +host_mem_usage 614748 # Number of bytes of host memory used +host_seconds 146.07 # Real time elapsed on the host sim_insts 200067055 # Number of instructions simulated sim_ops 409581065 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -174,11 +174,8 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks system.cpu.dcache.writebacks::total 1535790 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks. @@ -225,11 +222,8 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs 0 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 792340 # number of replacements system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks. @@ -277,11 +271,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 792340 # number of writebacks system.cpu.icache.writebacks::total 792340 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. @@ -332,11 +323,8 @@ system.cpu.itb_walker_cache.blocked::no_mshrs 0 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks -system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106202 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks. @@ -457,11 +445,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks system.cpu.l2cache.writebacks::total 98175 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -575,18 +560,18 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 903 system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses -system.iocache.demand_misses::total 903 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses -system.iocache.overall_misses::total 903 # number of overall misses +system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses +system.iocache.demand_misses::total 47623 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses +system.iocache.overall_misses::total 47623 # number of overall misses system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -601,11 +586,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 13857337 # Transaction distribution system.membus.trans_dist::ReadResp 13903644 # Transaction distribution system.membus.trans_dist::WriteReq 13943 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 38633f47f..94a3f35b5 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu sim_ticks 5194946000500 # Number of ticks simulated final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 842553 # Simulator instruction rate (inst/s) -host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34079125299 # Simulator tick rate (ticks/s) -host_mem_usage 659848 # Number of bytes of host memory used -host_seconds 152.44 # Real time elapsed on the host +host_inst_rate 910377 # Simulator instruction rate (inst/s) +host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36822413305 # Simulator tick rate (ticks/s) +host_mem_usage 616280 # Number of bytes of host memory used +host_seconds 141.08 # Real time elapsed on the host sim_insts 128436892 # Number of instructions simulated sim_ops 247560077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -451,8 +451,6 @@ system.cpu.dcache.blocked::no_mshrs 514 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks system.cpu.dcache.writebacks::total 1540773 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits @@ -491,10 +489,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses @@ -517,11 +513,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks. @@ -581,8 +574,6 @@ system.cpu.dtb_walker_cache.blocked::no_mshrs 0 system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses @@ -609,7 +600,6 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.5 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 790489 # number of replacements system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks. @@ -669,8 +659,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 790489 # number of writebacks system.cpu.icache.writebacks::total 790489 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses @@ -697,7 +685,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406 system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. @@ -761,8 +748,6 @@ system.cpu.itb_walker_cache.blocked::no_mshrs 0 system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses @@ -789,7 +774,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.8 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency -system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 87287 # number of replacements system.cpu.l2cache.tags.tagsinuse 64590.438483 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4366272 # Total number of references to valid blocks. @@ -950,8 +934,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks system.cpu.l2cache.writebacks::total 80702 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses @@ -1004,10 +986,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500 system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626267500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626267500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90929022500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90929022500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses @@ -1052,11 +1032,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1228,26 +1205,26 @@ system.iocache.ReadReq_misses::pc.south_bridge.ide 842 system.iocache.ReadReq_misses::total 842 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses -system.iocache.demand_misses::total 842 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses -system.iocache.overall_misses::total 842 # number of overall misses +system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses +system.iocache.demand_misses::total 47562 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses +system.iocache.overall_misses::total 47562 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles -system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1260,36 +1237,34 @@ system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1302,11 +1277,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency system.membus.trans_dist::ReadReq 546346 # Transaction distribution system.membus.trans_dist::ReadResp 588523 # Transaction distribution system.membus.trans_dist::WriteReq 13920 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 39184c503..0faba0dc5 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000037 # Nu sim_ticks 37494000 # Number of ticks simulated final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257461 # Simulator instruction rate (inst/s) -host_op_rate 257361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504149892 # Simulator tick rate (ticks/s) +host_inst_rate 141195 # Simulator instruction rate (inst/s) +host_op_rate 141164 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825166364 # Simulator tick rate (ticks/s) host_mem_usage 252900 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_seconds 0.05 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits @@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. @@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses @@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -628,8 +622,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses @@ -678,7 +670,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c617feb20..c082db4f6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22019000 # Number of ticks simulated final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66596 # Simulator instruction rate (inst/s) -host_op_rate 66584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 229093695 # Simulator tick rate (ticks/s) -host_mem_usage 228860 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 140516 # Simulator instruction rate (inst/s) +host_op_rate 140486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484379589 # Simulator tick rate (ticks/s) +host_mem_usage 253664 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -656,8 +656,6 @@ system.cpu.dcache.blocked::no_mshrs 43 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits @@ -698,7 +696,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. @@ -756,8 +753,6 @@ system.cpu.icache.blocked::no_mshrs 1 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits @@ -788,7 +783,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -878,8 +872,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses @@ -928,7 +920,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 9846d6881..1dfe1dcb3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 35682500 # Number of ticks simulated final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44587 # Simulator instruction rate (inst/s) -host_op_rate 44581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 248411942 # Simulator tick rate (ticks/s) -host_mem_usage 226904 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 421865 # Simulator instruction rate (inst/s) +host_op_rate 421312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2345119890 # Simulator tick rate (ticks/s) +host_mem_usage 251096 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. @@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses @@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses @@ -448,7 +440,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 8e060c84e..165263111 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20320000 # Number of ticks simulated final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31344 # Simulator instruction rate (inst/s) -host_op_rate 31334 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 243267003 # Simulator tick rate (ticks/s) -host_mem_usage 230348 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 183657 # Simulator instruction rate (inst/s) +host_op_rate 183501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1441333472 # Simulator tick rate (ticks/s) +host_mem_usage 251592 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -412,8 +412,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits @@ -454,7 +452,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks. @@ -512,8 +509,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses @@ -538,7 +533,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778 system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -622,8 +616,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses @@ -672,7 +664,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 619c657d2..86178d83d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12409500 # Number of ticks simulated final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12168 # Simulator instruction rate (inst/s) -host_op_rate 12166 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63007670 # Simulator tick rate (ticks/s) -host_mem_usage 231556 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 67215 # Simulator instruction rate (inst/s) +host_op_rate 67181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 349098234 # Simulator tick rate (ticks/s) +host_mem_usage 252356 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -655,8 +655,6 @@ system.cpu.dcache.blocked::no_mshrs 6 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits @@ -697,7 +695,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks. @@ -755,8 +752,6 @@ system.cpu.icache.blocked::no_mshrs 2 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits @@ -787,7 +782,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -871,8 +865,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses @@ -921,7 +913,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 42abe9c49..3011688bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18239500 # Number of ticks simulated final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29160 # Simulator instruction rate (inst/s) -host_op_rate 29152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206272099 # Simulator tick rate (ticks/s) -host_mem_usage 229424 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 277034 # Simulator instruction rate (inst/s) +host_op_rate 276552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1954350939 # Simulator tick rate (ticks/s) +host_mem_usage 249792 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -190,8 +190,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses @@ -224,7 +222,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. @@ -282,8 +279,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses @@ -308,7 +303,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. @@ -392,8 +386,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses @@ -442,7 +434,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 02dbcdc04..cb66660d4 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29977500 # Number of ticks simulated final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167534 # Simulator instruction rate (inst/s) -host_op_rate 196036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1088591965 # Simulator tick rate (ticks/s) -host_mem_usage 269228 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 89930 # Simulator instruction rate (inst/s) +host_op_rate 105235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 584953104 # Simulator tick rate (ticks/s) +host_mem_usage 268772 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -504,8 +504,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits @@ -546,7 +544,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4 # number of replacements system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. @@ -604,8 +601,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 4 # number of writebacks system.cpu.icache.writebacks::total 4 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses @@ -632,7 +627,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. @@ -730,8 +724,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits @@ -786,7 +778,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index b78b358b1..58e5912c9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 9367 # Simulator instruction rate (inst/s) -host_op_rate 10970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35022410 # Simulator tick rate (ticks/s) -host_mem_usage 245324 # Number of bytes of host memory used -host_seconds 0.49 # Real time elapsed on the host +host_inst_rate 43939 # Simulator instruction rate (inst/s) +host_op_rate 51450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164826819 # Simulator tick rate (ticks/s) +host_mem_usage 269540 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -878,8 +878,6 @@ system.cpu.dcache.blocked::no_mshrs 3 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits @@ -922,7 +920,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. @@ -980,8 +977,6 @@ system.cpu.icache.blocked::no_mshrs 5 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits @@ -1014,7 +1009,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. @@ -1112,8 +1106,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits @@ -1168,7 +1160,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a846c7a0c..d43357405 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 9099 # Simulator instruction rate (inst/s) -host_op_rate 10656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37131488 # Simulator tick rate (ticks/s) -host_mem_usage 241712 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host +host_inst_rate 49791 # Simulator instruction rate (inst/s) +host_op_rate 58299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203978556 # Simulator tick rate (ticks/s) +host_mem_usage 266084 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -759,8 +759,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits @@ -805,7 +803,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 44 # number of replacements system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. @@ -863,8 +860,6 @@ system.cpu.icache.blocked::no_mshrs 95 # nu system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits @@ -897,7 +892,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue @@ -1007,8 +1001,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits @@ -1079,7 +1071,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 83487a6ff..facfa8248 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 286813 # Simulator instruction rate (inst/s) -host_op_rate 333728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1769783602 # Simulator tick rate (ticks/s) -host_mem_usage 267436 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 441317 # Simulator instruction rate (inst/s) +host_op_rate 514292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726097982 # Simulator tick rate (ticks/s) +host_mem_usage 267744 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -284,8 +284,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses @@ -318,7 +316,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. @@ -376,8 +373,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1 # number of writebacks system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses @@ -404,7 +399,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. @@ -498,8 +492,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses @@ -548,7 +540,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 69eab7f94..815eb0bfe 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 22532000 # Number of ticks simulated final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106399 # Simulator instruction rate (inst/s) -host_op_rate 106364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 479269632 # Simulator tick rate (ticks/s) -host_mem_usage 251364 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 65525 # Simulator instruction rate (inst/s) +host_op_rate 65509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 295199371 # Simulator tick rate (ticks/s) +host_mem_usage 251356 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -640,8 +640,6 @@ system.cpu.dcache.blocked::no_mshrs 10 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits @@ -682,7 +680,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. @@ -740,8 +737,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 17 # number of writebacks system.cpu.icache.writebacks::total 17 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits @@ -774,7 +769,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. @@ -868,8 +862,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses @@ -918,7 +910,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index dc14a2b12..f975f616d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000034 # Nu sim_ticks 33932500 # Number of ticks simulated final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42153 # Simulator instruction rate (inst/s) -host_op_rate 42149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 253513577 # Simulator tick rate (ticks/s) -host_mem_usage 224784 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 442497 # Simulator instruction rate (inst/s) +host_op_rate 441783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2653552582 # Simulator tick rate (ticks/s) +host_mem_usage 249064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -176,8 +176,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -210,7 +208,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. @@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 13 # number of writebacks system.cpu.icache.writebacks::total 13 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses @@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. @@ -390,8 +384,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses @@ -440,7 +432,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 70134ae11..2c6934aef 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19908000 # Number of ticks simulated final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56421 # Simulator instruction rate (inst/s) -host_op_rate 56413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 194020204 # Simulator tick rate (ticks/s) -host_mem_usage 225060 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 130311 # Simulator instruction rate (inst/s) +host_op_rate 130281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 447700777 # Simulator tick rate (ticks/s) +host_mem_usage 249300 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -641,8 +641,6 @@ system.cpu.dcache.blocked::no_mshrs 6 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits @@ -683,7 +681,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. @@ -741,8 +738,6 @@ system.cpu.icache.blocked::no_mshrs 5 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits @@ -773,7 +768,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. @@ -867,8 +861,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses @@ -917,7 +909,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index a5edc52b5..ddd387c47 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30526500 # Number of ticks simulated final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33063 # Simulator instruction rate (inst/s) -host_op_rate 33056 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189395194 # Simulator tick rate (ticks/s) -host_mem_usage 228956 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 608531 # Simulator instruction rate (inst/s) +host_op_rate 607803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3479427932 # Simulator tick rate (ticks/s) +host_mem_usage 249516 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -158,8 +158,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses @@ -192,7 +190,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. @@ -250,8 +247,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses @@ -276,7 +271,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. @@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses @@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 9accffb70..3c1544f1d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21273500 # Number of ticks simulated final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39176 # Simulator instruction rate (inst/s) -host_op_rate 70969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151562567 # Simulator tick rate (ticks/s) -host_mem_usage 245924 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 70008 # Simulator instruction rate (inst/s) +host_op_rate 126817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 276755373 # Simulator tick rate (ticks/s) +host_mem_usage 271684 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -625,8 +625,6 @@ system.cpu.dcache.blocked::no_mshrs 3 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits @@ -665,7 +663,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. @@ -723,8 +720,6 @@ system.cpu.icache.blocked::no_mshrs 3 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits @@ -755,7 +750,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -845,8 +839,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses @@ -895,7 +887,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 79b38ccd2..b345a9c01 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30886500 # Number of ticks simulated final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79759 # Simulator instruction rate (inst/s) -host_op_rate 144442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 457524996 # Simulator tick rate (ticks/s) -host_mem_usage 247116 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 235920 # Simulator instruction rate (inst/s) +host_op_rate 427054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1352150005 # Simulator tick rate (ticks/s) +host_mem_usage 266824 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -161,8 +161,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses @@ -195,7 +193,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. @@ -253,8 +250,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses @@ -279,7 +274,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. @@ -369,8 +363,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses @@ -419,7 +411,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index ffcf45f3b..fcca5b721 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25580500 # Number of ticks simulated final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50796 # Simulator instruction rate (inst/s) -host_op_rate 50792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98611945 # Simulator tick rate (ticks/s) -host_mem_usage 229596 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 85448 # Simulator instruction rate (inst/s) +host_op_rate 85436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171120344 # Simulator tick rate (ticks/s) +host_mem_usage 253996 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -799,8 +799,6 @@ system.cpu.dcache.blocked::no_mshrs 130 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits @@ -841,7 +839,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements @@ -901,8 +898,6 @@ system.cpu.icache.blocked::no_mshrs 55 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 7 # number of writebacks system.cpu.icache.writebacks::total 7 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits @@ -935,7 +930,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements @@ -1031,8 +1025,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses @@ -1081,7 +1073,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d7b61e924..e76497684 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000029 # Nu sim_ticks 28845500 # Number of ticks simulated final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12271 # Simulator instruction rate (inst/s) -host_op_rate 12271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22902062 # Simulator tick rate (ticks/s) -host_mem_usage 227268 # Number of bytes of host memory used -host_seconds 1.18 # Real time elapsed on the host +host_inst_rate 68981 # Simulator instruction rate (inst/s) +host_op_rate 68975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137812851 # Simulator tick rate (ticks/s) +host_mem_usage 251992 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -621,8 +621,6 @@ system.cpu.dcache.blocked::no_mshrs 23 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits @@ -663,7 +661,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. @@ -721,8 +718,6 @@ system.cpu.icache.blocked::no_mshrs 2 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits @@ -753,7 +748,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -843,8 +837,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses @@ -893,7 +885,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 256c5877f..457c52bd3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 44282500 # Number of ticks simulated final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17930 # Simulator instruction rate (inst/s) -host_op_rate 17930 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52364992 # Simulator tick rate (ticks/s) -host_mem_usage 228848 # Number of bytes of host memory used -host_seconds 0.85 # Real time elapsed on the host +host_inst_rate 298703 # Simulator instruction rate (inst/s) +host_op_rate 298583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 871748609 # Simulator tick rate (ticks/s) +host_mem_usage 249440 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -162,8 +162,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses @@ -196,7 +194,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. @@ -254,8 +251,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses @@ -280,7 +275,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -370,8 +364,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses @@ -420,7 +412,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index b37d8b5b7..3c13d46b0 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000061 # Nu sim_ticks 61470000 # Number of ticks simulated final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62593 # Simulator instruction rate (inst/s) -host_op_rate 62569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 595804848 # Simulator tick rate (ticks/s) -host_mem_usage 614668 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 583425 # Simulator instruction rate (inst/s) +host_op_rate 580281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5518802940 # Simulator tick rate (ticks/s) +host_mem_usage 637904 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -409,8 +409,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -443,7 +441,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. @@ -501,8 +498,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses @@ -527,7 +522,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -647,8 +641,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses @@ -693,7 +685,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index f933f7176..60d51d141 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 411650 # Simulator instruction rate (inst/s) -host_op_rate 475781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4107877451 # Simulator tick rate (ticks/s) -host_mem_usage 655016 # Number of bytes of host memory used +host_inst_rate 523400 # Simulator instruction rate (inst/s) +host_op_rate 604831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5220928914 # Simulator tick rate (ticks/s) +host_mem_usage 655332 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated @@ -503,8 +503,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses @@ -537,7 +535,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 70 # number of replacements system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. @@ -595,8 +592,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses @@ -621,7 +616,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -744,8 +738,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses @@ -790,7 +782,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index c1870ce65..2c65c222a 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44023 # Simulator instruction rate (inst/s) -host_op_rate 44007 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 459268108 # Simulator tick rate (ticks/s) -host_mem_usage 612532 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 350541 # Simulator instruction rate (inst/s) +host_op_rate 350101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3650563038 # Simulator tick rate (ticks/s) +host_mem_usage 636120 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -395,8 +395,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -429,7 +427,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 94 # number of replacements system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. @@ -487,8 +484,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses @@ -513,7 +508,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -633,8 +627,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses @@ -679,7 +671,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 010db5b17..718f7b51e 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 486070 # Simulator instruction rate (inst/s) -host_op_rate 485474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4661655450 # Simulator tick rate (ticks/s) -host_mem_usage 680524 # Number of bytes of host memory used +host_inst_rate 388058 # Simulator instruction rate (inst/s) +host_op_rate 387570 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3721714769 # Simulator tick rate (ticks/s) +host_mem_usage 636836 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated @@ -382,8 +382,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses @@ -416,7 +414,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 71 # number of replacements system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. @@ -474,8 +471,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses @@ -500,7 +495,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -623,8 +617,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses @@ -669,7 +661,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 5f983df7d..e0706d7d4 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84620 # Simulator instruction rate (inst/s) -host_op_rate 152747 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 826790083 # Simulator tick rate (ticks/s) -host_mem_usage 634592 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 250477 # Simulator instruction rate (inst/s) +host_op_rate 451948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2445398371 # Simulator tick rate (ticks/s) +host_mem_usage 655164 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -381,8 +381,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses @@ -415,7 +413,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 58 # number of replacements system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. @@ -473,8 +470,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses @@ -499,7 +494,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -619,8 +613,6 @@ system.l2cache.blocked::no_mshrs 0 # nu system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.fast_writes 0 # number of fast writes performed -system.l2cache.cache_copies 0 # number of cache copies performed system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses @@ -665,7 +657,6 @@ system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 7b63e03f4..93c64ae72 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147149 # Nu sim_ticks 147148719500 # Number of ticks simulated final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1174056 # Simulator instruction rate (inst/s) -host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1907338487 # Simulator tick rate (ticks/s) -host_mem_usage 402756 # Number of bytes of host memory used -host_seconds 77.15 # Real time elapsed on the host +host_inst_rate 1067474 # Simulator instruction rate (inst/s) +host_op_rate 1072778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1734188097 # Simulator tick rate (ticks/s) +host_mem_usage 402040 # Number of bytes of host memory used +host_seconds 84.85 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -294,8 +294,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks system.cpu.dcache.writebacks::total 942334 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits @@ -344,7 +342,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. @@ -404,8 +401,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses @@ -432,7 +427,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. @@ -541,8 +535,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses @@ -591,7 +583,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index a8bc405b3..d612f6415 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 125889000 # Number of ticks simulated final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271253 # Simulator instruction rate (inst/s) -host_op_rate 271253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29155299 # Simulator tick rate (ticks/s) -host_mem_usage 267160 # Number of bytes of host memory used -host_seconds 4.32 # Real time elapsed on the host +host_inst_rate 196054 # Simulator instruction rate (inst/s) +host_op_rate 196054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21072637 # Simulator tick rate (ticks/s) +host_mem_usage 267156 # Number of bytes of host memory used +host_seconds 5.97 # Real time elapsed on the host sim_insts 1171234 # Number of instructions simulated sim_ops 1171234 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -666,8 +666,6 @@ system.cpu0.dcache.blocked::no_mshrs 22 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits @@ -718,7 +716,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 403 # number of replacements system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. @@ -777,8 +774,6 @@ system.cpu0.icache.blocked::no_mshrs 4 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 403 # number of writebacks system.cpu0.icache.writebacks::total 403 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits @@ -811,7 +806,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 75929 # Number of BP lookups system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect @@ -1193,8 +1187,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits @@ -1243,7 +1235,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 548 # number of replacements system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. @@ -1302,8 +1293,6 @@ system.cpu1.icache.blocked::no_mshrs 1 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 548 # number of writebacks system.cpu1.icache.writebacks::total 548 # number of writebacks system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits @@ -1336,7 +1325,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.branchPred.lookups 65577 # Number of BP lookups system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect @@ -1721,8 +1709,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits @@ -1773,7 +1759,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 555 # number of replacements system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. @@ -1832,8 +1817,6 @@ system.cpu2.icache.blocked::no_mshrs 7 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 555 # number of writebacks system.cpu2.icache.writebacks::total 555 # number of writebacks system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits @@ -1866,7 +1849,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.branchPred.lookups 57182 # Number of BP lookups system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect @@ -2248,8 +2230,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits @@ -2300,7 +2280,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 608 # number of replacements system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. @@ -2359,8 +2338,6 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 608 # number of writebacks system.cpu3.icache.writebacks::total 608 # number of writebacks system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits @@ -2393,7 +2370,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. @@ -2650,8 +2626,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 # number of ReadCleanReq MSHR hits @@ -2819,7 +2793,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 583 # Transaction distribution system.membus.trans_dist::UpgradeReq 286 # Transaction distribution system.membus.trans_dist::ReadExReq 182 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 1d3cbd064..f2280533e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1830828 # Simulator instruction rate (inst/s) -host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237054275 # Simulator tick rate (ticks/s) -host_mem_usage 306784 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host +host_inst_rate 1039500 # Simulator instruction rate (inst/s) +host_op_rate 1039462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134594380 # Simulator tick rate (ticks/s) +host_mem_usage 262812 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -180,11 +180,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. @@ -230,11 +227,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 215 # number of writebacks system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -353,9 +347,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 278 # number of replacements system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. @@ -401,11 +392,8 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 278 # number of writebacks system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -525,9 +513,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 278 # number of replacements system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. @@ -573,11 +558,8 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 278 # number of writebacks system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -696,9 +678,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 279 # number of replacements system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. @@ -744,11 +723,8 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 279 # number of writebacks system.cpu3.icache.writebacks::total 279 # number of writebacks -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. @@ -938,9 +914,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index eb0bc0573..22d94928b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000264 # Nu sim_ticks 263565500 # Number of ticks simulated final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 798172 # Simulator instruction rate (inst/s) -host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 317271660 # Simulator tick rate (ticks/s) -host_mem_usage 306776 # Number of bytes of host memory used -host_seconds 0.83 # Real time elapsed on the host +host_inst_rate 821706 # Simulator instruction rate (inst/s) +host_op_rate 821692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 326627282 # Simulator tick rate (ticks/s) +host_mem_usage 262816 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host sim_insts 663039 # Number of instructions simulated sim_ops 663039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,8 +200,6 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses @@ -244,7 +242,6 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. @@ -302,8 +299,6 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 215 # number of writebacks system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses @@ -330,7 +325,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 527130 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -470,8 +464,6 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses @@ -512,7 +504,6 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. @@ -571,8 +562,6 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 280 # number of writebacks system.cpu1.icache.writebacks::total 280 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses @@ -599,7 +588,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 527130 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -739,8 +727,6 @@ system.cpu2.dcache.blocked::no_mshrs 0 # nu system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses @@ -781,7 +767,6 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. @@ -840,8 +825,6 @@ system.cpu2.icache.blocked::no_mshrs 0 # nu system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 280 # number of writebacks system.cpu2.icache.writebacks::total 280 # number of writebacks system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses @@ -868,7 +851,6 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 527131 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1008,8 +990,6 @@ system.cpu3.dcache.blocked::no_mshrs 0 # nu system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses @@ -1050,7 +1030,6 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. @@ -1109,8 +1088,6 @@ system.cpu3.icache.blocked::no_mshrs 0 # nu system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks::writebacks 281 # number of writebacks system.cpu3.icache.writebacks::total 281 # number of writebacks system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses @@ -1137,7 +1114,6 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 347.185045 # Cycle average of tags in use system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. @@ -1393,8 +1369,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits @@ -1566,7 +1540,6 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 64e77dffe..30ddbd92e 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1816 +1,1739 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000535 # Number of seconds simulated -sim_ticks 535115500 # Number of ticks simulated -final_tick 535115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000502 # Number of seconds simulated +sim_ticks 501584000 # Number of ticks simulated +final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 114251239 # Simulator tick rate (ticks/s) -host_mem_usage 237088 # Number of bytes of host memory used -host_seconds 4.68 # Real time elapsed on the host +host_tick_rate 112049096 # Simulator tick rate (ticks/s) +host_mem_usage 235328 # Number of bytes of host memory used +host_seconds 4.48 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 81574 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80110 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79121 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81238 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 80899 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 79820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79202 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 79066 # Number of bytes read from this memory -system.physmem.bytes_read::total 641030 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 406208 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5473 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5509 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5540 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5388 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5404 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5375 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5435 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5475 # Number of bytes written to this memory -system.physmem.bytes_written::total 449807 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10829 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11026 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87827 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6347 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5473 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5509 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5540 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5388 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5375 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5435 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5475 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49946 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 152441856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 149705998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 147857799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 151813954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 151180446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 149164059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 148009168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 147755017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1197928298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 759103409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10227699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10294974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10352905 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10068854 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10098754 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10044560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10156686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10231436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 840579277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 759103409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 162669555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 160000972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 158210704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 161882808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 161279200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 159208619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 158165854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 157986453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2038507575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80557 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 77449 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 81573 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79541 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 76446 # Number of bytes read from this memory +system.physmem.bytes_read::total 633149 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 399616 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5525 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5482 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5537 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5409 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5437 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5416 # Number of bytes written to this memory +system.physmem.bytes_written::total 443294 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10960 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11104 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10887 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6244 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5376 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5525 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5482 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5409 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5437 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49922 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 153858576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 159381081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 160425771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 160605203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 154408833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 162630786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 158579620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 152409168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1262299037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 796708029 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10718045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11015104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10929376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11039028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10957287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10783837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10839660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10797793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 883788159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 796708029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 164576621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 170396185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 171355147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 171644231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165366120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 173414622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55271 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22387 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.751313 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13331 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.584873 # Average number of references to valid blocks. +system.cpu0.num_reads 99682 # number of read accesses completed +system.cpu0.num_writes 55240 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22392 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.595348 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.751313 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765139 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765139 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338274 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338274 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8660 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1174 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1174 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9834 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9834 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9834 # number of overall hits -system.cpu0.l1c.overall_hits::total 9834 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36517 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36517 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23979 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23979 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60496 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60496 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60496 # number of overall misses -system.cpu0.l1c.overall_misses::total 60496 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 647463503 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 647463503 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 554640697 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 554640697 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1202104200 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1202104200 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1202104200 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1202104200 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45177 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45177 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25153 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70330 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70330 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808310 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.808310 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953326 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953326 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860173 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860173 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860173 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860173 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 749854 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 393.390751 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768341 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768341 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1120 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9967 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9967 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9967 # number of overall hits +system.cpu0.l1c.overall_hits::total 9967 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36618 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36618 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60587 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60587 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60587 # number of overall misses +system.cpu0.l1c.overall_misses::total 60587 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 672506192 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 672506192 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 563028530 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 563028530 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1235534722 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1235534722 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1235534722 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1235534722 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45465 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45465 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25089 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25089 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70554 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70554 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70554 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70554 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805411 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805411 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955359 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955359 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858732 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858732 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858732 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858732 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18365.453930 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 18365.453930 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23489.863157 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 23489.863157 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20392.736429 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20392.736429 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20392.736429 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20392.736429 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 823442 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 59820 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66357 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.535172 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.409271 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.fast_writes 0 # number of fast writes performed -system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9840 # number of writebacks -system.cpu0.l1c.writebacks::total 9840 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36517 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36517 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23979 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23979 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60496 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60496 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60496 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60496 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9959 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9959 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15434 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15434 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 610946503 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 610946503 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 530662697 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 530662697 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1141609200 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1141609200 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1141609200 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1141609200 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 751203683 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 751203683 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 933372844 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 933372844 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1684576527 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1684576527 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808310 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808310 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953326 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953326 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860173 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860173 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025 # average overall mshr uncacheable latency -system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99085 # number of read accesses completed -system.cpu1.num_writes 54836 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22258 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.296117 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22654 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.590536 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 9844 # number of writebacks +system.cpu0.l1c.writebacks::total 9844 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36618 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36618 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60587 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60587 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60587 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60587 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9910 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5376 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15286 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 635888192 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 635888192 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 539061530 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 539061530 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1174949722 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1174949722 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1174949722 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1174949722 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 753971133 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 753971133 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 753971133 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 753971133 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805411 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805411 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955359 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955359 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858732 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858732 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17365.453930 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17365.453930 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22489.946598 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22489.946598 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency +system.cpu1.num_reads 99541 # number of read accesses completed +system.cpu1.num_writes 55028 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22314 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22722 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.597351 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.296117 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.764250 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.764250 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 336817 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 336817 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8647 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8647 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1131 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9778 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9778 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9778 # number of overall hits -system.cpu1.l1c.overall_hits::total 9778 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36589 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36589 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23685 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23685 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60274 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60274 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60274 # number of overall misses -system.cpu1.l1c.overall_misses::total 60274 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 652011208 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 652011208 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 548619495 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 548619495 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1200630703 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1200630703 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1200630703 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1200630703 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45236 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45236 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24816 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24816 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70052 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70052 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70052 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70052 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808847 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.808847 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954425 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954425 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860418 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860418 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860418 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860418 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 748495 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.210618 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.767989 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.767989 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9853 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9853 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9853 # number of overall hits +system.cpu1.l1c.overall_hits::total 9853 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36652 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36652 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23946 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23946 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60598 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60598 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60598 # number of overall misses +system.cpu1.l1c.overall_misses::total 60598 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 672762640 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 672762640 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 564762705 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 564762705 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1237525345 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1237525345 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1237525345 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1237525345 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45356 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25095 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25095 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70451 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70451 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70451 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70451 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808096 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808096 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954214 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954214 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860144 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860144 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860144 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860144 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18355.414166 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 18355.414166 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23584.845277 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 23584.845277 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20421.884303 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20421.884303 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20421.884303 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20421.884303 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 822356 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 59422 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.596261 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.429994 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.fast_writes 0 # number of fast writes performed -system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks -system.cpu1.l1c.writebacks::total 9809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36589 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36589 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23685 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23685 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60274 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60274 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60274 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60274 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9902 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5511 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5511 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15413 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15413 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 615423208 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 615423208 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 524934495 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 524934495 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1140357703 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1140357703 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1140357703 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1140357703 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 747152224 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 747152224 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 944376752 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 944376752 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1691528976 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1691528976 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808847 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808847 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954425 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954425 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860418 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860418 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409 # average overall mshr uncacheable latency -system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99705 # number of read accesses completed -system.cpu2.num_writes 55132 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22489 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.363987 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13472 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22889 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.588580 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9894 # number of writebacks +system.cpu1.l1c.writebacks::total 9894 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36652 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36652 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23946 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23946 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60598 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60598 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60598 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60598 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9864 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9864 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5527 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15391 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15391 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 636111640 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 636111640 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 540817705 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 540817705 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1176929345 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1176929345 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1176929345 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1176929345 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 750538193 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 750538193 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 750538193 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 750538193 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808096 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808096 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954214 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954214 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860144 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860144 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17355.441449 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17355.441449 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22584.887038 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22584.887038 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency +system.cpu2.num_reads 99993 # number of read accesses completed +system.cpu2.num_writes 55211 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22333 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.595509 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.363987 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.768289 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.768289 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339330 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339330 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8744 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8744 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1142 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9886 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9886 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9886 # number of overall hits -system.cpu2.l1c.overall_hits::total 9886 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36705 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36705 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23982 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23982 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60687 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60687 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60687 # number of overall misses -system.cpu2.l1c.overall_misses::total 60687 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 655863609 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 655863609 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 555301116 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 555301116 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1211164725 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1211164725 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1211164725 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1211164725 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70573 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70573 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70573 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70573 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807609 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.807609 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954545 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859918 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859918 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859918 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859918 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 744784 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.533782 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766668 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766668 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1131 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9831 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9831 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9831 # number of overall hits +system.cpu2.l1c.overall_hits::total 9831 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36743 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36743 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23917 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23917 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60660 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60660 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60660 # number of overall misses +system.cpu2.l1c.overall_misses::total 60660 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 667892138 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 667892138 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 561829218 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 561829218 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1229721356 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1229721356 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1229721356 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1229721356 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45443 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45443 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25048 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25048 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70491 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70491 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70491 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70491 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808551 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.808551 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954847 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954847 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860535 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860535 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860535 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860535 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18177.398089 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 18177.398089 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23490.789731 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 23490.789731 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20272.359974 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20272.359974 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20272.359974 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20272.359974 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 824101 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 59741 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66507 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.466882 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.391192 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.fast_writes 0 # number of fast writes performed -system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9941 # number of writebacks -system.cpu2.l1c.writebacks::total 9941 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36705 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36705 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23982 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23982 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60687 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60687 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60687 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60687 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9745 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5541 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5541 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15286 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 619160609 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 619160609 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 531319116 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 531319116 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1150479725 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1150479725 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1150479725 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1150479725 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 736103391 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 736103391 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 958643718 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 958643718 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1694747109 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1694747109 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807609 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807609 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954545 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859918 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859918 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874 # average overall mshr uncacheable latency -system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99493 # number of read accesses completed -system.cpu3.num_writes 55186 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22493 # number of replacements -system.cpu3.l1c.tags.tagsinuse 393.330553 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13483 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22894 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.588932 # Average number of references to valid blocks. +system.cpu2.l1c.writebacks::writebacks 9742 # number of writebacks +system.cpu2.l1c.writebacks::total 9742 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36743 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36743 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23917 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23917 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60660 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60660 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60660 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60660 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 10005 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5482 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15487 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 631149138 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 631149138 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537912218 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537912218 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1169061356 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1169061356 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1169061356 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1169061356 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 759988155 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 759988155 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 759988155 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 759988155 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808551 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808551 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954847 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954847 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860535 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860535 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17177.398089 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17177.398089 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22490.789731 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22490.789731 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency +system.cpu3.num_reads 99085 # number of read accesses completed +system.cpu3.num_writes 55606 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22528 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22909 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.588982 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 393.330553 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.768224 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.768224 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338296 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338296 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8738 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8738 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1110 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1110 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9848 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9848 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9848 # number of overall hits -system.cpu3.l1c.overall_hits::total 9848 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36582 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36582 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23939 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23939 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60521 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60521 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60521 # number of overall misses -system.cpu3.l1c.overall_misses::total 60521 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 654319900 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 654319900 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 552232159 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 552232159 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1206552059 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1206552059 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1206552059 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1206552059 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45320 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45320 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25049 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70369 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70369 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70369 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70369 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807193 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807193 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955687 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955687 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860052 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860052 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860052 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860052 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 748969 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.624901 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.764892 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.764892 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9904 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9904 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9904 # number of overall hits +system.cpu3.l1c.overall_hits::total 9904 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36439 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36439 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24225 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24225 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60664 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60664 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60664 # number of overall misses +system.cpu3.l1c.overall_misses::total 60664 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 671429109 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 671429109 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 572133441 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 572133441 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1243562550 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1243562550 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1243562550 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1243562550 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25359 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70568 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70568 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70568 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70568 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806012 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.806012 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955282 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955282 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859653 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859653 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859653 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859653 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18426.112380 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 18426.112380 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23617.479505 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 23617.479505 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20499.184854 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20499.184854 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20499.184854 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20499.184854 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 821290 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59958 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66174 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.491561 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.411068 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.fast_writes 0 # number of fast writes performed -system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9953 # number of writebacks -system.cpu3.l1c.writebacks::total 9953 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36582 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36582 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23939 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60521 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60521 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60521 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60521 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9878 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15266 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 617737900 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 617737900 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 528295159 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 528295159 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1146033059 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1146033059 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1146033059 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1146033059 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 746486832 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 746486832 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 927844496 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 927844496 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1674331328 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1674331328 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807193 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807193 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955687 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955687 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860052 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860052 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124 # average overall mshr uncacheable latency -system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99921 # number of read accesses completed -system.cpu4.num_writes 55196 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22380 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.777413 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13581 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22786 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596024 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 10017 # number of writebacks +system.cpu3.l1c.writebacks::total 10017 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36439 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36439 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24225 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24225 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60664 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60664 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60664 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60664 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5538 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5538 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15311 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 634992109 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 634992109 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 547908441 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 547908441 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1182900550 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1182900550 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1182900550 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1182900550 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 743773245 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 743773245 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 743773245 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 743773245 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806012 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806012 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955282 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955282 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859653 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859653 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17426.167266 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17426.167266 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22617.479505 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22617.479505 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency +system.cpu4.num_reads 99978 # number of read accesses completed +system.cpu4.num_writes 55474 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22223 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22628 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.612427 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.777413 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767143 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767143 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339211 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339211 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8862 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8862 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1132 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1132 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9994 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9994 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9994 # number of overall hits -system.cpu4.l1c.overall_hits::total 9994 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36800 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36800 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23778 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23778 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60578 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60578 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60578 # number of overall misses -system.cpu4.l1c.overall_misses::total 60578 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 655197570 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 655197570 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 548908934 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 548908934 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1204106504 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1204106504 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1204106504 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1204106504 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45662 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45662 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24910 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24910 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70572 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70572 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70572 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70572 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805922 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805922 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954556 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858386 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858386 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858386 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858386 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 750268 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.899958 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.765430 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.765430 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 396 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1171 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10061 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10061 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10061 # number of overall hits +system.cpu4.l1c.overall_hits::total 10061 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36725 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36725 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24186 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24186 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60911 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60911 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60911 # number of overall misses +system.cpu4.l1c.overall_misses::total 60911 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 668441602 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 668441602 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 573535032 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 573535032 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1241976634 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1241976634 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1241976634 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1241976634 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45615 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45615 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25357 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25357 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70972 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70972 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70972 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70972 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805108 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805108 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953819 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953819 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858240 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858240 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858240 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858240 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18201.268945 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 18201.268945 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23713.513272 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 23713.513272 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20390.022065 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20390.022065 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20390.022065 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20390.022065 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 823668 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 59848 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66629 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.536225 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.362005 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.fast_writes 0 # number of fast writes performed -system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9770 # number of writebacks -system.cpu4.l1c.writebacks::total 9770 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36800 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36800 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23778 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23778 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60578 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60578 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60578 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60578 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9925 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5406 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5406 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15331 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15331 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 618398570 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 618398570 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 525131934 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 525131934 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1143530504 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1143530504 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1143530504 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1143530504 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 750294225 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 750294225 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 944567825 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 944567825 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1694862050 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1694862050 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805922 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805922 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954556 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858386 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858386 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546 # average overall mshr uncacheable latency -system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99482 # number of read accesses completed -system.cpu5.num_writes 55607 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22456 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.242325 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13457 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22866 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.588516 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9699 # number of writebacks +system.cpu4.l1c.writebacks::total 9699 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36725 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36725 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24186 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24186 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60911 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60911 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60911 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60911 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9801 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5498 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 631717602 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 631717602 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 549351032 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 549351032 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1181068634 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1181068634 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1181068634 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1181068634 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748050214 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748050214 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 748050214 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 748050214 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805108 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805108 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953819 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953819 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858240 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858240 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17201.296174 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17201.296174 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22713.595965 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22713.595965 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 55110 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22358 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22751 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.599095 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.242325 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.766098 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.766098 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338143 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338143 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8578 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8578 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1205 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1205 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits -system.cpu5.l1c.overall_hits::total 9783 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36239 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36239 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24308 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24308 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60547 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60547 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60547 # number of overall misses -system.cpu5.l1c.overall_misses::total 60547 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 647043171 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 647043171 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 559180438 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 559180438 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1206223609 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1206223609 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1206223609 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1206223609 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44817 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44817 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25513 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25513 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70330 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70330 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808599 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808599 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952769 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952769 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860899 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860899 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860899 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860899 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 749399 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.816568 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765267 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1107 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9928 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9928 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9928 # number of overall hits +system.cpu5.l1c.overall_hits::total 9928 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36801 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36801 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24029 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24029 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60830 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60830 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60830 # number of overall misses +system.cpu5.l1c.overall_misses::total 60830 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 677475643 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 677475643 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 566244558 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 566244558 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1243720201 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1243720201 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1243720201 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1243720201 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45622 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45622 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25136 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70758 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70758 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70758 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70758 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806650 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806650 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955960 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.955960 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859691 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859691 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859691 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859691 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18409.163963 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 18409.163963 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23565.048816 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 23565.048816 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20445.835953 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20445.835953 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20445.835953 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20445.835953 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 821580 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 59952 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66406 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.499983 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.372075 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.fast_writes 0 # number of fast writes performed -system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 10051 # number of writebacks -system.cpu5.l1c.writebacks::total 10051 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36239 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36239 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24308 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24308 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60547 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60547 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60547 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60547 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5375 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15244 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 610804171 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 610804171 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 534872438 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 534872438 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1145676609 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1145676609 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1145676609 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1145676609 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 745114179 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 745114179 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 938602875 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 938602875 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1683717054 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1683717054 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808599 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808599 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952769 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952769 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860899 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860899 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855 # average overall mshr uncacheable latency -system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99231 # number of read accesses completed -system.cpu6.num_writes 55266 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22476 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.210816 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13488 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22863 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.589949 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 10004 # number of writebacks +system.cpu5.l1c.writebacks::total 10004 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36801 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36801 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24029 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24029 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60830 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60830 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60830 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60830 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9765 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5412 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5412 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15177 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15177 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 640675643 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 640675643 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 542215558 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 542215558 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1182891201 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1182891201 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1182891201 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1182891201 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 744215663 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 744215663 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 744215663 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 744215663 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806650 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806650 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955960 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955960 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859691 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859691 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17409.191136 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17409.191136 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22565.048816 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22565.048816 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency +system.cpu6.num_reads 99774 # number of read accesses completed +system.cpu6.num_writes 55185 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22542 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22929 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.585241 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.210816 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.767990 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.767990 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_blocks::cpu6 391.726459 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765091 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765091 # Average percentage of cache occupancy system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339081 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339081 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9910 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9910 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9910 # number of overall hits -system.cpu6.l1c.overall_hits::total 9910 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36605 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36605 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24011 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24011 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60616 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60616 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60616 # number of overall misses -system.cpu6.l1c.overall_misses::total 60616 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 653690176 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 653690176 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 554778070 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 554778070 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1208468246 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1208468246 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1208468246 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1208468246 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45308 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45308 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25218 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25218 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70526 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70526 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70526 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70526 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807915 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952137 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.952137 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859484 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859484 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859484 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859484 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 748048 # number of cycles access was blocked +system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1147 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits +system.cpu6.l1c.overall_hits::total 9857 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36696 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36696 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24079 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24079 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60775 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60775 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60775 # number of overall misses +system.cpu6.l1c.overall_misses::total 60775 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 672502171 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 672502171 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 571063447 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 571063447 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1243565618 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1243565618 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1243565618 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1243565618 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45406 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45406 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25226 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25226 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70632 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70632 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70632 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70632 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808175 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808175 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954531 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954531 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860446 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860446 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860446 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860446 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18326.307254 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 18326.307254 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23716.244321 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 23716.244321 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20461.795442 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20461.795442 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20461.795442 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20461.795442 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 822508 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 59929 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66430 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.482237 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.381575 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.fast_writes 0 # number of fast writes performed -system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9811 # number of writebacks -system.cpu6.l1c.writebacks::total 9811 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36605 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24011 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24011 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60616 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60616 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60616 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60616 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5436 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5436 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15264 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15264 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 617085176 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 617085176 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 530767070 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 530767070 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1147852246 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1147852246 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1147852246 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1147852246 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 743889866 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 743889866 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 938428736 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 938428736 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1682318602 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1682318602 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952137 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952137 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859484 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859484 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108 # average overall mshr uncacheable latency -system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99956 # number of read accesses completed -system.cpu7.num_writes 55531 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22312 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.161929 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13691 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22714 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.602756 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9969 # number of writebacks +system.cpu6.l1c.writebacks::total 9969 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36696 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36696 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24079 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24079 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60775 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60775 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60775 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60775 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9782 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15220 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 635806171 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 635806171 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 546984447 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 546984447 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1182790618 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1182790618 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1182790618 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1182790618 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 745377162 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 745377162 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 745377162 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 745377162 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808175 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808175 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954531 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954531 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860446 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860446 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17326.307254 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17326.307254 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22716.244321 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22716.244321 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency +system.cpu7.num_reads 99703 # number of read accesses completed +system.cpu7.num_writes 55656 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22447 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22845 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.592777 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.161929 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.767894 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.767894 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338939 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338939 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8916 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8916 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 10081 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 10081 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 10081 # number of overall hits -system.cpu7.l1c.overall_hits::total 10081 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36493 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36493 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23963 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23963 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60456 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60456 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60456 # number of overall misses -system.cpu7.l1c.overall_misses::total 60456 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 649044669 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 649044669 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 555516702 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 555516702 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1204561371 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1204561371 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1204561371 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1204561371 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45409 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25128 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70537 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70537 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70537 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70537 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803651 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.803651 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953637 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953637 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857082 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857082 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857082 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857082 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 753584 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 392.675740 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766945 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766945 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1173 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9855 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9855 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9855 # number of overall hits +system.cpu7.l1c.overall_hits::total 9855 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36511 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36511 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24145 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24145 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60656 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60656 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60656 # number of overall misses +system.cpu7.l1c.overall_misses::total 60656 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 668215285 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 668215285 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 564137498 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 564137498 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1232352783 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1232352783 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1232352783 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1232352783 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45193 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45193 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25318 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25318 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70511 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70511 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70511 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70511 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807891 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807891 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953669 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953669 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860235 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860235 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860235 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860235 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18301.752486 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 18301.752486 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23364.568151 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 23364.568151 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20317.079646 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20317.079646 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20317.079646 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20317.079646 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 824059 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 60106 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66592 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.537584 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.374745 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.fast_writes 0 # number of fast writes performed -system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9825 # number of writebacks -system.cpu7.l1c.writebacks::total 9825 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36493 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36493 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23963 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23963 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60456 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60456 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60456 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60456 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5477 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5477 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15423 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15423 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 612553669 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 612553669 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 531553702 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 531553702 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1144107371 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1144107371 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1144107371 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1144107371 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 750008205 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 750008205 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 931574803 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 931574803 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1681583008 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1681583008 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953637 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953637 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857082 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857082 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516 # average overall mshr uncacheable latency -system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13679 # number of replacements -system.l2c.tags.tagsinuse 785.030982 # Cycle average of tags in use -system.l2c.tags.total_refs 164295 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14481 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.345556 # Average number of references to valid blocks. +system.cpu7.l1c.writebacks::writebacks 9889 # number of writebacks +system.cpu7.l1c.writebacks::total 9889 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36511 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36511 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24145 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24145 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60656 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60656 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60656 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60656 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9951 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5417 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15368 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15368 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 631704285 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 631704285 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 539994498 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 539994498 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1171698783 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1171698783 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1171698783 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1171698783 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 757938041 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 757938041 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 757938041 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 757938041 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807891 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807891 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953669 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953669 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860235 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860235 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17301.752486 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17301.752486 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22364.650984 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22364.650984 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency +system.l2c.tags.replacements 13600 # number of replacements +system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use +system.l2c.tags.total_refs 164496 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14391 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.430477 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 728.912576 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.109869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.264593 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.067016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.280147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.468572 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.873708 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.969066 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.085434 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.711829 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006943 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007094 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006713 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006919 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.766632 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 802 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2100989 # Number of tag accesses -system.l2c.tags.data_accesses 2100989 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 77660 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77660 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 265 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 275 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 255 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 292 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 297 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 302 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2259 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1784 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1764 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1831 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1735 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1864 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14282 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10784 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10837 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10882 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10814 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10969 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10782 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10825 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10836 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86729 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12646 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12592 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12616 # number of demand (read+write) hits -system.l2c.demand_hits::total 101011 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12568 # number of overall hits -system.l2c.overall_hits::cpu1 12601 # number of overall hits -system.l2c.overall_hits::cpu2 12713 # number of overall hits -system.l2c.overall_hits::cpu3 12549 # number of overall hits -system.l2c.overall_hits::cpu4 12726 # number of overall hits -system.l2c.overall_hits::cpu5 12646 # number of overall hits -system.l2c.overall_hits::cpu6 12592 # number of overall hits -system.l2c.overall_hits::cpu7 12616 # number of overall hits -system.l2c.overall_hits::total 101011 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2063 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2062 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2025 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1973 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16225 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4717 # number of ReadExReq misses +system.l2c.tags.occ_blocks::writebacks 730.947637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.698781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.684981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.056959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.865777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.833706 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.577663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.826515 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.502881 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713816 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006528 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006892 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006705 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006674 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007400 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006350 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.767573 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 651 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2102241 # Number of tag accesses +system.l2c.tags.data_accesses 2102241 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 294 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 264 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 279 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 268 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2299 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1816 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1719 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1709 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1788 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1754 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1794 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1762 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14182 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10810 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10840 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 11008 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10829 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10875 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10910 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86815 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12626 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12669 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12470 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12621 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12672 # number of demand (read+write) hits +system.l2c.demand_hits::total 100997 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12626 # number of overall hits +system.l2c.overall_hits::cpu1 12559 # number of overall hits +system.l2c.overall_hits::cpu2 12717 # number of overall hits +system.l2c.overall_hits::cpu3 12669 # number of overall hits +system.l2c.overall_hits::cpu4 12663 # number of overall hits +system.l2c.overall_hits::cpu5 12470 # number of overall hits +system.l2c.overall_hits::cpu6 12621 # number of overall hits +system.l2c.overall_hits::cpu7 12672 # number of overall hits +system.l2c.overall_hits::total 100997 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2133 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2089 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2051 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2132 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2082 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2039 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16603 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4589 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4643 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4618 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4604 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4664 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4698 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 701 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 741 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 707 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 750 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 700 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 714 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 696 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 703 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5712 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5418 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5350 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5368 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5395 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5360 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5401 # number of demand (read+write) misses -system.l2c.demand_misses::total 42910 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5418 # number of overall misses -system.l2c.overall_misses::cpu1 5314 # number of overall misses -system.l2c.overall_misses::cpu2 5350 # number of overall misses -system.l2c.overall_misses::cpu3 5368 # number of overall misses -system.l2c.overall_misses::cpu4 5304 # number of overall misses -system.l2c.overall_misses::cpu5 5395 # number of overall misses -system.l2c.overall_misses::cpu6 5360 # number of overall misses -system.l2c.overall_misses::cpu7 5401 # number of overall misses -system.l2c.overall_misses::total 42910 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 33570299 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 36327486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 35657979 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 35008978 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 34589470 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 34691475 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 32410475 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 35465977 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 277722139 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 161829189 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 155335873 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 157770030 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 156623200 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 158516385 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 158789879 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 159063367 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 159738542 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1267666465 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 49231417 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 51778912 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 49960071 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 52497915 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 48409406 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 49972406 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 48755897 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 49161911 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 399767935 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 211060606 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 207114785 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 207730101 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 209121115 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 206925791 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 208762285 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 207819264 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 208900453 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1667434400 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 211060606 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 207114785 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 207730101 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 209121115 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 206925791 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 208762285 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 207819264 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 208900453 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1667434400 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77660 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77660 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2200 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2338 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2352 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18484 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6501 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6337 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6474 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6361 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6545 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6431 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6478 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51480 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11485 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11578 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11589 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11564 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11669 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11496 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11521 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11539 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92441 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17986 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17915 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17917 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18030 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143921 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17986 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17915 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17917 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18030 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18041 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143921 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.879545 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.882378 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.889944 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.876648 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.877383 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.875639 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.869163 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.871599 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.877786 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.725581 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.721635 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.717176 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.726901 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.723786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.715202 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.725237 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.725224 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.722572 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.061036 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.064001 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.061006 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.064856 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.059988 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.062109 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.060411 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.060924 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.061791 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.301234 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.296623 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.296186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.299604 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294176 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.299041 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.298574 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.299772 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.298150 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.301234 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.296623 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.296186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.299604 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294176 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.299041 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.298574 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.299772 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.298150 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 17348.991731 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 17609.057683 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 17292.909311 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16986.403688 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 17081.219753 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 16873.285506 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16427.002027 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 17300.476585 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17116.926903 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 34307.650837 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 33968.045703 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 33980.191686 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 33915.807709 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 34430.144440 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 33922.212989 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 34104.495497 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 34078.887709 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 69987.383578 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 38955.445921 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 38975.307678 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 38828.056262 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 38956.988636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 39013.158183 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 38695.511585 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 38772.250746 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 38678.106462 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 38858.876719 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 38955.445921 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 38975.307678 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 38828.056262 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 38956.988636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 39013.158183 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 38695.511585 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 38772.250746 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 38678.106462 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 38858.876719 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 15775 # number of cycles access was blocked +system.l2c.ReadExReq_misses::cpu2 4653 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4696 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4757 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4526 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4651 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4580 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37025 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 704 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 708 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 726 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 758 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 689 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 675 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5641 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5293 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5422 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5428 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5284 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5340 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5255 # number of demand (read+write) misses +system.l2c.demand_misses::total 42666 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5293 # number of overall misses +system.l2c.overall_misses::cpu1 5281 # number of overall misses +system.l2c.overall_misses::cpu2 5363 # number of overall misses +system.l2c.overall_misses::cpu3 5422 # number of overall misses +system.l2c.overall_misses::cpu4 5428 # number of overall misses +system.l2c.overall_misses::cpu5 5284 # number of overall misses +system.l2c.overall_misses::cpu6 5340 # number of overall misses +system.l2c.overall_misses::cpu7 5255 # number of overall misses +system.l2c.overall_misses::total 42666 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 33033499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 37073999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 35504000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 34167500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 35922999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 36683500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 35141499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 35012999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 282539995 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 156097931 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 156545440 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 159419095 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 159741454 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 162402934 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 154349443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 159730395 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 156156442 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1264443134 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 50090895 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 50336063 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 50437231 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 51704240 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 47729417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 53673691 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 48908906 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 47302737 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 400183180 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 206188826 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 206881503 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 209856326 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 211445694 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 210132351 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 208023134 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 208639301 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 203459179 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1664626314 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 206188826 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 206881503 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 209856326 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 211445694 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 210132351 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 208023134 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 208639301 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 203459179 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1664626314 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77703 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77703 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2423 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2383 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2315 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2411 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2379 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2350 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2364 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18902 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6405 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6292 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6362 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6536 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6545 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6445 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51207 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11514 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11548 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11718 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11555 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11546 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11474 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11516 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11585 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92456 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17919 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17840 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18080 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17754 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17961 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17927 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143663 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17919 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17840 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18080 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17754 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17961 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17927 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143663 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.872639 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.880314 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.876626 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.885961 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.884280 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.878520 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.885957 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.862521 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878373 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.716472 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.726796 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.731374 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.718482 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.726814 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.720701 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.721645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.722170 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.723046 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.061143 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.061309 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.060591 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.062830 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.058115 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.066062 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.059830 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.058265 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.061013 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.295385 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.296020 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296626 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.299707 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.300039 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.297311 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.293133 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.296987 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.295385 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.296020 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296626 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.299707 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.300039 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.297311 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.293133 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.296987 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16624.810770 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17381.152836 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16995.691719 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 16658.946855 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16849.436679 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 17551.913876 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16878.721902 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 17171.652281 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 17017.406192 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 34015.674657 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 34232.547562 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 34261.572104 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 34016.493612 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 34139.780114 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 34102.837605 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 34343.236938 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 34095.293013 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 34151.063714 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 71151.839489 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 71096.134181 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 71038.353521 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 71217.961433 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 71131.769001 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70809.618734 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70985.349782 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70078.128889 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 70941.886190 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 38955.002078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 39174.683393 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 39130.398285 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 38997.730358 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 38712.665991 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 39368.496215 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 39071.030150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 38717.255756 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 39015.288848 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 38955.002078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 39174.683393 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 39130.398285 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 38997.730358 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 38712.665991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 39368.496215 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 39071.030150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 38717.255756 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 39015.288848 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 20827 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2328 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3189 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.776203 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.530887 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6347 # number of writebacks -system.l2c.writebacks::total 6347 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 71 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 116 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1217 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1217 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1934 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2063 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2062 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2060 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2025 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2055 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1973 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16222 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4714 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4566 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4635 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4673 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4662 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4689 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37153 # number of ReadExReq MSHR misses +system.l2c.writebacks::writebacks 6244 # number of writebacks +system.l2c.writebacks::total 6244 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 15 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 77 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 112 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 112 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1208 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1208 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1987 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2132 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2088 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2051 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2132 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2088 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2082 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2039 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16599 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4587 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4571 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4648 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4690 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4753 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4524 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4643 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4574 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 36990 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0 694 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 728 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 740 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 687 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 706 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 687 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 699 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5641 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5408 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5294 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5335 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5355 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5286 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5379 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5349 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5388 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42794 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5408 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5294 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5335 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5355 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5286 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5379 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5349 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5388 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42794 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9958 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 79051 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5509 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5540 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5404 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5435 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5475 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43601 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15433 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15411 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15285 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15329 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15263 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15421 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122652 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 40213943 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 42852043 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 42722752 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42718914 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 41954263 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 42662066 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 40886253 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 42452590 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 336462824 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 114483428 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 109319242 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 111132111 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 110326921 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 112301120 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 111711839 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 112344259 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 112421561 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 894040481 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41942368 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 43799223 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42582401 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44577742 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40998173 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 42436532 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41443209 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 41880731 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 339660379 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 156425796 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 153118465 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 153714512 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 154904663 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 153299293 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 154148371 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 153787468 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 154302292 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1233700860 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 156425796 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 153118465 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 153714512 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 154904663 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 153299293 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 154148371 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 153787468 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 154302292 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1233700860 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 532537334 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 530034961 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 522091524 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 528677272 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 531067932 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 528334987 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 526505398 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 532738235 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 4231987643 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302507401 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 304491446 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 306673088 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 296941482 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 299721877 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 297975047 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 302462757 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 303375300 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2414148398 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 835044735 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 834526407 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 828764612 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 825618754 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 830789809 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 826310034 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 828968155 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 836113535 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6646136041 # number of overall MSHR uncacheable cycles +system.l2c.ReadSharedReq_mshr_misses::cpu1 699 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 695 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 722 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu4 667 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 748 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 679 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 660 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5564 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5270 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5412 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5420 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5272 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5322 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5234 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42554 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5270 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5343 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5412 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5420 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5272 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5322 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5234 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42554 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9909 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9863 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78849 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5525 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5537 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5496 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5409 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5416 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43679 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15285 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15388 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15310 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15297 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15174 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15367 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122528 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 41114731 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 44135575 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43262560 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42495420 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44129731 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43370592 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43201403 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 42227606 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 343937618 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 110096109 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 110716645 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 112771891 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 112546795 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 114695609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 108961847 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 112947605 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 110110769 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 892847270 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 42686190 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42892571 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42733862 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44195932 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40778543 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 45766520 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41640903 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 39953551 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 340648072 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 152782299 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 153609216 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 155505753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 156742727 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 155474152 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 154728367 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 154588508 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 150064320 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1233495342 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 152782299 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 153609216 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 155505753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 156742727 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 155474152 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 154728367 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 154588508 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 150064320 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1233495342 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 531934603 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 529144419 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 536612256 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 524755063 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 526637223 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 524048250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 524701912 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 534783521 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4232617247 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 531934603 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 529144419 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 536612256 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 524755063 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 526637223 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 524048250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 524701912 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 534783521 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4232617247 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.879091 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.882378 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889944 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.876223 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877383 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875213 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.869163 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871599 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.877624 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725119 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.720530 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.715941 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.726428 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.723000 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.713980 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.724926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.723835 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.721698 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060427 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062878 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060402 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063992 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.058874 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.061413 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.059630 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060577 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061023 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297344 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297344 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 125196 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 119242 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.872639 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.879901 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.876206 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885961 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884280 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877680 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.885957 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.862521 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878161 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716159 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726478 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730588 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.717564 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.726203 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720382 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720403 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721224 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.722362 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060274 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060530 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.059310 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057769 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065191 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058961 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.056970 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060180 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.296207 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.296207 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20691.862607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20701.489212 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.616858 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20719.366163 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20698.748124 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20771.356322 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20749.953410 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20709.958803 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20720.381830 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24001.767822 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 24221.536863 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 24262.455034 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23997.184435 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24131.203240 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 24085.288904 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24326.427956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 24073.189550 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 24137.530954 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61507.478386 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 61362.762518 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 61487.571223 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 61213.202216 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 61137.245877 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 61185.187166 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 61326.808542 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60535.683333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 61223.593098 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53681.966192 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53649.439217 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53634.408396 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53694.368464 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53733.009183 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53665.975422 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53639.533020 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53741.686363 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53680.037122 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 34801.086228 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 34386.822134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 34649.206173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 34275.314370 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 34427.484016 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 34535.933175 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 34474.501445 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 34800.775753 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 34544.081736 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 125015 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 119335 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 79046 # Transaction distribution -system.membus.trans_dist::ReadResp 84668 # Transaction distribution -system.membus.trans_dist::WriteReq 43599 # Transaction distribution -system.membus.trans_dist::WriteResp 43596 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6347 # Transaction distribution -system.membus.trans_dist::CleanEvict 1243 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60999 # Transaction distribution -system.membus.trans_dist::ReadExReq 49250 # Transaction distribution -system.membus.trans_dist::ReadExResp 3150 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5631 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377529 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 377529 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1090828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1090828 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56847 # Total snoops (count) -system.membus.snoop_fanout::samples 245688 # Request fanout histogram +system.membus.trans_dist::ReadReq 78845 # Transaction distribution +system.membus.trans_dist::ReadResp 84388 # Transaction distribution +system.membus.trans_dist::WriteReq 43678 # Transaction distribution +system.membus.trans_dist::WriteResp 43672 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6244 # Transaction distribution +system.membus.trans_dist::CleanEvict 1238 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61417 # Transaction distribution +system.membus.trans_dist::ReadExReq 49074 # Transaction distribution +system.membus.trans_dist::ReadExResp 3109 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377217 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 377217 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1076434 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1076434 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56879 # Total snoops (count) +system.membus.snoop_fanout::samples 245548 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 245548 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245688 # Request fanout histogram -system.membus.reqLayer0.occupancy 290283631 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.2 # Layer utilization (%) -system.membus.respLayer0.occupancy 245575000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 45.9 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 665524 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283935 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335837 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12315 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 79051 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371557 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43601 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43596 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 84007 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105887 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29230 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162413 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162411 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292528 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133251 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133559 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133586 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1068067 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1785416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1780080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1798067 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1787232 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784031 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1781660 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1785403 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14303561 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335445 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 626448 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148675 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.987271 # Request fanout histogram +system.membus.snoop_fanout::total 245548 # Request fanout histogram +system.membus.reqLayer0.occupancy 288762573 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 57.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 244649000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 48.8 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663848 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283900 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 334405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43671 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83947 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105636 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29816 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29815 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162678 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162674 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 293185 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133340 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 134024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1069251 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781172 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1779932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1786043 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1783744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1792304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1782917 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14289488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 336712 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 624467 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.150434 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.985907 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 174709 27.89% 27.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 258191 41.22% 69.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133874 21.37% 90.47% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 46929 7.49% 97.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 11007 1.76% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1601 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 133 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 172892 27.69% 27.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 258676 41.42% 69.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133601 21.39% 90.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 46619 7.47% 97.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 10890 1.74% 99.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1624 0.26% 99.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 162 0.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 626448 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 498178453 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102533331 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102040683 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102532818 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102294677 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102527849 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102329742 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102510939 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 102349372 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 624467 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 494463871 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102665881 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102599371 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102945420 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102767709 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102912196 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102768177 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102966672 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 102752542 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 36475e393..35b91ee55 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1811 +1,1733 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000530 # Number of seconds simulated -sim_ticks 530176500 # Number of ticks simulated -final_tick 530176500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000500 # Number of seconds simulated +sim_ticks 500337000 # Number of ticks simulated +final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 118834220 # Simulator tick rate (ticks/s) -host_mem_usage 236308 # Number of bytes of host memory used -host_seconds 4.46 # Real time elapsed on the host +host_tick_rate 94931123 # Simulator tick rate (ticks/s) +host_mem_usage 234040 # Number of bytes of host memory used +host_seconds 5.27 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 78184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80178 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79911 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82157 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 80611 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 81441 # Number of bytes read from this memory -system.physmem.bytes_read::total 641954 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 404160 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5485 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5418 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5526 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5422 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5386 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5538 # Number of bytes written to this memory -system.physmem.bytes_written::total 447793 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10815 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11071 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10904 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10881 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87113 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5485 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5400 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5526 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5422 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5386 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5538 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 147467872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 151228883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 150725277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 151474085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 154961602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 152045592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 149316313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 153611109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1210830733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 762312173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10345611 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10185287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10219238 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10422944 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10226783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10294685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10158881 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10445578 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 844611181 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 762312173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 157813483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 161414171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 160944516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 161897029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165188385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 162340277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 159475194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 164056687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2055441914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 79993 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 82197 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 76405 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83460 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78091 # Number of bytes read from this memory +system.physmem.bytes_read::total 637685 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 400320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5398 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5467 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5579 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5520 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5589 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5357 # Number of bytes written to this memory +system.physmem.bytes_written::total 444107 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11007 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10948 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6255 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5398 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5467 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5579 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5520 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5589 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5357 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50042 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 151735730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 161976828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 161045455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 159878242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 164283273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 152707075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 166807572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 156076804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1274510980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 800100732 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10788728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10926635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10844691 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11150485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11032564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10894657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11170471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10706784 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 887615747 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 800100732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 162524459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 172903463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 171890146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 171028727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 175315837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 163601732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99175 # number of read accesses completed -system.cpu0.num_writes 54789 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22440 # number of replacements -system.cpu0.l1c.tags.tagsinuse 392.189512 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13440 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.588648 # Average number of references to valid blocks. +system.cpu0.num_reads 99905 # number of read accesses completed +system.cpu0.num_writes 55400 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22463 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.606990 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 392.189512 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765995 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765995 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338141 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338141 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8693 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8693 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1204 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1204 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits -system.cpu0.l1c.overall_hits::total 9897 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36509 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36509 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23927 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23927 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60436 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60436 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60436 # number of overall misses -system.cpu0.l1c.overall_misses::total 60436 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 645236912 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 645236912 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 543361201 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 543361201 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1188598113 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1188598113 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1188598113 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1188598113 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45202 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45202 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25131 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25131 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70333 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70333 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70333 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70333 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807686 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807686 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952091 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952091 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859284 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859284 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859284 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859284 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 716464 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.153981 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763973 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763973 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1261 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 10155 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 10155 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 10155 # number of overall hits +system.cpu0.l1c.overall_hits::total 10155 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36720 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36720 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24041 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24041 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60761 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60761 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60761 # number of overall misses +system.cpu0.l1c.overall_misses::total 60761 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 677337671 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 677337671 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 564207136 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 564207136 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1241544807 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1241544807 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1241544807 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1241544807 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45614 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45614 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25302 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25302 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70916 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70916 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70916 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70916 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805016 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805016 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.950162 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.950162 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.856802 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.856802 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.856802 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.856802 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18446.015005 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 18446.015005 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23468.538580 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 23468.538580 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20433.251708 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20433.251708 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20433.251708 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20433.251708 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 800862 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 58624 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 65942 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.221343 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.144946 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.fast_writes 0 # number of fast writes performed -system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9950 # number of writebacks -system.cpu0.l1c.writebacks::total 9950 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36509 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36509 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23927 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60436 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60436 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60436 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60436 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9705 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9705 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5489 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5489 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15194 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15194 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 608727912 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 608727912 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 519435201 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 519435201 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1128163113 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1128163113 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1128163113 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1128163113 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 718425919 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 718425919 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 939004763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 939004763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1657430682 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1657430682 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807686 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807686 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952091 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952091 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859284 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859284 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928 # average overall mshr uncacheable latency -system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99705 # number of read accesses completed -system.cpu1.num_writes 54823 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22335 # number of replacements -system.cpu1.l1c.tags.tagsinuse 390.697643 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13624 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22725 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.599516 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 10055 # number of writebacks +system.cpu0.l1c.writebacks::total 10055 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36720 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36720 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24041 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24041 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60761 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60761 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60761 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60761 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5400 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15143 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15143 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 640619671 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 640619671 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 540167136 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 540167136 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1180786807 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1180786807 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1180786807 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1180786807 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 730760811 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 730760811 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 730760811 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 730760811 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805016 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805016 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.950162 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.950162 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.856802 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.856802 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17446.069472 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17446.069472 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22468.580176 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22468.580176 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency +system.cpu1.num_reads 99552 # number of read accesses completed +system.cpu1.num_writes 55243 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22440 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22851 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.596954 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 390.697643 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.763081 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.763081 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339221 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339221 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8840 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8840 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1148 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9988 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9988 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9988 # number of overall hits -system.cpu1.l1c.overall_hits::total 9988 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36605 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36605 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23987 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23987 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60592 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60592 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60592 # number of overall misses -system.cpu1.l1c.overall_misses::total 60592 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 646842299 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 646842299 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 543658224 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 543658224 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1190500523 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1190500523 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1190500523 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1190500523 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45445 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45445 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25135 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25135 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70580 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70580 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70580 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70580 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805479 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805479 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954327 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954327 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858487 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858487 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858487 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858487 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 718948 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.475962 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.766555 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.766555 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1136 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 10042 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 10042 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 10042 # number of overall hits +system.cpu1.l1c.overall_hits::total 10042 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36595 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36595 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24033 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24033 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60628 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60628 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60628 # number of overall misses +system.cpu1.l1c.overall_misses::total 60628 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 675076804 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 675076804 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 561344066 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 561344066 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1236420870 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1236420870 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1236420870 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1236420870 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45501 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45501 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25169 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70670 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70670 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70670 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70670 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804268 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.804268 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954865 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954865 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857903 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857903 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857903 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857903 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18447.241536 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 18447.241536 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23357.219906 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 23357.219906 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20393.561886 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20393.561886 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20393.561886 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20393.561886 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 800224 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 59028 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 65844 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.179779 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.153332 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.fast_writes 0 # number of fast writes performed -system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9932 # number of writebacks -system.cpu1.l1c.writebacks::total 9932 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36605 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23987 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23987 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60592 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60592 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60592 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60592 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9715 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9715 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5400 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15115 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15115 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 610238299 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 610238299 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 519672224 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 519672224 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1129910523 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1129910523 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1129910523 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1129910523 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 721621903 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 721621903 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954237303 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954237303 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1675859206 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1675859206 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805479 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805479 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954327 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954327 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858487 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858487 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728 # average overall mshr uncacheable latency -system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99117 # number of read accesses completed -system.cpu2.num_writes 54908 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22381 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.253516 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13534 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22797 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.593675 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9864 # number of writebacks +system.cpu1.l1c.writebacks::total 9864 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36595 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36595 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24033 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24033 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60628 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60628 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60628 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60628 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9811 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5468 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5468 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15279 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15279 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 638481804 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 638481804 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 537312066 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 537312066 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1175793870 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1175793870 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1175793870 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1175793870 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 734637731 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 734637731 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 734637731 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 734637731 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804268 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804268 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954865 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954865 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857903 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857903 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17447.241536 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17447.241536 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22357.261515 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22357.261515 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency +system.cpu2.num_reads 100001 # number of read accesses completed +system.cpu2.num_writes 55556 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22129 # number of replacements +system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22527 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.604475 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.253516 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766120 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766120 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338010 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338010 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8679 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8679 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1137 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9816 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9816 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9816 # number of overall hits -system.cpu2.l1c.overall_hits::total 9816 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36478 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36478 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24024 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24024 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60502 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60502 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60502 # number of overall misses -system.cpu2.l1c.overall_misses::total 60502 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 647459345 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 647459345 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 543523925 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 543523925 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1190983270 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1190983270 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1190983270 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1190983270 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45157 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45157 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25161 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25161 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70318 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70318 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70318 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70318 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807804 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.807804 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954811 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954811 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860406 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860406 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860406 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860406 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 722959 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 390.469202 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.762635 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.762635 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9918 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9918 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9918 # number of overall hits +system.cpu2.l1c.overall_hits::total 9918 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36520 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36520 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60649 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60649 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60649 # number of overall misses +system.cpu2.l1c.overall_misses::total 60649 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 666978729 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 666978729 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 561823462 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 561823462 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1228802191 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1228802191 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1228802191 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1228802191 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45261 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45261 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25306 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25306 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70567 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70567 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70567 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70567 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806876 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806876 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953489 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953489 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859453 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859453 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859453 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859453 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18263.382503 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 18263.382503 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23284.158564 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 23284.158564 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20260.881317 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20260.881317 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20260.881317 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20260.881317 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 804972 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 59032 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66283 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.246900 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.144471 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.fast_writes 0 # number of fast writes performed -system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9774 # number of writebacks -system.cpu2.l1c.writebacks::total 9774 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36478 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24024 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24024 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60502 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60502 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9767 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9767 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5419 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5419 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15186 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15186 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 610981345 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 610981345 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 519499925 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 519499925 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1130481270 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1130481270 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1130481270 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1130481270 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722748371 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722748371 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 934057840 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 934057840 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1656806211 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1656806211 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807804 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807804 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954811 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954811 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860406 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860406 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286 # average overall mshr uncacheable latency -system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55255 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22194 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.395366 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13678 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22603 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.605141 # Average number of references to valid blocks. +system.cpu2.l1c.writebacks::writebacks 9821 # number of writebacks +system.cpu2.l1c.writebacks::total 9821 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36520 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36520 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60649 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60649 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60649 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60649 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9985 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5427 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15412 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 630459729 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 630459729 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537696462 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537696462 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1168156191 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1168156191 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1168156191 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1168156191 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 746431095 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 746431095 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 746431095 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 746431095 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806876 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806876 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953489 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953489 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859453 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859453 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17263.409885 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17263.409885 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22284.241452 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22284.241452 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency +system.cpu3.num_reads 99831 # number of read accesses completed +system.cpu3.num_writes 55461 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22291 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22681 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.588598 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.395366 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764444 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764444 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 403 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337339 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337339 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8923 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8923 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1132 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1132 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 10055 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 10055 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 10055 # number of overall hits -system.cpu3.l1c.overall_hits::total 10055 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36521 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36521 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23639 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23639 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60160 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60160 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60160 # number of overall misses -system.cpu3.l1c.overall_misses::total 60160 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 641069966 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 641069966 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 531956623 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 531956623 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1173026589 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1173026589 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1173026589 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1173026589 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45444 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45444 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24771 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24771 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70215 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70215 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70215 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70215 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.803648 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.803648 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954301 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954301 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.856797 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.856797 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.856797 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.856797 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 718925 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.006782 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.763685 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.763685 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1176 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9705 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9705 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9705 # number of overall hits +system.cpu3.l1c.overall_hits::total 9705 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36689 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36689 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23899 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23899 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60588 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60588 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60588 # number of overall misses +system.cpu3.l1c.overall_misses::total 60588 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 675943664 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 675943664 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 557387689 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 557387689 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1233331353 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1233331353 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1233331353 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1233331353 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45218 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45218 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25075 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25075 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70293 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70293 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811380 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.811380 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953101 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953101 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861935 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861935 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861935 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861935 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18423.605549 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 18423.605549 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23322.636470 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 23322.636470 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20356.033422 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20356.033422 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20356.033422 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20356.033422 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 801051 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 65873 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.224121 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.160536 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.fast_writes 0 # number of fast writes performed -system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9851 # number of writebacks -system.cpu3.l1c.writebacks::total 9851 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36521 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36521 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23639 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60160 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60160 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9973 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9973 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5527 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15500 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 604549966 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 604549966 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 508318623 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 508318623 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1112868589 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1112868589 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1112868589 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1112868589 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738348758 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738348758 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962176807 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962176807 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1700525565 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1700525565 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.803648 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.803648 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954301 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954301 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.856797 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.856797 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774 # average overall mshr uncacheable latency -system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98958 # number of read accesses completed -system.cpu4.num_writes 54718 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22445 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.205168 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22839 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.583476 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks +system.cpu3.l1c.writebacks::total 9857 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36689 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36689 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23899 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60588 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60588 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60588 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60588 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9849 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5582 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5582 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15431 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15431 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 639257664 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 639257664 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 533488689 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 533488689 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1172746353 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1172746353 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1172746353 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1172746353 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738856089 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738856089 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 738856089 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 738856089 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953101 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953101 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861935 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861935 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17423.687318 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17423.687318 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22322.636470 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22322.636470 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency +system.cpu4.num_reads 99911 # number of read accesses completed +system.cpu4.num_writes 55300 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22364 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.594344 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.205168 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766026 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766026 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 336585 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 336585 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8551 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8551 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1195 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1195 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9746 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9746 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9746 # number of overall hits -system.cpu4.l1c.overall_hits::total 9746 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36430 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36430 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23820 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23820 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60250 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60250 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60250 # number of overall misses -system.cpu4.l1c.overall_misses::total 60250 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 646410865 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 646410865 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 541537295 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 541537295 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1187948160 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1187948160 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1187948160 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1187948160 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44981 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44981 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25015 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809898 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809898 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952229 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952229 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860763 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860763 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860763 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860763 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 719943 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.705900 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.765051 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.765051 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1168 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10054 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10054 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10054 # number of overall hits +system.cpu4.l1c.overall_hits::total 10054 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36446 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36446 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24191 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24191 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60637 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60637 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60637 # number of overall misses +system.cpu4.l1c.overall_misses::total 60637 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 672672441 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 672672441 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 560233927 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 560233927 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1232906368 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1232906368 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1232906368 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1232906368 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45332 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45332 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25359 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70691 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70691 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70691 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70691 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803980 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.803980 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953941 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953941 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857775 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857775 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857775 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857775 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18456.687730 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 18456.687730 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23158.775040 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 23158.775040 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20332.575292 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20332.575292 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20332.575292 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20332.575292 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 801696 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 58800 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 65950 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.243929 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.156118 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.fast_writes 0 # number of fast writes performed -system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9851 # number of writebacks -system.cpu4.l1c.writebacks::total 9851 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36430 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23820 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23820 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60250 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60250 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60250 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60250 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9773 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5424 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5424 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15197 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 609980865 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 609980865 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 517717295 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 517717295 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1127698160 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1127698160 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1127698160 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1127698160 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 724329762 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 724329762 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 945564873 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 945564873 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1669894635 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1669894635 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809898 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809898 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952229 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952229 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860763 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860763 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614 # average overall mshr uncacheable latency -system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99011 # number of read accesses completed -system.cpu5.num_writes 55007 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22453 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.576438 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13255 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.579986 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9921 # number of writebacks +system.cpu4.l1c.writebacks::total 9921 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36446 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36446 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24191 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24191 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60637 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60637 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60637 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60637 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9877 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5522 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15399 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15399 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 636227441 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 636227441 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 536043927 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 536043927 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1172271368 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1172271368 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1172271368 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1172271368 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 739458183 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 739458183 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 739458183 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 739458183 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803980 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803980 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953941 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953941 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857775 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857775 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17456.715168 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17456.715168 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22158.816378 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22158.816378 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency +system.cpu5.num_reads 99665 # number of read accesses completed +system.cpu5.num_writes 55439 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22286 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22703 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592785 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.576438 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.764798 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.764798 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336606 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336606 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8524 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8524 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1134 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1134 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9658 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9658 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9658 # number of overall hits -system.cpu5.l1c.overall_hits::total 9658 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36435 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36435 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23892 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23892 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60327 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60327 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60327 # number of overall misses -system.cpu5.l1c.overall_misses::total 60327 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 644721410 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 644721410 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 540612961 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 540612961 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1185334371 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1185334371 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1185334371 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1185334371 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44959 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44959 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25026 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69985 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69985 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69985 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69985 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810405 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.810405 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954687 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954687 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.861999 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.861999 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.861999 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.861999 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 717184 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.859990 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765352 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765352 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1196 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9845 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9845 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9845 # number of overall hits +system.cpu5.l1c.overall_hits::total 9845 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36574 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36574 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24003 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24003 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60577 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60577 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60577 # number of overall misses +system.cpu5.l1c.overall_misses::total 60577 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 671451246 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 671451246 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 559158053 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 559158053 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1230609299 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1230609299 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1230609299 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1230609299 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45223 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25199 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25199 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70422 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70422 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70422 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70422 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808748 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808748 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952538 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952538 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860200 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860200 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860200 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860200 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18358.704161 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 18358.704161 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23295.340291 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 23295.340291 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20314.794377 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20314.794377 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20314.794377 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20314.794377 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 802483 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 58708 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66128 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.216120 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.135298 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.fast_writes 0 # number of fast writes performed -system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9910 # number of writebacks -system.cpu5.l1c.writebacks::total 9910 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36435 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36435 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23892 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60327 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60327 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60327 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60327 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9763 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9763 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15221 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 608288410 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 608288410 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 516720961 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 516720961 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1125009371 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1125009371 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1125009371 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1125009371 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 723860386 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 723860386 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 946272316 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 946272316 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1670132702 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1670132702 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810405 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810405 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954687 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954687 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.861999 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.861999 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928 # average overall mshr uncacheable latency -system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99860 # number of read accesses completed -system.cpu6.num_writes 55212 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22379 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.641405 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13476 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22769 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.591857 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 9886 # number of writebacks +system.cpu5.l1c.writebacks::total 9886 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36574 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36574 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24003 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24003 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60577 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60577 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60577 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60577 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5451 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15361 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 634877246 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 634877246 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 535156053 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 535156053 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1170033299 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1170033299 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1170033299 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1170033299 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 742019082 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 742019082 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 742019082 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 742019082 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808748 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808748 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952538 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952538 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860200 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860200 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17358.704161 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17358.704161 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22295.381952 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22295.381952 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency +system.cpu6.num_reads 99712 # number of read accesses completed +system.cpu6.num_writes 55282 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22239 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22637 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.596501 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.641405 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.766878 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.766878 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338111 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338111 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8761 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8761 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1100 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1100 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits -system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36533 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36533 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23935 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23935 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60468 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60468 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60468 # number of overall misses -system.cpu6.l1c.overall_misses::total 60468 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 641137331 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 641137331 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 545446790 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 545446790 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1186584121 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1186584121 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1186584121 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1186584121 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45294 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45294 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25035 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70329 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70329 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806575 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806575 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956062 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956062 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859788 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859788 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859788 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859788 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 722832 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.046110 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765715 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765715 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9825 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9825 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9825 # number of overall hits +system.cpu6.l1c.overall_hits::total 9825 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36548 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36548 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23952 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23952 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60500 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60500 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60500 # number of overall misses +system.cpu6.l1c.overall_misses::total 60500 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 674135322 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 674135322 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 560982121 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 560982121 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1235117443 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1235117443 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1235117443 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1235117443 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45306 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25019 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25019 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70325 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70325 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70325 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70325 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806692 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.957352 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.957352 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860292 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860292 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860292 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860292 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18445.204170 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 18445.204170 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23421.097236 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 23421.097236 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20415.164347 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20415.164347 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20415.164347 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20415.164347 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 802988 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 59177 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 65839 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.214746 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.196236 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.fast_writes 0 # number of fast writes performed -system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9900 # number of writebacks -system.cpu6.l1c.writebacks::total 9900 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36533 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36533 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23935 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23935 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60468 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60468 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9853 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9853 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5386 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5386 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 604606331 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 604606331 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 521511790 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 521511790 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1126118121 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1126118121 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1126118121 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1126118121 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 730958843 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 730958843 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 936459347 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 936459347 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1667418190 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1667418190 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806575 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806575 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956062 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956062 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859788 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859788 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036 # average overall mshr uncacheable latency -system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99316 # number of read accesses completed -system.cpu7.num_writes 55530 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22262 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.242621 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13656 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22650 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.602914 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9826 # number of writebacks +system.cpu6.l1c.writebacks::total 9826 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36548 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36548 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23952 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23952 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60500 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60500 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60500 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60500 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9861 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5592 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5592 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15453 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15453 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 637587322 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 637587322 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 537030121 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 537030121 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1174617443 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1174617443 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1174617443 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1174617443 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 737828201 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 737828201 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 737828201 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 737828201 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806692 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.957352 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.957352 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860292 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860292 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17445.204170 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17445.204170 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22421.097236 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22421.097236 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency +system.cpu7.num_reads 99031 # number of read accesses completed +system.cpu7.num_writes 54931 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22638 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 23038 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.588419 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.242621 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766099 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766099 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338652 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338652 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8912 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8912 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1186 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1186 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 10098 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 10098 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 10098 # number of overall hits -system.cpu7.l1c.overall_hits::total 10098 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36380 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36380 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23998 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23998 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60378 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60378 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60378 # number of overall misses -system.cpu7.l1c.overall_misses::total 60378 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 644409565 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 644409565 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 538142857 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 538142857 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1182552422 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1182552422 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1182552422 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1182552422 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25184 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25184 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70476 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70476 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70476 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70476 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803232 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.803232 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952907 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.952907 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.856717 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.856717 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.856717 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.856717 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 716334 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.993848 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.765613 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.765613 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9966 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9966 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9966 # number of overall hits +system.cpu7.l1c.overall_hits::total 9966 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36554 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36554 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24149 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24149 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60703 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60703 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60703 # number of overall misses +system.cpu7.l1c.overall_misses::total 60703 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 675691654 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 675691654 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 565139421 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 565139421 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1240831075 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1240831075 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1240831075 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1240831075 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45372 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45372 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25297 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25297 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70669 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70669 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70669 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70669 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805651 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805651 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954619 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954619 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858976 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858976 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858976 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858976 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18484.752804 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 18484.752804 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23402.187296 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 23402.187296 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20441.017330 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20441.017330 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20441.017330 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20441.017330 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 799894 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 65859 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.180065 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.145553 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.fast_writes 0 # number of fast writes performed -system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9846 # number of writebacks -system.cpu7.l1c.writebacks::total 9846 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36380 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36380 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23998 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23998 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60378 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60378 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9762 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9762 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5539 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5539 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15301 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15301 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 608029565 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 608029565 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 514144857 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 514144857 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1122174422 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1122174422 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1122174422 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1122174422 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 722808914 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 722808914 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 961004780 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 961004780 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1683813694 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1683813694 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803232 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803232 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952907 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952907 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.856717 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.856717 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066 # average overall mshr uncacheable latency -system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13767 # number of replacements -system.l2c.tags.tagsinuse 787.442113 # Cycle average of tags in use -system.l2c.tags.total_refs 164717 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14568 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.306768 # Average number of references to valid blocks. +system.cpu7.l1c.writebacks::writebacks 9912 # number of writebacks +system.cpu7.l1c.writebacks::total 9912 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36554 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36554 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24149 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24149 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60703 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60703 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60703 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60703 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9740 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9740 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5359 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5359 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15099 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15099 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 639138654 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 639138654 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 540990421 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 540990421 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1180129075 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1180129075 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1180129075 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1180129075 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 730529776 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 730529776 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 730529776 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 730529776 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954619 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954619 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858976 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858976 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17484.780161 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17484.780161 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22402.187296 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22402.187296 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency +system.l2c.tags.replacements 13688 # number of replacements +system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use +system.l2c.tags.total_refs 164623 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14478 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.370562 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.095360 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.568517 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.047502 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.052359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.453742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.826765 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.175771 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.149899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 8.072198 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006882 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006887 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007279 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768986 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 661 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2101238 # Number of tag accesses -system.l2c.tags.data_accesses 2101238 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 77585 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77585 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 280 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 286 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 296 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 265 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 264 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 295 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2258 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1755 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1739 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1749 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1791 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1796 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1820 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1726 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14259 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10845 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10830 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10896 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10859 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10783 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 11038 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10953 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10583 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86787 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12600 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12309 # number of demand (read+write) hits -system.l2c.demand_hits::total 101046 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12600 # number of overall hits -system.l2c.overall_hits::cpu1 12713 # number of overall hits -system.l2c.overall_hits::cpu2 12635 # number of overall hits -system.l2c.overall_hits::cpu3 12608 # number of overall hits -system.l2c.overall_hits::cpu4 12574 # number of overall hits -system.l2c.overall_hits::cpu5 12834 # number of overall hits -system.l2c.overall_hits::cpu6 12773 # number of overall hits -system.l2c.overall_hits::cpu7 12309 # number of overall hits -system.l2c.overall_hits::total 101046 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2028 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2036 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2114 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2014 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2072 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2019 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16296 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4674 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4592 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4655 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4541 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4557 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4724 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36984 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 715 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 735 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 738 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 731 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 726 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 715 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 749 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5780 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5389 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5327 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5393 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5272 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5283 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5354 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5395 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5351 # number of demand (read+write) misses -system.l2c.demand_misses::total 42764 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5389 # number of overall misses -system.l2c.overall_misses::cpu1 5327 # number of overall misses -system.l2c.overall_misses::cpu2 5393 # number of overall misses -system.l2c.overall_misses::cpu3 5272 # number of overall misses -system.l2c.overall_misses::cpu4 5283 # number of overall misses -system.l2c.overall_misses::cpu5 5354 # number of overall misses -system.l2c.overall_misses::cpu6 5395 # number of overall misses -system.l2c.overall_misses::cpu7 5351 # number of overall misses -system.l2c.overall_misses::total 42764 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 32787478 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 32272475 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 34405982 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 32097495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 34646656 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 31653981 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 32901471 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 32271475 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 263037013 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 151347885 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 149012881 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 150333871 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 147794053 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 149925888 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 151442380 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 154217889 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 149568871 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1203643718 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 49081904 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 50341908 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 51226892 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 50079413 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 49691401 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 48946419 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 46272414 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 51820900 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 397461251 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 200429789 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 199354789 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 201560763 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 197873466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 199617289 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 200388799 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 200490303 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 201389771 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1601104969 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 200429789 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 199354789 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 201560763 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 197873466 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 199617289 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 200388799 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 200490303 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 201389771 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1601104969 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77585 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77585 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2322 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2410 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2279 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2292 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18554 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6429 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6475 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6394 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6290 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6348 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6435 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6544 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6328 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51243 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11560 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11565 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11634 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11590 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11509 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11753 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11624 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11332 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92567 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17989 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18040 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17880 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17857 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17660 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143810 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17989 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18040 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17880 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17857 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17660 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143810 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.878683 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.876830 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.877178 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.883721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.886986 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.869204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.872900 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.880890 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878301 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.727018 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.709189 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.728026 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.721940 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.717864 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.720901 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.721883 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.727244 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.721738 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.061851 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.063554 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.063435 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.063072 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.063081 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.060836 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.057725 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.066096 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.062441 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.299572 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.295288 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.299146 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.294855 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.295850 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.294370 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.296951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.303001 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.297365 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.299572 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.295288 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.299146 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.294855 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.295850 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.294370 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.296951 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.303001 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.297365 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16167.395464 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 15850.920923 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16275.298959 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 15937.187190 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 16721.359073 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 15930.539004 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16239.620434 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 15983.890540 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16141.201092 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 32380.805520 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 32450.540287 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 32295.138776 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 32546.587316 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 32900.129032 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 32645.479629 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 32645.615792 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 32500.841156 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 32544.984804 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68646.019580 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68492.391837 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69413.132791 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68508.088919 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68445.455923 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68456.530070 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68960.378539 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69186.782377 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 68764.922318 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 37192.389868 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 37423.463300 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 37374.515668 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 37532.903263 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 37784.836078 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 37427.866829 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 37162.243373 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 37635.913100 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 37440.486601 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 37192.389868 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 37423.463300 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 37374.515668 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 37532.903263 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 37784.836078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 37427.866829 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 37162.243373 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 37635.913100 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 37440.486601 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 15217 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 726.348525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.677170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.765222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.924842 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.010620 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.585654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.814501 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.441816 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 6.991588 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709325 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006763 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007408 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006655 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007267 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.764219 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 664 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2107372 # Number of tag accesses +system.l2c.tags.data_accesses 2107372 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 284 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 276 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 280 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 255 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 262 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2151 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1876 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1780 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1805 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1782 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1816 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1727 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1803 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1809 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14398 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10873 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10958 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10812 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 11007 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 10755 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10989 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 11012 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10808 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 87214 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12749 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12738 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12789 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12571 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12716 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12815 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12617 # number of demand (read+write) hits +system.l2c.demand_hits::total 101612 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12749 # number of overall hits +system.l2c.overall_hits::cpu1 12738 # number of overall hits +system.l2c.overall_hits::cpu2 12617 # number of overall hits +system.l2c.overall_hits::cpu3 12789 # number of overall hits +system.l2c.overall_hits::cpu4 12571 # number of overall hits +system.l2c.overall_hits::cpu5 12716 # number of overall hits +system.l2c.overall_hits::cpu6 12815 # number of overall hits +system.l2c.overall_hits::cpu7 12617 # number of overall hits +system.l2c.overall_hits::total 101612 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 2119 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2003 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2061 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2101 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1934 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2026 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2139 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2027 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16410 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4596 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4672 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4641 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4561 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4696 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4677 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4637 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4651 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37131 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 698 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 712 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 734 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 737 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 740 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 681 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 697 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5737 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5375 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5298 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5436 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5358 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5375 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5348 # number of demand (read+write) misses +system.l2c.demand_misses::total 42868 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5294 # number of overall misses +system.l2c.overall_misses::cpu1 5384 # number of overall misses +system.l2c.overall_misses::cpu2 5375 # number of overall misses +system.l2c.overall_misses::cpu3 5298 # number of overall misses +system.l2c.overall_misses::cpu4 5436 # number of overall misses +system.l2c.overall_misses::cpu5 5358 # number of overall misses +system.l2c.overall_misses::cpu6 5375 # number of overall misses +system.l2c.overall_misses::cpu7 5348 # number of overall misses +system.l2c.overall_misses::total 42868 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 34306000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 32515999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 33970000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 33665000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 30524499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 33417998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 35180998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 31945000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 265525494 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 148628443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 153234943 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 151708946 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 148204781 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 153854439 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 151693945 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 152734439 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 151392920 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1211452856 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 49327224 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 49579908 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 50488876 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 50929398 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 51564743 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 47695729 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 51087902 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 48881401 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 399555181 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 197955667 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 202814851 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 202197822 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 199134179 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 205419182 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 199389674 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 203822341 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 200274321 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1611008037 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 197955667 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 202814851 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 202197822 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 199134179 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 205419182 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 199389674 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 203822341 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 200274321 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1611008037 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77671 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77671 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2391 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2287 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2337 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2381 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2189 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2309 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2378 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18561 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6472 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6452 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6446 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6343 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6512 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6404 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6440 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6460 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51529 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11571 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11670 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11546 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11744 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11495 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11670 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11750 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11505 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92951 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18043 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18122 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18087 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18007 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18074 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17965 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144480 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18043 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18122 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18087 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18007 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18074 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17965 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144480 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.886240 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.875820 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.881900 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882402 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.883508 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.877436 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.899495 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.885540 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.884112 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.710136 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.724117 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.719981 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.719060 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.721130 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.730325 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.720031 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.719969 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.720585 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.060323 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.061011 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063572 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.062755 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.064376 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.058355 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.062809 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.060582 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.061721 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.293410 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.297097 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.298744 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.292918 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.301883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.296448 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.295492 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.297690 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.296705 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.293410 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.297097 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.298744 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.292918 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.301883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.296448 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.295492 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.297690 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.296705 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16189.712128 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 16233.649026 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16482.290150 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 16023.322228 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 15783.091520 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 16494.569595 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16447.404395 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 15759.743463 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16180.712614 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 32338.651654 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 32798.575128 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 32688.848524 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 32493.922605 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 32762.870315 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 32434.027154 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 32938.201208 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 32550.617072 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 32626.453799 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70669.375358 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69634.702247 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68785.934605 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69103.660787 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69682.085135 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70037.781204 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69224.799458 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70131.134864 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 69645.316542 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 37392.456932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 37669.920319 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 37618.199442 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 37586.670253 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 37788.664827 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 37213.451661 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 37920.435535 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 37448.451945 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 37580.667094 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 37392.456932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 37669.920319 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 37618.199442 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 37586.670253 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 37788.664827 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 37213.451661 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 37920.435535 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 37448.451945 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 37580.667094 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 19223 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2217 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2973 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.863780 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.465859 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6315 # number of writebacks -system.l2c.writebacks::total 6315 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.writebacks::writebacks 6255 # number of writebacks +system.l2c.writebacks::total 6255 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 38 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 3 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 13 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 14 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 83 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 97 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1226 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1226 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2028 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2036 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2114 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2013 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2071 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2026 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2018 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16293 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4668 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4588 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4650 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4536 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4555 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4635 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4720 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4594 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36946 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 728 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 733 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 725 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 715 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 705 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 668 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 745 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5721 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5370 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5316 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5383 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5261 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5270 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5340 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5388 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5339 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42667 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5370 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5316 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5383 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5261 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5270 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5340 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5388 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5339 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42667 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9705 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9715 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9767 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9972 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9773 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9763 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9852 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9762 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78309 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5486 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5400 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5419 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5526 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5423 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5386 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5538 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43636 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15191 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15115 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15186 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15498 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15196 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15221 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15238 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15300 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 121945 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 39014213 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 39232059 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 40780597 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 38858267 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 39920741 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 38246941 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 38960747 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 38849596 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 313863161 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 104350937 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 102876549 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 103582540 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 102275935 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 104240403 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 104871121 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 106828418 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 103332582 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 832358485 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41502671 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42773140 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 43592644 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 42525173 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 42051842 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 41416678 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39402449 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 44058192 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 337322789 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 145853608 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 145649689 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 147175184 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 144801108 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 146292245 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 146287799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 146230867 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 147390774 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1169681274 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 145853608 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 145649689 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 147175184 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 144801108 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 146292245 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 146287799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 146230867 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 147390774 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1169681274 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 503077334 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 503572362 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 506294012 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 516868052 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 506181413 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 506175452 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 511232158 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 505608163 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 4059008946 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 292251287 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 290147025 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 292888717 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297220505 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290868538 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 292450481 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 288970880 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 297704385 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2342501818 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 795328621 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 793719387 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 799182729 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 814088557 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 797049951 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 798625933 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 800203038 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 803312548 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6401510764 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 123 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1242 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1242 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 2119 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2003 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2060 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2101 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1934 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2026 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2138 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2027 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16408 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4594 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4668 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4632 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4558 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4689 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4672 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4632 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4646 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 37091 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 687 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 702 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 720 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 724 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu4 732 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 672 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 730 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 687 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5654 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5370 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5352 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5282 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5421 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5344 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5362 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5333 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 42745 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5370 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5352 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5282 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5421 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5344 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5362 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5333 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 42745 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9739 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78775 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5399 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5467 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5579 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5520 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5590 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5357 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43790 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15142 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15278 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15397 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15451 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15096 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122565 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 40841935 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 38564215 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 39647592 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 40417370 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 37145795 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 38899918 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 41229107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 39009527 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 315755459 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 102604763 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 106353151 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 105053935 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 102451130 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 106647279 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 104810242 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 106228599 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 104763871 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 838912970 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 41984323 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42028851 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42690563 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 43142020 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 43825891 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 40479162 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 43405339 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 41523836 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 339079985 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 144589086 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 148382002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 147744498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 145593150 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 150473170 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 145289404 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 149633938 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 146287707 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1177992955 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 144589086 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 148382002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 147744498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 145593150 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 150473170 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 145289404 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 149633938 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 146287707 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1177992955 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 506398152 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 509332752 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 518417832 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 511679337 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 512962712 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 514656758 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 512189388 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 505729590 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4091366521 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 506398152 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 509332752 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 518417832 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 511679337 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 512962712 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 514656758 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 512189388 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 505729590 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4091366521 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878683 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.876830 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.877178 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.883282 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.886558 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.869204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.872900 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880454 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.878139 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726085 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.708571 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.727244 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.721145 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717549 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720280 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.721271 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.725980 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.720996 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060727 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062949 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063005 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062554 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062125 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059985 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.057467 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065743 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061804 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.296690 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.296690 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78306 # Transaction distribution -system.membus.trans_dist::ReadResp 84006 # Transaction distribution -system.membus.trans_dist::WriteReq 43633 # Transaction distribution -system.membus.trans_dist::WriteResp 43633 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6315 # Transaction distribution -system.membus.trans_dist::CleanEvict 1254 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60980 # Transaction distribution -system.membus.trans_dist::ReadExReq 48711 # Transaction distribution -system.membus.trans_dist::ReadExResp 3097 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5709 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 375644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 375644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1089674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1089674 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56426 # Total snoops (count) -system.membus.snoop_fanout::samples 252331 # Request fanout histogram +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886240 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.875820 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.881472 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882402 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.883508 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877436 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.899075 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885540 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.884004 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.709827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.723497 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.718585 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718587 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.720055 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.729544 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719255 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.719195 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.719808 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059373 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060154 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062359 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.061649 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.063680 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.057584 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.062128 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059713 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060828 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.295854 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.295854 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19274.155262 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19253.227659 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19246.403883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19237.206092 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19206.719235 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19200.354393 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19283.960243 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19244.956586 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19243.994332 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22334.515237 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22783.451371 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22680.037781 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22477.211496 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22744.141395 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22433.699058 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22933.635363 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22549.261946 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 22617.696207 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61112.551674 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59870.158120 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59292.448611 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59588.425414 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59871.435792 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60236.848214 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59459.368493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60442.264920 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59971.698797 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51975.587807 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51914.458465 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51919.662694 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51952.415169 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51935.072593 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51933.073461 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51940.917554 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51928.287298 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51937.372529 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 33443.280412 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 33337.658856 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 33637.284713 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 33165.629829 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 33315.757096 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency +system.membus.trans_dist::ReadReq 78773 # Transaction distribution +system.membus.trans_dist::ReadResp 84410 # Transaction distribution +system.membus.trans_dist::WriteReq 43787 # Transaction distribution +system.membus.trans_dist::WriteResp 43783 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6255 # Transaction distribution +system.membus.trans_dist::CleanEvict 1278 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61348 # Transaction distribution +system.membus.trans_dist::ReadExReq 49073 # Transaction distribution +system.membus.trans_dist::ReadExResp 3087 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5646 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 377440 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1081783 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1081783 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56900 # Total snoops (count) +system.membus.snoop_fanout::samples 253448 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 252331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253448 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 252331 # Request fanout histogram -system.membus.reqLayer0.occupancy 290210873 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 244257000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 46.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663692 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283641 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 333885 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12353 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6661 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78309 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370176 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43636 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43632 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83900 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105566 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29367 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161854 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161852 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 291888 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133276 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 132901 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133285 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 132788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1065036 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1790740 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1793737 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783183 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1779785 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1777562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801715 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1799686 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1764480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14290888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 334512 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 624442 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148246 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.987708 # Request fanout histogram +system.membus.snoop_fanout::total 253448 # Request fanout histogram +system.membus.reqLayer0.occupancy 289313112 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 57.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 244976000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 49.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 662658 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 284136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 332740 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43790 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43780 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83926 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105295 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29475 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162920 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162916 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292639 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133502 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133647 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133528 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1068709 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1800550 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783667 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1792707 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1790564 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791999 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1796631 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14339895 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335681 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 623777 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148975 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.984758 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 174331 27.92% 27.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 257461 41.23% 69.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 132941 21.29% 90.44% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 47060 7.54% 97.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 10899 1.75% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1610 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 136 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 172972 27.73% 27.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 258444 41.43% 69.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133198 21.35% 90.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 46670 7.48% 98.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 10752 1.72% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1603 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 135 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 624442 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 496537925 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 93.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101982318 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102105458 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101942894 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101777352 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101724075 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101820787 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102063169 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101980781 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.2 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 623777 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 493769156 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102470874 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102502346 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102645272 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102492443 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102725884 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102549521 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102424000 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 102560017 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 8e6ab353a..e76d0cce6 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.134742 # Nu sim_ticks 134741611500 # Number of ticks simulated final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536259 # Simulator instruction rate (inst/s) -host_op_rate 536259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 817928903 # Simulator tick rate (ticks/s) -host_mem_usage 239376 # Number of bytes of host memory used -host_seconds 164.74 # Real time elapsed on the host +host_inst_rate 1303886 # Simulator instruction rate (inst/s) +host_op_rate 1303885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1988750581 # Simulator tick rate (ticks/s) +host_mem_usage 260188 # Number of bytes of host memory used +host_seconds 67.75 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -198,8 +198,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks system.cpu.dcache.writebacks::total 168278 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses @@ -234,7 +232,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. @@ -294,8 +291,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 74391 # number of writebacks system.cpu.icache.writebacks::total 74391 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses @@ -322,7 +317,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 131998 # number of replacements system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. @@ -431,8 +425,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks system.cpu.l2cache.writebacks::total 114382 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses @@ -487,7 +479,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index c10ef56cb..2518d4d22 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu sim_ticks 128076834500 # Number of ticks simulated final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 508798 # Simulator instruction rate (inst/s) -host_op_rate 649592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 925989388 # Simulator tick rate (ticks/s) -host_mem_usage 253236 # Number of bytes of host memory used -host_seconds 138.31 # Real time elapsed on the host +host_inst_rate 775777 # Simulator instruction rate (inst/s) +host_op_rate 990450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1411878896 # Simulator tick rate (ticks/s) +host_mem_usage 277764 # Number of bytes of host memory used +host_seconds 90.71 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -300,8 +300,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks system.cpu.dcache.writebacks::total 128175 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits @@ -350,7 +348,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. @@ -410,8 +407,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 16890 # number of writebacks system.cpu.icache.writebacks::total 16890 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses @@ -438,7 +433,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95333 # number of replacements system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. @@ -547,8 +541,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks system.cpu.l2cache.writebacks::total 86150 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses @@ -603,7 +595,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 75f9fb3c6..97bc2f274 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu sim_ticks 203115946500 # Number of ticks simulated final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 864116 # Simulator instruction rate (inst/s) -host_op_rate 875304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1305930078 # Simulator tick rate (ticks/s) -host_mem_usage 235576 # Number of bytes of host memory used -host_seconds 155.53 # Real time elapsed on the host +host_inst_rate 1277402 # Simulator instruction rate (inst/s) +host_op_rate 1293942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1930526358 # Simulator tick rate (ticks/s) +host_mem_usage 259920 # Number of bytes of host memory used +host_seconds 105.21 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -178,8 +178,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks system.cpu.dcache.writebacks::total 123865 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses @@ -222,7 +220,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. @@ -283,8 +280,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 184976 # number of writebacks system.cpu.icache.writebacks::total 184976 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses @@ -311,7 +306,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 99022 # number of replacements system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. @@ -420,8 +414,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks system.cpu.l2cache.writebacks::total 85270 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses @@ -476,7 +468,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index da47b432f..c2aa1fab9 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118763 # Nu sim_ticks 118762761500 # Number of ticks simulated final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 546473 # Simulator instruction rate (inst/s) -host_op_rate 546472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 706184987 # Simulator tick rate (ticks/s) -host_mem_usage 235092 # Number of bytes of host memory used -host_seconds 168.18 # Real time elapsed on the host +host_inst_rate 1409040 # Simulator instruction rate (inst/s) +host_op_rate 1409039 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1820846467 # Simulator tick rate (ticks/s) +host_mem_usage 255756 # Number of bytes of host memory used +host_seconds 65.22 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -193,8 +193,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses @@ -229,7 +227,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. @@ -290,8 +287,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 6681 # number of writebacks system.cpu.icache.writebacks::total 6681 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses @@ -318,7 +313,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. @@ -427,8 +421,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses @@ -477,7 +469,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 9f34f3699..d21481ee3 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151849 # Simulator instruction rate (inst/s) -host_op_rate 1214340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543000471 # Simulator tick rate (ticks/s) -host_mem_usage 272972 # Number of bytes of host memory used -host_seconds 149.19 # Real time elapsed on the host +host_inst_rate 927075 # Simulator instruction rate (inst/s) +host_op_rate 977372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1241896591 # Simulator tick rate (ticks/s) +host_mem_usage 272260 # Number of bytes of host memory used +host_seconds 185.36 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -295,8 +295,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses @@ -339,7 +337,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. @@ -400,8 +397,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1506 # number of writebacks system.cpu.icache.writebacks::total 1506 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses @@ -428,7 +423,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. @@ -537,8 +531,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses @@ -587,7 +579,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 9e9ac48d5..c87fb96c4 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270600 # Nu sim_ticks 270599529500 # Number of ticks simulated final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 568132 # Simulator instruction rate (inst/s) -host_op_rate 568133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 794730164 # Simulator tick rate (ticks/s) -host_mem_usage 235264 # Number of bytes of host memory used -host_seconds 340.49 # Real time elapsed on the host +host_inst_rate 1248385 # Simulator instruction rate (inst/s) +host_op_rate 1248386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1746300725 # Simulator tick rate (ticks/s) +host_mem_usage 255364 # Number of bytes of host memory used +host_seconds 154.96 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -173,8 +173,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2 # number of writebacks system.cpu.dcache.writebacks::total 2 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses @@ -217,7 +215,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. @@ -278,8 +275,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 10362 # number of writebacks system.cpu.icache.writebacks::total 10362 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses @@ -306,7 +301,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. @@ -409,8 +403,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses @@ -459,7 +451,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 01cb3bdc8..25c6ff3ba 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250987 # Nu sim_ticks 250987138500 # Number of ticks simulated final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290260 # Simulator instruction rate (inst/s) -host_op_rate 486501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 551606975 # Simulator tick rate (ticks/s) -host_mem_usage 279340 # Number of bytes of host memory used -host_seconds 455.01 # Real time elapsed on the host +host_inst_rate 637690 # Simulator instruction rate (inst/s) +host_op_rate 1068827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1211861746 # Simulator tick rate (ticks/s) +host_mem_usage 298388 # Number of bytes of host memory used +host_seconds 207.11 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -164,8 +164,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 7 # number of writebacks system.cpu.dcache.writebacks::total 7 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses @@ -200,7 +198,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. @@ -261,8 +258,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 2836 # number of writebacks system.cpu.icache.writebacks::total 2836 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses @@ -289,7 +284,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. @@ -398,8 +392,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses @@ -448,7 +440,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |