diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
| commit | c37086633189ec6cc754bcd24369e6e2d15cf1f8 (patch) | |
| tree | 9e66f2e8b7d7b8ea7d9ae7a3cf2c8bd6ee19d51b /tests/quick | |
| parent | 6fbea1506498f56f6855b139bb82faa3bdc193bb (diff) | |
| download | gem5-c37086633189ec6cc754bcd24369e6e2d15cf1f8.tar.xz | |
ARM: Update regressions for CLCD and KMI additions
Diffstat (limited to 'tests/quick')
9 files changed, 514 insertions, 496 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 034c2aa0b..505488008 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -178,7 +178,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.clcd_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.kmi0_fake.pio system.realview.kmi1_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -282,7 +282,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd_fake dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0_fake kmi1_fake l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -294,17 +294,22 @@ pio_addr=268451840 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[18] +pio=system.iobus.port[20] -[system.realview.clcd_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=41667 +gic=system.realview.gic +int_num=55 +max_backoff_delay=10000000 +min_backoff_delay=4000 pio_addr=268566528 -pio_latency=1000 +pio_latency=10000 platform=system.realview system=system -pio=system.iobus.port[10] +dma=system.iobus.port[25] +pio=system.iobus.port[5] [system.realview.dmac_fake] type=AmbaFake @@ -314,7 +319,7 @@ pio_addr=268632064 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[5] +pio=system.iobus.port[8] [system.realview.flash_fake] type=IsaFake @@ -351,7 +356,7 @@ pio_addr=268513280 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[13] +pio=system.iobus.port[15] [system.realview.gpio1_fake] type=AmbaFake @@ -361,7 +366,7 @@ pio_addr=268517376 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[14] +pio=system.iobus.port[16] [system.realview.gpio2_fake] type=AmbaFake @@ -371,27 +376,31 @@ pio_addr=268521472 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[15] +pio=system.iobus.port[17] -[system.realview.kmi0_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=100000 +int_num=52 pio_addr=268460032 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[20] +pio=system.iobus.port[6] -[system.realview.kmi1_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=100000 +int_num=53 pio_addr=268464128 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[21] +pio=system.iobus.port[7] [system.realview.l2x0_fake] type=IsaFake @@ -417,7 +426,7 @@ pio_addr=268455936 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[19] +pio=system.iobus.port[21] [system.realview.realview_io] type=RealViewCtrl @@ -446,7 +455,7 @@ pio_addr=268492800 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[17] +pio=system.iobus.port[19] [system.realview.smc_fake] type=AmbaFake @@ -456,7 +465,7 @@ pio_addr=269357056 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[9] +pio=system.iobus.port[12] [system.realview.sp810_fake] type=AmbaFake @@ -466,7 +475,7 @@ pio_addr=268439552 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[11] +pio=system.iobus.port[13] [system.realview.ssp_fake] type=AmbaFake @@ -476,7 +485,7 @@ pio_addr=268488704 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[16] +pio=system.iobus.port[18] [system.realview.timer0] type=Sp804 @@ -527,7 +536,7 @@ pio_addr=268476416 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[6] +pio=system.iobus.port[9] [system.realview.uart2_fake] type=AmbaFake @@ -537,7 +546,7 @@ pio_addr=268480512 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[7] +pio=system.iobus.port[10] [system.realview.uart3_fake] type=AmbaFake @@ -547,7 +556,7 @@ pio_addr=268484608 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[8] +pio=system.iobus.port[11] [system.realview.watchdog_fake] type=AmbaFake @@ -557,7 +566,7 @@ pio_addr=268500992 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[12] +pio=system.iobus.port[14] [system.terminal] type=Terminal diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 7d0a8d3b5..05fcdedb2 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 1 2010 22:55:27 -M5 revision 8dd1bd50f739 7724 default qtip tip ext/vfp_serial_nonspec_flags.patch -M5 started Oct 1 2010 23:07:06 -M5 executing on aus-bc3-b7 +M5 compiled Oct 15 2010 11:17:32 +M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip +M5 started Oct 15 2010 11:17:48 +M5 executing on aus-bc3-b4 command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 25749159000 because m5_exit instruction encountered +Exiting @ tick 25821310500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 11c550b7b..1bfa8bc8a 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1902681 # Simulator instruction rate (inst/s) -host_mem_usage 378772 # Number of bytes of host memory used -host_seconds 26.70 # Real time elapsed on the host -host_tick_rate 964308738 # Simulator tick rate (ticks/s) +host_inst_rate 1831927 # Simulator instruction rate (inst/s) +host_mem_usage 384484 # Number of bytes of host memory used +host_seconds 27.81 # Real time elapsed on the host +host_tick_rate 928414614 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50805202 # Number of instructions simulated -sim_seconds 0.025749 # Number of seconds simulated -sim_ticks 25749159000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 96510 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96510 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 91456 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 91456 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052368 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5054 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5054 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7686910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7686910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7455461 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7455461 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030109 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 231449 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 231449 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 96509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 96509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 96509 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 96509 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6583516 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6583516 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6409119 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6409119 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.026490 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 174397 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 174397 # number of WriteReq misses +sim_insts 50949504 # Number of instructions simulated +sim_seconds 0.025821 # Number of seconds simulated +sim_ticks 25821310500 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.349377 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14270426 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14270426 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13864580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13864580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028440 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 405846 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 405846 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999474 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.730497 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14270426 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14270426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13864580 # number of overall hits +system.cpu.dcache.overall_hits::0 13915504 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13864580 # number of overall hits +system.cpu.dcache.overall_hits::total 13915504 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028440 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 405846 # number of overall misses +system.cpu.dcache.overall_misses::0 403872 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 405846 # number of overall misses +system.cpu.dcache.overall_misses::total 403872 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 408645 # number of replacements -system.cpu.dcache.sampled_refs 409157 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 406424 # number of replacements +system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.730497 # Cycle average of tags in use -system.cpu.dcache.total_refs 14054288 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use +system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 380684 # number of writebacks -system.cpu.dtb.accesses 15287038 # DTB accesses +system.cpu.dcache.writebacks 379025 # number of writebacks +system.cpu.dtb.accesses 15336291 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2258 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15281544 # DTB hits +system.cpu.dtb.hits 15330762 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5494 # DTB misses +system.cpu.dtb.misses 5529 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 771 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8595265 # DTB read accesses -system.cpu.dtb.read_hits 8590763 # DTB read hits -system.cpu.dtb.read_misses 4502 # DTB read misses -system.cpu.dtb.write_accesses 6691773 # DTB write accesses -system.cpu.dtb.write_hits 6690781 # DTB write hits -system.cpu.dtb.write_misses 992 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41062986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41062986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 40634897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40634897 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 428089 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 428089 # number of ReadReq misses +system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8622893 # DTB read accesses +system.cpu.dtb.read_hits 8618361 # DTB read hits +system.cpu.dtb.read_misses 4532 # DTB read misses +system.cpu.dtb.write_accesses 6713398 # DTB write accesses +system.cpu.dtb.write_hits 6712401 # DTB write hits +system.cpu.dtb.write_misses 997 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.921831 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41062986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41062986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 40634897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40634897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 428089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 428089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.928964 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 475.629536 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41062986 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41062986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 40634897 # number of overall hits +system.cpu.icache.overall_hits::0 40741841 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 40634897 # number of overall hits +system.cpu.icache.overall_hits::total 40741841 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 428089 # number of overall misses +system.cpu.icache.overall_misses::0 430782 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 428089 # number of overall misses +system.cpu.icache.overall_misses::total 430782 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 427576 # number of replacements -system.cpu.icache.sampled_refs 428088 # Sample count of references to valid blocks. +system.cpu.icache.replacements 430269 # number of replacements +system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 475.629536 # Cycle average of tags in use -system.cpu.icache.total_refs 40634897 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use +system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 30587 # number of writebacks +system.cpu.icache.writebacks 33727 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41064113 # DTB accesses +system.cpu.itb.accesses 41173750 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -208,11 +208,11 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41061294 # DTB hits -system.cpu.itb.inst_accesses 41064113 # ITB inst accesses -system.cpu.itb.inst_hits 41061294 # ITB inst hits -system.cpu.itb.inst_misses 2819 # ITB inst misses -system.cpu.itb.misses 2819 # DTB misses +system.cpu.itb.hits 41170928 # DTB hits +system.cpu.itb.inst_accesses 41173750 # ITB inst accesses +system.cpu.itb.inst_hits 41170928 # ITB inst hits +system.cpu.itb.inst_misses 2822 # ITB inst misses +system.cpu.itb.misses 2822 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses @@ -224,9 +224,9 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 51498319 # number of cpu cycles simulated -system.cpu.num_insts 50805202 # Number of instructions executed -system.cpu.num_refs 16039990 # Number of memory references +system.cpu.numCycles 51642622 # number of cpu cycles simulated +system.cpu.num_insts 50949504 # Number of instructions executed +system.cpu.num_refs 16092645 # Number of memory references system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -294,61 +294,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 172654 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 172654 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 63568 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 63568 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.631819 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109086 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109086 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 662584 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 669329 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 644874 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6723 # number of ReadReq hits -system.l2c.ReadReq_hits::total 651597 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.026729 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.029990 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 17710 # number of ReadReq misses -system.l2c.ReadReq_misses::1 22 # number of ReadReq misses -system.l2c.ReadReq_misses::total 17732 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1743 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits +system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses +system.l2c.ReadReq_misses::1 24 # number of ReadReq misses +system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.990247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1726 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1726 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 411271 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 411271 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 411271 # number of Writeback hits -system.l2c.Writeback_hits::total 411271 # number of Writeback hits +system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 412752 # number of Writeback hits +system.l2c.Writeback_hits::total 412752 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.881395 # Average number of references to valid blocks. +system.l2c.avg_refs 6.885433 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 835238 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6745 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 841983 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 708442 # number of demand (read+write) hits -system.l2c.demand_hits::1 6723 # number of demand (read+write) hits -system.l2c.demand_hits::total 715165 # number of demand (read+write) hits +system.l2c.demand_hits::0 708536 # number of demand (read+write) hits +system.l2c.demand_hits::1 6049 # number of demand (read+write) hits +system.l2c.demand_hits::total 714585 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.151808 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003262 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.155070 # miss rate for demand accesses -system.l2c.demand_misses::0 126796 # number of demand (read+write) misses -system.l2c.demand_misses::1 22 # number of demand (read+write) misses -system.l2c.demand_misses::total 126818 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses +system.l2c.demand_misses::0 127076 # number of demand (read+write) misses +system.l2c.demand_misses::1 24 # number of demand (read+write) misses +system.l2c.demand_misses::total 127100 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -358,28 +358,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.072867 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.479441 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4775.385687 # Average occupied blocks per context -system.l2c.occ_blocks::1 31420.668700 # Average occupied blocks per context -system.l2c.overall_accesses::0 835238 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6745 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 841983 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context +system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context +system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 708442 # number of overall hits -system.l2c.overall_hits::1 6723 # number of overall hits -system.l2c.overall_hits::total 715165 # number of overall hits +system.l2c.overall_hits::0 708536 # number of overall hits +system.l2c.overall_hits::1 6049 # number of overall hits +system.l2c.overall_hits::total 714585 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.151808 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003262 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.155070 # miss rate for overall accesses -system.l2c.overall_misses::0 126796 # number of overall misses -system.l2c.overall_misses::1 22 # number of overall misses -system.l2c.overall_misses::total 126818 # number of overall misses +system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses +system.l2c.overall_misses::0 127076 # number of overall misses +system.l2c.overall_misses::1 24 # number of overall misses +system.l2c.overall_misses::total 127100 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -388,12 +388,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94668 # number of replacements -system.l2c.sampled_refs 125475 # Sample count of references to valid blocks. +system.l2c.replacements 95922 # number of replacements +system.l2c.sampled_refs 125830 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36196.054387 # Cycle average of tags in use -system.l2c.total_refs 863443 # Total number of references to valid blocks. +system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use +system.l2c.total_refs 866394 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 88928 # number of writebacks +system.l2c.writebacks 90126 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status index 82440bd4a..586cb6b73 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status @@ -1 +1 @@ -build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic passed. +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal Binary files differindex afc1a18fe..14d51f6d3 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index a4062b9b2..b338978a2 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -175,7 +175,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.clcd_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.kmi0_fake.pio system.realview.kmi1_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -279,7 +279,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd_fake dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0_fake kmi1_fake l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -291,17 +291,22 @@ pio_addr=268451840 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[18] +pio=system.iobus.port[20] -[system.realview.clcd_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=41667 +gic=system.realview.gic +int_num=55 +max_backoff_delay=10000000 +min_backoff_delay=4000 pio_addr=268566528 -pio_latency=1000 +pio_latency=10000 platform=system.realview system=system -pio=system.iobus.port[10] +dma=system.iobus.port[25] +pio=system.iobus.port[5] [system.realview.dmac_fake] type=AmbaFake @@ -311,7 +316,7 @@ pio_addr=268632064 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[5] +pio=system.iobus.port[8] [system.realview.flash_fake] type=IsaFake @@ -348,7 +353,7 @@ pio_addr=268513280 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[13] +pio=system.iobus.port[15] [system.realview.gpio1_fake] type=AmbaFake @@ -358,7 +363,7 @@ pio_addr=268517376 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[14] +pio=system.iobus.port[16] [system.realview.gpio2_fake] type=AmbaFake @@ -368,27 +373,31 @@ pio_addr=268521472 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[15] +pio=system.iobus.port[17] -[system.realview.kmi0_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=100000 +int_num=52 pio_addr=268460032 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[20] +pio=system.iobus.port[6] -[system.realview.kmi1_fake] -type=AmbaFake -amba_id=0 -ignore_access=false +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +gic=system.realview.gic +int_delay=100000 +int_num=53 pio_addr=268464128 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[21] +pio=system.iobus.port[7] [system.realview.l2x0_fake] type=IsaFake @@ -414,7 +423,7 @@ pio_addr=268455936 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[19] +pio=system.iobus.port[21] [system.realview.realview_io] type=RealViewCtrl @@ -443,7 +452,7 @@ pio_addr=268492800 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[17] +pio=system.iobus.port[19] [system.realview.smc_fake] type=AmbaFake @@ -453,7 +462,7 @@ pio_addr=269357056 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[9] +pio=system.iobus.port[12] [system.realview.sp810_fake] type=AmbaFake @@ -463,7 +472,7 @@ pio_addr=268439552 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[11] +pio=system.iobus.port[13] [system.realview.ssp_fake] type=AmbaFake @@ -473,7 +482,7 @@ pio_addr=268488704 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[16] +pio=system.iobus.port[18] [system.realview.timer0] type=Sp804 @@ -524,7 +533,7 @@ pio_addr=268476416 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[6] +pio=system.iobus.port[9] [system.realview.uart2_fake] type=AmbaFake @@ -534,7 +543,7 @@ pio_addr=268480512 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[7] +pio=system.iobus.port[10] [system.realview.uart3_fake] type=AmbaFake @@ -544,7 +553,7 @@ pio_addr=268484608 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[8] +pio=system.iobus.port[11] [system.realview.watchdog_fake] type=AmbaFake @@ -554,7 +563,7 @@ pio_addr=268500992 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[12] +pio=system.iobus.port[14] [system.terminal] type=Terminal diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 981efa137..715d7a4d1 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 1 2010 22:55:27 -M5 revision 8dd1bd50f739 7724 default qtip tip ext/vfp_serial_nonspec_flags.patch -M5 started Oct 1 2010 23:07:34 -M5 executing on aus-bc3-b7 +M5 compiled Oct 15 2010 11:17:32 +M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip +M5 started Oct 15 2010 11:17:48 +M5 executing on aus-bc3-b4 command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 120048264000 because m5_exit instruction encountered +Exiting @ tick 120261685000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index d35264510..d79fbb100 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 546024 # Simulator instruction rate (inst/s) -host_mem_usage 378800 # Number of bytes of host memory used -host_seconds 92.51 # Real time elapsed on the host -host_tick_rate 1297642212 # Simulator tick rate (ticks/s) +host_inst_rate 571745 # Simulator instruction rate (inst/s) +host_mem_usage 384580 # Number of bytes of host memory used +host_seconds 88.62 # Real time elapsed on the host +host_tick_rate 1356995451 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50513922 # Number of instructions simulated -sim_seconds 0.120048 # Number of seconds simulated -sim_ticks 120048264000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 99871 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 99871 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14859.416446 # average LoadLockedReq miss latency +sim_insts 50669854 # Number of instructions simulated +sim_seconds 0.120262 # Number of seconds simulated +sim_ticks 120261685000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100213 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100213 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15144.474290 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11859.416446 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12144.474290 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 94593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 94593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78428000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052848 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5278 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5278 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 62594000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052848 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95001 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95001 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 78933000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052009 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5212 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5212 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63297000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052009 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5278 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310054500 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7793356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7793356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15742.239268 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7824422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7824422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15793.989050 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.872084 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12793.661656 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7557779 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7557779 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3708509500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030228 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 235577 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 235577 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3001692000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030228 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7587704 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7587704 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3738721500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030254 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236718 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3028490000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030254 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 235577 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43427916500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 99870 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 99870 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 99870 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 99870 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6647889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6647889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40318.665363 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 236718 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43432839000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100212 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100212 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100212 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100212 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6671650 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6671650 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40817.981450 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37318.368117 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37817.693965 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6472950 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6472950 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7053307000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.026315 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 174939 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 174939 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6528438000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.026315 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6499467 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499467 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7028162500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025808 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172183 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172183 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6511564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025808 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 174939 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926045500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172183 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.360003 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.639363 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14441245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14496072 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14441245 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14496072 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26331.273340 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14030729 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14087171 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14030729 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10761816500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028427 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14087171 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10766884000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028208 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408901 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 410516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408901 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9530130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9540054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028208 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 410516 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 408901 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994772 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.323403 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14441245 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.994782 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.328153 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14496072 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14441245 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26215.339962 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14496072 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26331.273340 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23215.002582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14030729 # number of overall hits +system.cpu.dcache.overall_hits::0 14087171 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14030729 # number of overall hits -system.cpu.dcache.overall_miss_latency 10761816500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028427 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14087171 # number of overall hits +system.cpu.dcache.overall_miss_latency 10766884000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028208 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 410516 # number of overall misses +system.cpu.dcache.overall_misses::0 408901 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 410516 # number of overall misses +system.cpu.dcache.overall_misses::total 408901 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9530130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9540054000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028208 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 410516 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 44353962000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 408901 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 44358885500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 413543 # number of replacements -system.cpu.dcache.sampled_refs 414055 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411855 # number of replacements +system.cpu.dcache.sampled_refs 412367 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.323403 # Cycle average of tags in use -system.cpu.dcache.total_refs 14226931 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.328153 # Cycle average of tags in use +system.cpu.dcache.total_refs 14284130 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 384690 # number of writebacks -system.cpu.dtb.accesses 15468820 # DTB accesses +system.cpu.dcache.writebacks 383037 # number of writebacks +system.cpu.dtb.accesses 15524365 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2225 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2228 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15463286 # DTB hits +system.cpu.dtb.hits 15518843 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5534 # DTB misses +system.cpu.dtb.misses 5522 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 764 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8708503 # DTB read accesses -system.cpu.dtb.read_hits 8703948 # DTB read hits -system.cpu.dtb.read_misses 4555 # DTB read misses -system.cpu.dtb.write_accesses 6760317 # DTB write accesses -system.cpu.dtb.write_hits 6759338 # DTB write hits -system.cpu.dtb.write_misses 979 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41422231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41422231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14804.202290 # average ReadReq miss latency +system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8739944 # DTB read accesses +system.cpu.dtb.read_hits 8735402 # DTB read hits +system.cpu.dtb.read_misses 4542 # DTB read misses +system.cpu.dtb.write_accesses 6784421 # DTB write accesses +system.cpu.dtb.write_hits 6783441 # DTB write hits +system.cpu.dtb.write_misses 980 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41542689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41542689 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14799.146758 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11802.928446 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11797.848096 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 40992037 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40992037 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6368679000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010386 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 430194 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430194 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5077549000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41109166 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41109166 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6415770500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010436 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433523 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433523 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5114638500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010436 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 430194 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 433523 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 95.287550 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.826020 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41422231 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41542689 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41422231 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.demand_accesses::total 41542689 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14799.146758 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 40992037 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41109166 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40992037 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6368679000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010386 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41109166 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6415770500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010436 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 430194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433523 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433523 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5077549000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5114638500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010436 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 430194 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 433523 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.948192 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 485.474186 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41422231 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.948287 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 485.522726 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41542689 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41422231 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14804.202290 # average overall miss latency +system.cpu.icache.overall_accesses::total 41542689 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14799.146758 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11802.928446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 40992037 # number of overall hits +system.cpu.icache.overall_hits::0 41109166 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 40992037 # number of overall hits -system.cpu.icache.overall_miss_latency 6368679000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010386 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41109166 # number of overall hits +system.cpu.icache.overall_miss_latency 6415770500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010436 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 430194 # number of overall misses +system.cpu.icache.overall_misses::0 433523 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 430194 # number of overall misses +system.cpu.icache.overall_misses::total 433523 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5077549000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5114638500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010436 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 430194 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 433523 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 429681 # number of replacements -system.cpu.icache.sampled_refs 430193 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433010 # number of replacements +system.cpu.icache.sampled_refs 433522 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 485.474186 # Cycle average of tags in use -system.cpu.icache.total_refs 40992037 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 485.522726 # Cycle average of tags in use +system.cpu.icache.total_refs 41109166 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 30998 # number of writebacks +system.cpu.icache.writebacks 33595 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41425050 # DTB accesses +system.cpu.itb.accesses 41545508 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41422231 # DTB hits -system.cpu.itb.inst_accesses 41425050 # ITB inst accesses -system.cpu.itb.inst_hits 41422231 # ITB inst hits +system.cpu.itb.hits 41542689 # DTB hits +system.cpu.itb.inst_accesses 41545508 # ITB inst accesses +system.cpu.itb.inst_hits 41542689 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,9 +272,9 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 240096528 # number of cpu cycles simulated -system.cpu.num_insts 50513922 # Number of instructions executed -system.cpu.num_refs 16229722 # Number of memory references +system.cpu.numCycles 240523370 # number of cpu cycles simulated +system.cpu.num_insts 50669854 # Number of instructions executed +system.cpu.num_refs 16289326 # Number of memory references system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -343,141 +343,141 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234000000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 173200 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 173200 # number of ReadExReq accesses(hits+misses) +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 170437 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170437 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 65260 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 65260 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5612880000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.623210 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107940 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107940 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4317600000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.623210 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62185 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.635144 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.635144 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107940 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 669099 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 7756 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 676855 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52101.691699 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 26691986.111111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26744087.802810 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 673342 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5664 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 679006 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52102.216096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 26560864.864865 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26612967.080961 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 650656 # number of ReadReq hits -system.l2c.ReadReq_hits::1 7720 # number of ReadReq hits -system.l2c.ReadReq_hits::total 658376 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 960911500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.027564 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.004642 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.032206 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18443 # number of ReadReq misses -system.l2c.ReadReq_misses::1 36 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18479 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 739160000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027618 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.382543 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 2.410160 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18479 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 33151541000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1739 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1739 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 392.794887 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 654480 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5627 # number of ReadReq hits +system.l2c.ReadReq_hits::total 660107 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 982752000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.028013 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.006532 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.034545 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18862 # number of ReadReq misses +system.l2c.ReadReq_misses::1 37 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18899 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 755960000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.336688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.364755 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18899 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 33155867000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1746 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1746 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 721.804511 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.989649 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1721 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1721 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 68840000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.989649 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 1248000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990263 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1729 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1729 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 69160000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990263 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1721 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1729 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 415688 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 415688 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 415688 # number of Writeback hits -system.l2c.Writeback_hits::total 415688 # number of Writeback hits +system.l2c.Writeback_accesses::0 416632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 416632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 416632 # number of Writeback hits +system.l2c.Writeback_hits::total 416632 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.983802 # Average number of references to valid blocks. +system.l2c.avg_refs 6.976763 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 842299 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 7756 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 850055 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52014.839812 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 182605319.444444 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.demand_accesses::0 843779 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5664 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849443 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52015.167487 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 178698810.810811 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 178750825.978298 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 715916 # number of demand (read+write) hits -system.l2c.demand_hits::1 7720 # number of demand (read+write) hits -system.l2c.demand_hits::total 723636 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6573791500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150045 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.004642 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.154687 # miss rate for demand accesses -system.l2c.demand_misses::0 126383 # number of demand (read+write) misses -system.l2c.demand_misses::1 36 # number of demand (read+write) misses -system.l2c.demand_misses::total 126419 # number of demand (read+write) misses +system.l2c.demand_hits::0 716665 # number of demand (read+write) hits +system.l2c.demand_hits::1 5627 # number of demand (read+write) hits +system.l2c.demand_hits::total 722292 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6611856000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.150648 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.006532 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.157181 # miss rate for demand accesses +system.l2c.demand_misses::0 127114 # number of demand (read+write) misses +system.l2c.demand_misses::1 37 # number of demand (read+write) misses +system.l2c.demand_misses::total 127151 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5056760000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 16.299510 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 16.449598 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 126419 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5086040000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.150692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.448976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.599668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 127151 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086001 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.479853 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5636.151787 # Average occupied blocks per context -system.l2c.occ_blocks::1 31447.614519 # Average occupied blocks per context -system.l2c.overall_accesses::0 842299 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 7756 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 850055 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52014.839812 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 182605319.444444 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 182657334.284257 # average overall miss latency +system.l2c.occ_%::0 0.087309 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.478511 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5721.907765 # Average occupied blocks per context +system.l2c.occ_blocks::1 31359.701032 # Average occupied blocks per context +system.l2c.overall_accesses::0 843779 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5664 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849443 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52015.167487 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 178698810.810811 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 178750825.978298 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 715916 # number of overall hits -system.l2c.overall_hits::1 7720 # number of overall hits -system.l2c.overall_hits::total 723636 # number of overall hits -system.l2c.overall_miss_latency 6573791500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150045 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.004642 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.154687 # miss rate for overall accesses -system.l2c.overall_misses::0 126383 # number of overall misses -system.l2c.overall_misses::1 36 # number of overall misses -system.l2c.overall_misses::total 126419 # number of overall misses +system.l2c.overall_hits::0 716665 # number of overall hits +system.l2c.overall_hits::1 5627 # number of overall hits +system.l2c.overall_hits::total 722292 # number of overall hits +system.l2c.overall_miss_latency 6611856000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.150648 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.006532 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.157181 # miss rate for overall accesses +system.l2c.overall_misses::0 127114 # number of overall misses +system.l2c.overall_misses::1 37 # number of overall misses +system.l2c.overall_misses::total 127151 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5056760000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 16.299510 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 16.449598 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 126419 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 33891385000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5086040000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.150692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.448976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.599668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 127151 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 33895711000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 93485 # number of replacements -system.l2c.sampled_refs 125077 # Sample count of references to valid blocks. +system.l2c.replacements 94181 # number of replacements +system.l2c.sampled_refs 125790 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 37083.766306 # Cycle average of tags in use -system.l2c.total_refs 873513 # Total number of references to valid blocks. +system.l2c.tagsinuse 37081.608797 # Cycle average of tags in use +system.l2c.total_refs 877607 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87014 # number of writebacks +system.l2c.writebacks 87612 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex b44fac3a0..19639b6da 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |