stats: Update stats to reflect changes to cache and crossbar

43 files changed, 16126 insertions, 16143 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index f73eb8157..41f61bd3d 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,76 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.869358                       # Number of seconds simulated
-sim_ticks                                1869358498000                       # Number of ticks simulated
-final_tick                               1869358498000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1869357988000                       # Number of ticks simulated
+final_tick                               1869357988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1016587                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1016586                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            29236138105                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314344                       # Number of bytes of host memory used
-host_seconds                                    63.94                       # Real time elapsed on the host
-sim_insts                                    65000470                       # Number of instructions simulated
-sim_ops                                      65000470                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1993950                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1993950                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57344769220                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 333724                       # Number of bytes of host memory used
+host_seconds                                    32.60                       # Real time elapsed on the host
+sim_insts                                    64999904                       # Number of instructions simulated
+sim_ops                                      64999904                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           758272                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         66535616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           105984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           106112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data           766336                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             68167168                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             68167296                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst       758272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       105984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          864256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7836224                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7836224                       # Number of bytes written to this memory
+system.physmem.bytes_inst_read::cpu1.inst       106112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          864384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7836352                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7836352                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.inst             11848                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data           1039619                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1658                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data             11974                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1065112                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122441                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122441                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1065114                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          122443                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               122443                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.inst              405632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            35592753                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            35592763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56764                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.data              409946                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36465540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36465619                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu0.inst         405632                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56695                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             462328                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4191932                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4191932                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4191932                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56764                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             462396                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4192002                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4192002                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4192002                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.inst             405632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           35592753                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           35592763                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56764                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data             409946                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40657473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40657621                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7758839                       # DTB read hits
+system.cpu0.dtb.read_hits                     7758808                       # DTB read hits
 system.cpu0.dtb.read_misses                      7155                       # DTB read misses
 system.cpu0.dtb.read_acv                          152                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  531148                       # DTB read accesses
-system.cpu0.dtb.write_hits                    4740268                       # DTB write hits
+system.cpu0.dtb.write_hits                    4740251                       # DTB write hits
 system.cpu0.dtb.write_misses                      732                       # DTB write misses
 system.cpu0.dtb.write_acv                         102                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 201714                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12499107                       # DTB hits
+system.cpu0.dtb.data_hits                    12499059                       # DTB hits
 system.cpu0.dtb.data_misses                      7887                       # DTB misses
 system.cpu0.dtb.data_acv                          254                       # DTB access violations
 system.cpu0.dtb.data_accesses                  732862                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3525737                       # ITB hits
+system.cpu0.itb.fetch_hits                    3525726                       # ITB hits
 system.cpu0.itb.fetch_misses                     3572                       # ITB misses
 system.cpu0.itb.fetch_acv                         127                       # ITB acv
-system.cpu0.itb.fetch_accesses                3529309                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3529298                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -83,36 +83,36 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3738723791                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3738722771                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6794                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    150436                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    150435                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   51398     40.00%     40.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    243      0.19%     40.18% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    243      0.19%     40.19% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1907      1.48%     41.67% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    514      0.40%     42.07% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  74447     57.93%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              128509                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  74446     57.93%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              128508                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    51050     48.97%     48.97% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     243      0.23%     49.20% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1907      1.83%     51.03% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     514      0.49%     51.52% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   50536     48.48%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               104250                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1853222948500     99.14%     99.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1853222721000     99.14%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::21               20110000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::22               82001000      0.00%     99.14% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               57621500      0.00%     99.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            15975609500      0.85%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1869358290500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            15975327000      0.85%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1869357780500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.993229                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.678818                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.811227                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.678828                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.811234                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.63%      2.63% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.77%     11.40% # number of syscalls executed
 system.cpu0.kern.syscall::4                         2      0.88%     12.28% # number of syscalls executed
@@ -152,7 +152,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.46% # nu
 system.cpu0.kern.callpal::swpctx                 2743      2.02%      2.47% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      39      0.03%      2.50% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.01%      2.51% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               121669     89.51%     92.02% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               121668     89.51%     92.02% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6149      4.52%     96.54% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.54% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.54% # number of callpals executed
@@ -161,44 +161,44 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.55% # nu
 system.cpu0.kern.callpal::rti                    4175      3.07%     99.62% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 369      0.27%     99.89% # number of callpals executed
 system.cpu0.kern.callpal::imb                     146      0.11%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                135930                       # number of callpals executed
+system.cpu0.kern.callpal::total                135929                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             6593                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1174                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1173                      
-system.cpu0.kern.mode_good::user                 1174                      
+system.cpu0.kern.mode_good::kernel               1172                      
+system.cpu0.kern.mode_good::user                 1173                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.177916                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.177764                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.302176                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1868349657500     99.95%     99.95% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1008632000      0.05%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.301957                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1868349152500     99.95%     99.95% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1008627000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    2744                       # number of times the context was actually changed
-system.cpu0.committedInsts                   49478313                       # Number of instructions committed
-system.cpu0.committedOps                     49478313                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             46202260                       # Number of integer alu accesses
+system.cpu0.committedInsts                   49477745                       # Number of instructions committed
+system.cpu0.committedOps                     49477745                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             46201705                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                197598                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1124639                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6043708                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    46202260                       # number of integer instructions
+system.cpu0.num_func_calls                    1124633                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6043603                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    46201705                       # number of integer instructions
 system.cpu0.num_fp_insts                       197598                       # number of float instructions
-system.cpu0.num_int_register_reads           64004164                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          34834852                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           64003225                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          34834421                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads               97440                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes              98967                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12536155                       # number of memory refs
-system.cpu0.num_load_insts                    7783785                       # Number of load instructions
-system.cpu0.num_store_insts                   4752370                       # Number of store instructions
-system.cpu0.num_idle_cycles              3689240240.665401                       # Number of idle cycles
-system.cpu0.num_busy_cycles              49483550.334599                       # Number of busy cycles
+system.cpu0.num_mem_refs                     12536107                       # number of memory refs
+system.cpu0.num_load_insts                    7783754                       # Number of load instructions
+system.cpu0.num_store_insts                   4752353                       # Number of store instructions
+system.cpu0.num_idle_cycles              3689239788.666409                       # Number of idle cycles
+system.cpu0.num_busy_cycles              49482982.333591                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.013235                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.986765                       # Percentage of idle cycles
-system.cpu0.Branches                          7530941                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2589824      5.23%      5.23% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 33436514     67.57%     72.80% # Class of executed instruction
-system.cpu0.op_class::IntMult                   50547      0.10%     72.90% # Class of executed instruction
+system.cpu0.Branches                          7530826                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2589816      5.23%      5.23% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 33436017     67.57%     72.80% # Class of executed instruction
+system.cpu0.op_class::IntMult                   50540      0.10%     72.90% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     72.90% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                  27840      0.06%     72.96% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     72.96% # Class of executed instruction
@@ -226,18 +226,18 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.96% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.96% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.96% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.96% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7945621     16.06%     89.02% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4758309      9.62%     98.63% # Class of executed instruction
-system.cpu0.op_class::IprAccess                675566      1.37%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7945590     16.06%     89.02% # Class of executed instruction
+system.cpu0.op_class::MemWrite                4758292      9.62%     98.63% # Class of executed instruction
+system.cpu0.op_class::IprAccess                675558      1.37%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  49486454                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1781373                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.187448                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10705809                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1781885                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             6.008137                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  49485886                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1781371                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.187328                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10705763                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1781883                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             6.008118                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187448                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.187328                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.988647                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -245,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          446
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51822236                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51822236                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6068914                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6068914                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4360098                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4360098                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       127591                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       127591                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       132845                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       132845                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10429012                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10429012                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10429012                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10429012                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1560067                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1560067                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       236542                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       236542                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12627                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        12627                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         6925                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         6925                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1796609                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1796609                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1796609                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1796609                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7628981                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7628981                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4596640                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4596640                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.tags.tag_accesses         51822042                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51822042                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6068881                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6068881                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4360085                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4360085                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       127592                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       127592                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       132849                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       132849                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10428966                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10428966                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10428966                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10428966                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1560069                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1560069                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       236538                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       236538                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        12626                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        12626                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         6921                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         6921                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1796607                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1796607                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1796607                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1796607                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7628950                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7628950                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4596623                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4596623                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       140218                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       140218                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       139770                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       139770                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12225621                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12225621                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12225621                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12225621                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.204492                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.204492                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051460                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051460                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.090053                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090053                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049546                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.049546                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.146954                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.146954                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.146954                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.146954                       # miss rate for overall accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     12225573                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12225573                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12225573                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12225573                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.204493                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.204493                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051459                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051459                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.090046                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090046                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.049517                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.049517                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.146955                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.146955                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.146955                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.146955                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -303,16 +303,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       632988                       # number of writebacks
-system.cpu0.dcache.writebacks::total           632988                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       633127                       # number of writebacks
+system.cpu0.dcache.writebacks::total           633127                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           618298                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.240646                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           48867509                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           618810                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            78.970135                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           618292                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.240644                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           48866947                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           618804                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            78.969992                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       9786048500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.240646                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.240644                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998517                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998517                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -320,26 +320,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0           63
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         50105399                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        50105399                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     48867509                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       48867509                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     48867509                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        48867509                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     48867509                       # number of overall hits
-system.cpu0.icache.overall_hits::total       48867509                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       618945                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       618945                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       618945                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        618945                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       618945                       # number of overall misses
-system.cpu0.icache.overall_misses::total       618945                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     49486454                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     49486454                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     49486454                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     49486454                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     49486454                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     49486454                       # number of overall (read+write) accesses
+system.cpu0.icache.tags.tag_accesses         50104825                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        50104825                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     48866947                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       48866947                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     48866947                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        48866947                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     48866947                       # number of overall hits
+system.cpu0.icache.overall_hits::total       48866947                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       618939                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       618939                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       618939                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        618939                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       618939                       # number of overall misses
+system.cpu0.icache.overall_misses::total       618939                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     49485886                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     49485886                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     49485886                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     49485886                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     49485886                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     49485886                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012507                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.012507                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012507                       # miss rate for demand accesses
@@ -354,14 +354,14 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       618298                       # number of writebacks
-system.cpu0.icache.writebacks::total           618298                       # number of writebacks
+system.cpu0.icache.writebacks::writebacks       618292                       # number of writebacks
+system.cpu0.icache.writebacks::total           618292                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2831558                       # DTB read hits
+system.cpu1.dtb.read_hits                     2831559                       # DTB read hits
 system.cpu1.dtb.read_misses                      3191                       # DTB read misses
 system.cpu1.dtb.read_acv                           58                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  198160                       # DTB read accesses
@@ -369,7 +369,7 @@ system.cpu1.dtb.write_hits                    2101673                       # DT
 system.cpu1.dtb.write_misses                      412                       # DTB write misses
 system.cpu1.dtb.write_acv                          55                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  90619                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4933231                       # DTB hits
+system.cpu1.dtb.data_hits                     4933232                       # DTB hits
 system.cpu1.dtb.data_misses                      3603                       # DTB misses
 system.cpu1.dtb.data_acv                          113                       # DTB access violations
 system.cpu1.dtb.data_accesses                  288779                       # DTB accesses
@@ -389,7 +389,7 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3738297607                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3738296587                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
@@ -405,11 +405,11 @@ system.cpu1.kern.ipl_good::22                    1906      2.99%     51.49% # nu
 system.cpu1.kern.ipl_good::30                     616      0.97%     52.46% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   30319     47.54%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                63776                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1856124001500     99.30%     99.30% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1856123490500     99.30%     99.30% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::22               81958000      0.00%     99.31% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks::30               70736500      0.00%     99.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            12870742500      0.69%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1869147438500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            12870743500      0.69%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1869146928500                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.967808                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -461,32 +461,32 @@ system.cpu1.kern.mode_switch_good::kernel     0.434066                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.177356                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.358625                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        5986367000      0.32%      0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        5986368000      0.32%      0.32% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user           456602000      0.02%      0.34% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1862102855500     99.66%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1862102404500     99.66%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2507                       # number of times the context was actually changed
-system.cpu1.committedInsts                   15522157                       # Number of instructions committed
-system.cpu1.committedOps                     15522157                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             14295542                       # Number of integer alu accesses
+system.cpu1.committedInsts                   15522159                       # Number of instructions committed
+system.cpu1.committedOps                     15522159                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             14295544                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                198941                       # Number of float alu accesses
 system.cpu1.num_func_calls                     493140                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1540067                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    14295542                       # number of integer instructions
+system.cpu1.num_conditional_control_insts      1540068                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    14295544                       # number of integer instructions
 system.cpu1.num_fp_insts                       198941                       # number of float instructions
-system.cpu1.num_int_register_reads           19514287                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          10457599                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           19514289                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          10457600                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads              101734                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes             104129                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4961785                       # number of memory refs
-system.cpu1.num_load_insts                    2849089                       # Number of load instructions
+system.cpu1.num_mem_refs                      4961786                       # number of memory refs
+system.cpu1.num_load_insts                    2849090                       # Number of load instructions
 system.cpu1.num_store_insts                   2112696                       # Number of store instructions
-system.cpu1.num_idle_cycles              3722774671.474094                       # Number of idle cycles
-system.cpu1.num_busy_cycles              15522935.525906                       # Number of busy cycles
+system.cpu1.num_idle_cycles              3722773649.474793                       # Number of idle cycles
+system.cpu1.num_busy_cycles              15522937.525207                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.004152                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.995848                       # Percentage of idle cycles
-system.cpu1.Branches                          2214162                       # Number of branches fetched
+system.cpu1.Branches                          2214163                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass               856043      5.51%      5.51% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  9156765     58.98%     64.49% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  9156766     58.98%     64.49% # Class of executed instruction
 system.cpu1.op_class::IntMult                   25065      0.16%     64.65% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     64.65% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                  12426      0.08%     64.73% # Class of executed instruction
@@ -515,68 +515,68 @@ system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.74% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.74% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.74% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.74% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2937015     18.92%     83.66% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2937016     18.92%     83.66% # Class of executed instruction
 system.cpu1.op_class::MemWrite                2113897     13.62%     97.27% # Class of executed instruction
 system.cpu1.op_class::IprAccess                423253      2.73%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  15525873                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           201756                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          497.613037                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4718402                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           202064                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.351027                       # Average number of references to valid blocks.
+system.cpu1.op_class::total                  15525875                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           201757                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          497.601960                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4718401                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           202065                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.350907                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle      15869420000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.613037                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971900                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.971900                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   497.601960                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.971879                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.971879                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.601562                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         20020602                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        20020602                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2632689                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2632689                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1954642                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1954642                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        61099                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        61099                       # number of LoadLockedReq hits
+system.cpu1.dcache.tags.tag_accesses         20020608                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        20020608                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2632688                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2632688                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1954643                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1954643                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        61098                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        61098                       # number of LoadLockedReq hits
 system.cpu1.dcache.StoreCondReq_hits::cpu1.data        64210                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        64210                       # number of StoreCondReq hits
 system.cpu1.dcache.demand_hits::cpu1.data      4587331                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total         4587331                       # number of demand (read+write) hits
 system.cpu1.dcache.overall_hits::cpu1.data      4587331                       # number of overall hits
 system.cpu1.dcache.overall_hits::total        4587331                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       140883                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       140883                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        78318                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        78318                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        10999                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        10999                       # number of LoadLockedReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data       140885                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       140885                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        78317                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        78317                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11000                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11000                       # number of LoadLockedReq misses
 system.cpu1.dcache.StoreCondReq_misses::cpu1.data         7305                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total         7305                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       219201                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        219201                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       219201                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       219201                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2773572                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2773572                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.demand_misses::cpu1.data       219202                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        219202                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       219202                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       219202                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2773573                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2773573                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data      2032960                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      2032960                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        72098                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        72098                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        71515                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        71515                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4806532                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4806532                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4806532                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4806532                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data      4806533                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4806533                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4806533                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4806533                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050795                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.050795                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.038524                       # miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::total     0.038524                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152556                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152556                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152570                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.152570                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.102146                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::total     0.102146                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.045605                       # miss rate for demand accesses
@@ -591,48 +591,48 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       144531                       # number of writebacks
-system.cpu1.dcache.writebacks::total           144531                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       144536                       # number of writebacks
+system.cpu1.dcache.writebacks::total           144536                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           380671                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          453.133725                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           15144661                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           381183                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.730683                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1859779767500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133725                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.replacements           380647                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          453.133719                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           15144687                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           381159                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.733253                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1859777157500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   453.133719                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.885027                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.885027                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         15907085                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        15907085                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     15144661                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       15144661                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     15144661                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        15144661                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     15144661                       # number of overall hits
-system.cpu1.icache.overall_hits::total       15144661                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       381212                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       381212                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       381212                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        381212                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       381212                       # number of overall misses
-system.cpu1.icache.overall_misses::total       381212                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     15525873                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     15525873                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     15525873                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     15525873                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     15525873                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     15525873                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024553                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024553                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024553                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024553                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024553                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024553                       # miss rate for overall accesses
+system.cpu1.icache.tags.tag_accesses         15907063                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        15907063                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     15144687                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       15144687                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     15144687                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        15144687                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     15144687                       # number of overall hits
+system.cpu1.icache.overall_hits::total       15144687                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       381188                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       381188                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       381188                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        381188                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       381188                       # number of overall misses
+system.cpu1.icache.overall_misses::total       381188                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     15525875                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     15525875                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     15525875                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     15525875                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     15525875                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     15525875                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024552                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024552                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024552                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024552                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024552                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024552                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -641,8 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       380671                       # number of writebacks
-system.cpu1.icache.writebacks::total           380671                       # number of writebacks
+system.cpu1.icache.writebacks::writebacks       380647                       # number of writebacks
+system.cpu1.icache.writebacks::total           380647                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -687,12 +687,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      26616
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2747818                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.434101                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.434096                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1685787163517                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.434101                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::tsunami.ide     0.434096                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.027131                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.027131                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -735,140 +735,140 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   999918                       # number of replacements
-system.l2c.tags.tagsinuse                65320.982415                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4249962                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1064968                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.990695                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   999922                       # number of replacements
+system.l2c.tags.tagsinuse                65337.856722                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4259784                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1064972                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.999902                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55992.770808                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4860.291584                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4178.146657                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      175.172078                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      114.601288                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.854382                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   55997.404251                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4860.296117                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4190.275222                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      175.171528                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      114.709605                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.854453                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.074162                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.063753                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.063939                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.inst       0.002673                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001749                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996719                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.001750                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.996977                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65050                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          768                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1         3271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6123                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5943                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48945                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6047                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5933                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        49031                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.992584                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 46365909                       # Number of tag accesses
-system.l2c.tags.data_accesses                46365909                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       777519                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          777519                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       719211                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          719211                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             116                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             577                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 693                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            13                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                50                       # number of SCUpgradeReq hits
+system.l2c.tags.tag_accesses                 46377222                       # Number of tag accesses
+system.l2c.tags.data_accesses                46377222                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       777663                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          777663                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       721478                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          721478                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data             130                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             604                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 734                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            44                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                72                       # number of SCUpgradeReq hits
 system.l2c.ReadExReq_hits::cpu0.data           111475                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            56603                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               168078                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        607076                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        379556                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            986632                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       626681                       # number of ReadSharedReq hits
+system.l2c.ReadExReq_hits::cpu1.data            56605                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               168080                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        607070                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        379530                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            986600                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       626719                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data       129011                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           755692                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              607076                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              738156                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              379556                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              185614                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1910402                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             607076                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             738156                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             379556                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             185614                       # number of overall hits
-system.l2c.overall_hits::total                1910402                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          3006                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2174                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              5180                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         1175                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1110                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2285                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113874                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          11069                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             124943                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_hits::total           755730                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              607070                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              738194                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              379530                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              185616                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1910410                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             607070                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             738194                       # number of overall hits
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+system.l2c.overall_hits::cpu1.data             185616                       # number of overall hits
+system.l2c.overall_hits::total                1910410                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          2989                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          2147                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              5136                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data         1165                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total            2260                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113871                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          11066                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124937                       # number of ReadExReq misses
 system.l2c.ReadCleanReq_misses::cpu0.inst        11848                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1656                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           13504                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         1658                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           13506                       # number of ReadCleanReq misses
 system.l2c.ReadSharedReq_misses::cpu0.data       926615                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu1.data         1035                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::total         927650                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.inst             11848                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data           1040489                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1656                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             12104                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1066097                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data           1040486                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1658                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             12101                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1066093                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.inst            11848                       # number of overall misses
-system.l2c.overall_misses::cpu0.data          1040489                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1656                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            12104                       # number of overall misses
-system.l2c.overall_misses::total              1066097                       # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks       777519                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       777519                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       719211                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       719211                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3122                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_misses::cpu0.data          1040486                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1658                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            12101                       # number of overall misses
+system.l2c.overall_misses::total              1066093                       # number of overall misses
+system.l2c.WritebackDirty_accesses::writebacks       777663                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       777663                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks       721478                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total       721478                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3119                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         2751                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5873                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         1212                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5870                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1209                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data         1123                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          2335                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       225349                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        67672                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           293021                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       618924                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       381212                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1000136                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      1553296                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          2332                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       225346                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        67671                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           293017                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       618918                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       381188                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1000106                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      1553334                       # number of ReadSharedReq accesses(hits+misses)
 system.l2c.ReadSharedReq_accesses::cpu1.data       130046                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1683342                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          618924                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1778645                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          381212                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          197718                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2976499                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         618924                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1778645                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         381212                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         197718                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2976499                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.962844                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.790258                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.882002                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.969472                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.988424                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.978587                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.505323                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.163568                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.426396                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_accesses::total      1683380                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          618918                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1778680                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          381188                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          197717                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2976503                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         618918                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1778680                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         381188                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         197717                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2976503                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.958320                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780443                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.874957                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.963606                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.975067                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.969125                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.505316                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.163526                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.426381                       # miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.019143                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004344                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.013502                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.596548                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004350                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.013505                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.596533                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.007959                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.551076                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.551064                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.019143                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.584990                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004344                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.061219                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.358171                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.584976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004350                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.061204                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.358170                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.019143                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.584990                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004344                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.061219                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.358171                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.584976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004350                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.061204                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.358170                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -877,91 +877,91 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               80921                       # number of writebacks
-system.l2c.writebacks::total                    80921                       # number of writebacks
+system.l2c.writebacks::writebacks               80923                       # number of writebacks
+system.l2c.writebacks::total                    80923                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7449                       # Transaction distribution
-system.membus.trans_dist::ReadResp             948782                       # Transaction distribution
+system.membus.trans_dist::ReadResp             948784                       # Transaction distribution
 system.membus.trans_dist::WriteReq              14588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             14588                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       122441                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           917844                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            19642                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          14180                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            8186                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            126447                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       122443                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           918012                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            19594                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          14154                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            8111                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            125245                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           124222                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        941333                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        941335                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        44074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3173737                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3217811                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124995                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3342806                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3172394                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3216468                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125161                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       125161                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3341629                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        86162                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73363008                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     73449170                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     73363264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     73449426                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2668736                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2668736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                76117906                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                76118162                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2205642                       # Request fanout histogram
+system.membus.snoop_fanout::samples           2204372                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2205642    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2204372    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2205642                       # Request fanout histogram
-system.toL2Bus.snoop_filter.tot_requests      6035921                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      3018741                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       376832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total             2204372                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests      6035855                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      3018704                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       374458                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops           1611                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops         1521                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           90                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq               7449                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2732182                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2732156                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             14588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            14588                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       777519                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       719211                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1143412                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           19614                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         14230                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          33844                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295246                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295246                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1000157                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1724576                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1705094                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5410979                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1014431                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       661358                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8791862                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     69513536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155758011                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     40526016                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23357975                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              289155538                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1083512                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          7141306                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.106198                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.308338                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty       777663                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       998939                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1205465                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           19613                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         14226                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          33839                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295242                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295242                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1000127                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1724580                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1856170                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5450139                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1143023                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       684385                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               9133717                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     79182784                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    155766779                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     48757440                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23358423                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              307065426                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1083516                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          7141244                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.105534                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.307488                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                6383457     89.39%     89.39% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 757309     10.60%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                6388144     89.45%     89.45% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 752560     10.54%     99.99% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                    538      0.01%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7141306                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            7141244                       # Request fanout histogram
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index be6733354..25be00c51 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,51 +1,51 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332273500                       # Number of ticks simulated
-final_tick                               1829332273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1829331993500                       # Number of ticks simulated
+final_tick                               1829331993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 996309                       # Simulator instruction rate (inst/s)
-host_op_rate                                   996308                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            30356892493                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311076                       # Number of bytes of host memory used
-host_seconds                                    60.26                       # Real time elapsed on the host
-sim_insts                                    60038341                       # Number of instructions simulated
-sim_ops                                      60038341                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1828258                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1828257                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            55705727715                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 331420                       # Number of bytes of host memory used
+host_seconds                                    32.84                       # Real time elapsed on the host
+sim_insts                                    60038469                       # Number of instructions simulated
+sim_ops                                      60038469                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66835456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          66835072                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             67686912                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             67686528                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       850496                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          850496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7416128                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7416128                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7415744                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7415744                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst              13289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044304                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1044298                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1057608                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115877                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115877                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1057602                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115871                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115871                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               464922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36535438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36535234                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                37000884                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37000680                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          464922                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             464922                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4054008                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4054008                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4054008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4053799                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4053799                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4053799                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              464922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36535438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36535234                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41054893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41054479                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710422                       # DTB read hits
+system.cpu.dtb.read_hits                      9710423                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
@@ -53,14 +53,14 @@ system.cpu.dtb.write_hits                     6352496                       # DT
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062918                       # DTB hits
+system.cpu.dtb.data_hits                     16062919                       # DTB hits
 system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974648                       # ITB hits
+system.cpu.itb.fetch_hits                     4974637                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -73,32 +73,32 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3658670905                       # number of cpu cycles simulated
+system.cpu.numCycles                       3658670345                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105623     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182562                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
 system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811929473000     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1811929127500     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17302245000      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829332066000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1829331786000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -137,7 +137,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
@@ -146,43 +146,43 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192180                       # number of callpals executed
+system.cpu.kern.callpal::total                 192179                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26833319500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801033671500     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801033399500     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
-system.cpu.committedInsts                    60038341                       # Number of instructions committed
-system.cpu.committedOps                      60038341                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913563                       # Number of integer alu accesses
+system.cpu.committedInsts                    60038469                       # Number of instructions committed
+system.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              55913692                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
 system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110761                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913563                       # number of integer instructions
+system.cpu.num_conditional_control_insts      7110791                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     55913692                       # number of integer instructions
 system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76954014                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740254                       # number of times the integer registers were written
+system.cpu.num_int_register_reads            76954245                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41740352                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115702                       # number of memory refs
-system.cpu.num_load_insts                     9747508                       # Number of load instructions
+system.cpu.num_mem_refs                      16115703                       # number of memory refs
+system.cpu.num_load_insts                     9747509                       # Number of load instructions
 system.cpu.num_store_insts                    6368194                       # Number of store instructions
-system.cpu.num_idle_cycles               3598621691.055137                       # Number of idle cycles
-system.cpu.num_busy_cycles               60049213.944863                       # Number of busy cycles
+system.cpu.num_idle_cycles               3598621002.088897                       # Number of idle cycles
+system.cpu.num_busy_cycles               60049342.911103                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
-system.cpu.Branches                           9064400                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3199098      5.33%      5.33% # Class of executed instruction
-system.cpu.op_class::IntAlu                  39448273     65.69%     71.02% # Class of executed instruction
+system.cpu.Branches                           9064428                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3199100      5.33%      5.33% # Class of executed instruction
+system.cpu.op_class::IntAlu                  39448406     65.69%     71.02% # Class of executed instruction
 system.cpu.op_class::IntMult                    60677      0.10%     71.12% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
 system.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
@@ -211,16 +211,16 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
-system.cpu.op_class::MemRead                  9975076     16.61%     87.80% # Class of executed instruction
+system.cpu.op_class::MemRead                  9975077     16.61%     87.80% # Class of executed instruction
 system.cpu.op_class::MemWrite                 6374115     10.61%     98.42% # Class of executed instruction
-system.cpu.op_class::IprAccess                 951217      1.58%    100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   60050179                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           2042728                       # number of replacements
+system.cpu.op_class::total                   60050307                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           2042707                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14038398                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2043240                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              6.870655                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            14038420                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2043219                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.870737                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
@@ -230,52 +230,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          443
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          66369797                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         66369797                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7807758                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807758                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848202                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848202                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          66369780                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         66369780                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7807771                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807771                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848210                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848210                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655960                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655960                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655960                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655960                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721724                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721724                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304370                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304370                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17163                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17163                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026094                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026094                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026094                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026094                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529482                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      13655981                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655981                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13655981                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655981                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721712                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721712                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304362                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682054                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682054                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682054                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682054                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180673                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180673                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085685                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085685                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129198                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129198                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129198                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129198                       # miss rate for overall accesses
+system.cpu.dcache.demand_accesses::cpu.data     15682055                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682055                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682055                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682055                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -284,16 +284,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833492                       # number of writebacks
-system.cpu.dcache.writebacks::total            833492                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       833475                       # number of writebacks
+system.cpu.dcache.writebacks::total            833475                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            919605                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.215260                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            59129947                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            920117                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             64.263509                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            919603                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            59130077                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            920115                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             64.263790                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.215260                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -301,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           63
 system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60970411                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60970411                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     59129947                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59129947                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59129947                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59129947                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59129947                       # number of overall hits
-system.cpu.icache.overall_hits::total        59129947                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920232                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920232                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920232                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920232                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920232                       # number of overall misses
-system.cpu.icache.overall_misses::total        920232                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050179                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050179                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050179                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050179                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050179                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050179                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          60970537                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60970537                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     59130077                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59130077                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59130077                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59130077                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59130077                       # number of overall hits
+system.cpu.icache.overall_hits::total        59130077                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       920230                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920230                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       920230                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920230                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       920230                       # number of overall misses
+system.cpu.icache.overall_misses::total        920230                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60050307                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60050307                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60050307                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
@@ -335,18 +335,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       919605                       # number of writebacks
-system.cpu.icache.writebacks::total            919605                       # number of writebacks
+system.cpu.icache.writebacks::writebacks       919603                       # number of writebacks
+system.cpu.icache.writebacks::total            919603                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           992425                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65424.374115                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4560164                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1057588                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.311853                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           992419                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65424.374401                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4560132                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1057582                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.311847                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4843.320500                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4249.498040                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4843.327000                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4249.506195                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.859551                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073903                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.064842                       # Average percentage of cache occupancy
@@ -355,75 +355,75 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          781                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3260                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4024                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3053                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54045                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54052                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         48754034                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        48754034                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       833492                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       833492                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       919353                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       919353                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         48753652                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        48753652                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       833475                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       833475                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       919351                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       919351                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187288                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187288                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       906925                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811243                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       811243                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       906925                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       998531                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1905456                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       906925                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       998531                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1905456                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187286                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187286                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906923                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       906923                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       811230                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       811230                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       906923                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998516                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1905439                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       906923                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998516                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1905439                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       117066                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       117066                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       117060                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       117060                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13289                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total        13289                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data       927644                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total       927644                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst        13289                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1044710                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1057999                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1044704                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1057993                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        13289                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1044710                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1057999                       # number of overall misses
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       833492                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       833492                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       919353                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       919353                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1044704                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1057993                       # number of overall misses
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       833475                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       833475                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       919351                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       919351                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304354                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304354                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       920214                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738887                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1738887                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       920214                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2043241                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2963455                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       920214                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2043241                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2963455                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304346                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304346                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920212                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       920212                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738874                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1738874                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       920212                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2963432                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       920212                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2963432                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384638                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.384638                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384628                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384628                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014441                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014441                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533470                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533470                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533474                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533474                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014441                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.511300                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.357015                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.511303                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.357016                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014441                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.511300                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.357015                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.511303                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.357016                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -432,46 +432,46 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        74365                       # number of writebacks
-system.cpu.l2cache.writebacks::total            74365                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74359                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5925822                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962455                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5925776                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2962432                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1834                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1449                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2666303                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2666288                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       833492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       919353                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1207667                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       833475                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       919603                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      1209232                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       920232                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738887                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2759817                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6161717                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8921534                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117733440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184157038                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          301890478                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1075994                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      7018681                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       304346                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304346                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       920230                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1738874                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760063                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163223                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8923286                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154606                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          301903918                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1075988                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      7018629                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000744                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.027269                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            7013458     99.93%     99.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            7013406     99.93%     99.93% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               5223      0.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        7018681                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        7018629                       # Request fanout histogram
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -515,12 +515,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      26616
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                41686                       # number of replacements
-system.iocache.tags.tagsinuse                1.225572                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.225569                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         1685780587017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.225572                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::tsunami.ide     1.225569                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -567,39 +567,39 @@ system.membus.trans_dist::ReadReq                7184                       # Tr
 system.membus.trans_dist::ReadResp             948291                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9838                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9838                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       115877                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           917027                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       115871                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           917188                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              147                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             147                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116931                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116931                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116925                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116925                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq        941107                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3107401                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3141445                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124977                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124977                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3266422                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3107383                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3141427                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125138                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       125138                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3266565                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72462656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72508782                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72461888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     72508014                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2667904                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2667904                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                75176686                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                75175918                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2149824                       # Request fanout histogram
+system.membus.snoop_fanout::samples           2149812                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2149824    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2149812    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2149824                       # Request fanout histogram
+system.membus.snoop_fanout::total             2149812                       # Request fanout histogram
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index a1e8c67e3..965d378dd 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,118 +1,118 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.982594                       # Number of seconds simulated
-sim_ticks                                1982594146000                       # Number of ticks simulated
-final_tick                               1982594146000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.982593                       # Number of seconds simulated
+sim_ticks                                1982593132000                       # Number of ticks simulated
+final_tick                               1982593132000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 452083                       # Simulator instruction rate (inst/s)
-host_op_rate                                   452083                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14696000274                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314492                       # Number of bytes of host memory used
-host_seconds                                   134.91                       # Real time elapsed on the host
-sim_insts                                    60989111                       # Number of instructions simulated
-sim_ops                                      60989111                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1109655                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1109654                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36063876778                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 333984                       # Number of bytes of host memory used
+host_seconds                                    54.97                       # Real time elapsed on the host
+sim_insts                                    61002651                       # Number of instructions simulated
+sim_ops                                      61002651                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           800320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24686528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            60096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           523456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           800256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24686464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            59392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           523264                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26071360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       800320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        60096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          860416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7740160                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7740160                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             12505                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            385727                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               939                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8179                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26070336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       800256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        59392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          859648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7739904                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7739904                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             12504                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            385726                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               928                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8176                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                407365                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120940                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120940                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              403673                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12451630                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               30312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              264026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                407349                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          120936                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               120936                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              403641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12451604                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               29957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              263929                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13150125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         403673                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          30312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             433985                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3904057                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3904057                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3904057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             403673                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12451630                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              30312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             264026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13149615                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         403641                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          29957                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433598                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3903930                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3903930                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3903930                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             403641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12451604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              29957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             263929                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17054181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        407365                       # Number of read requests accepted
-system.physmem.writeReqs                       120940                       # Number of write requests accepted
-system.physmem.readBursts                      407365                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     120940                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26063552                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7808                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7739008                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26071360                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7740160                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      122                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17053544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        407349                       # Number of read requests accepted
+system.physmem.writeReqs                       120936                       # Number of write requests accepted
+system.physmem.readBursts                      407349                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     120936                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26062656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7738112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26070336                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7739904                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         310700                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               25226                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               25379                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25426                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24856                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25428                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24855                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               25157                       # Per bank write bursts
 system.physmem.perBankRdBursts::5               25423                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25497                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25344                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25496                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25345                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               25239                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               25589                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25746                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25918                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25733                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25919                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              25947                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              25572                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              25277                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25647                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7851                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25644                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7850                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7778                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7471                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6887                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6886                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7104                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7345                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7441                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7150                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7430                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7151                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7161                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7315                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7729                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8151                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8152                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               8256                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7924                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7541                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7818                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7815                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1982586778500                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1982585764500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  407365                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  407349                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 120940                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 120936                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407149                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        67                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -158,125 +158,112 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5780                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5833                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1879                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7458                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8912                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       66                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       76                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        67594                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      500.082256                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     302.770491                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     404.772373                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16306     24.12%     24.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12315     18.22%     42.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5219      7.72%     50.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3345      4.95%     55.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2482      3.67%     58.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4236      6.27%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1519      2.25%     67.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2145      3.17%     70.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20027     29.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          67594                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5426                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        75.053815                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2863.944316                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5423     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67582                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      500.144536                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     302.732498                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     404.890859                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16271     24.08%     24.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        12393     18.34%     42.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5170      7.65%     50.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3294      4.87%     54.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2518      3.73%     58.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4277      6.33%     64.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1487      2.20%     67.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2102      3.11%     70.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20070     29.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67582                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5413                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        75.229078                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2867.379606                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5410     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5426                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5426                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.285662                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.994987                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.002081                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4792     88.32%     88.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              23      0.42%     88.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              16      0.29%     89.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             184      3.39%     92.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               1      0.02%     92.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              19      0.35%     92.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              45      0.83%     93.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               3      0.06%     93.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               7      0.13%     93.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              30      0.55%     94.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               7      0.13%     94.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.07%     94.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               5      0.09%     94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     94.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              20      0.37%     95.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.48%     95.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              28      0.52%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     96.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.07%     96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           168      3.10%     99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.04%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.04%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.04%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             5      0.09%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             5      0.09%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183            10      0.18%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             3      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5426                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2787487250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10423293500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2036215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6844.78                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5413                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5413                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.336597                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.167195                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.176387                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4808     88.82%     88.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              29      0.54%     89.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              21      0.39%     89.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              46      0.85%     90.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             212      3.92%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              15      0.28%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              14      0.26%     95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              26      0.48%     95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             189      3.49%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               5      0.09%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              5      0.09%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.07%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             5      0.09%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             2      0.04%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             4      0.07%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159             1      0.02%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             1      0.02%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             8      0.15%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             2      0.04%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             3      0.06%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             8      0.15%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-231             2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5413                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2790032750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10425576500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2036145000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6851.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25594.78                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25601.26                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.15                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.90                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.15                       # Average system read bandwidth in MiByte/s
@@ -286,62 +273,62 @@ system.physmem.busUtil                           0.13                       # Da
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363847                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96724                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363813                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96742                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   89.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3752731.43                       # Average gap between requests
+system.physmem.writeRowHitRate                  79.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3752871.58                       # Average gap between requests
 system.physmem.pageHitRate                      87.20                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  243930960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133097250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1578002400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                382494960                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                  244006560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  133138500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1578010200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                382417200                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            72912858435                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1125595195500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1330338686625                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.010578                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1872246434250                       # Time in different power states
+system.physmem_0.actBackEnergy            72939489120                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1125571835250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1330342003950                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.012251                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1872206783000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     66203020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     44140298250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     44179949500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  267079680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  145728000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1598493000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                401079600                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  266913360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  145637250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1598376000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                401066640                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            73974222945                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1124664165750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1330543876095                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.114078                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1870697169250                       # Time in different power states
+system.physmem_1.actBackEnergy            73838725110                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1124783023500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1330526848980                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.105490                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1870895185000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     66203020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     45689549500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     45491533750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7416215                       # DTB read hits
+system.cpu0.dtb.read_hits                     7416541                       # DTB read hits
 system.cpu0.dtb.read_misses                      7442                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  490672                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5004240                       # DTB write hits
+system.cpu0.dtb.write_hits                    5004457                       # DTB write hits
 system.cpu0.dtb.write_misses                      812                       # DTB write misses
 system.cpu0.dtb.write_acv                         134                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 187451                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12420455                       # DTB hits
+system.cpu0.dtb.data_hits                    12420998                       # DTB hits
 system.cpu0.dtb.data_misses                      8254                       # DTB misses
 system.cpu0.dtb.data_acv                          344                       # DTB access violations
 system.cpu0.dtb.data_accesses                  678123                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3482237                       # ITB hits
+system.cpu0.itb.fetch_hits                    3482402                       # ITB hits
 system.cpu0.itb.fetch_misses                     3871                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3486108                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3486273                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -354,36 +341,36 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3964851893                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3964851877                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6804                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    162792                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6803                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    162801                       # number of hwrei instructions executed
 system.cpu0.kern.ipl_count::0                   55926     40.12%     40.12% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.21% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    133      0.10%     40.21% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1977      1.42%     41.63% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    435      0.31%     41.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  80934     58.06%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              139403                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  80941     58.06%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              139412                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    55417     49.07%     49.07% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.12%     49.18% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     133      0.12%     49.18% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1977      1.75%     50.93% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     435      0.39%     51.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   54982     48.68%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               112942                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1904792162000     96.08%     96.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               93245000      0.00%     96.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              790775500      0.04%     96.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              326471500      0.02%     96.14% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            76423262500      3.86%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1982425916500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::31                   54983     48.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               112945                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1904793300500     96.08%     96.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               93813000      0.00%     96.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              790638500      0.04%     96.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              326474000      0.02%     96.15% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            76421682500      3.85%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1982425908500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.990899                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.679344                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810183                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.679297                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810153                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
@@ -422,54 +409,54 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.36% # nu
 system.cpu0.kern.callpal::swpctx                 3024      2.05%      2.41% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               132535     89.80%     92.24% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               132542     89.80%     92.24% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6593      4.47%     96.71% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.71% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.71% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.01%     96.72% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.72% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4324      2.93%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4325      2.93%     99.65% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 381      0.26%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                147594                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6862                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1281                       # number of protection mode switches
+system.cpu0.kern.callpal::total                147602                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6863                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1281                      
-system.cpu0.kern.mode_good::user                 1281                      
+system.cpu0.kern.mode_good::kernel               1282                      
+system.cpu0.kern.mode_good::user                 1282                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.186680                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.186799                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.314626                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1977686351500     99.80%     99.80% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3896829000      0.20%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.314794                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1977682087000     99.80%     99.80% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3901070000      0.20%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3025                       # number of times the context was actually changed
-system.cpu0.committedInsts                   47311851                       # Number of instructions committed
-system.cpu0.committedOps                     47311851                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             43882265                       # Number of integer alu accesses
+system.cpu0.committedInsts                   47316172                       # Number of instructions committed
+system.cpu0.committedOps                     47316172                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             43886449                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                206939                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1185568                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5564719                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    43882265                       # number of integer instructions
+system.cpu0.num_func_calls                    1185652                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5565345                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    43886449                       # number of integer instructions
 system.cpu0.num_fp_insts                       206939                       # number of float instructions
-system.cpu0.num_int_register_reads           60327433                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          32715156                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads           60334275                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          32718467                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads              100516                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes             102286                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12460349                       # number of memory refs
-system.cpu0.num_load_insts                    7443153                       # Number of load instructions
-system.cpu0.num_store_insts                   5017196                       # Number of store instructions
-system.cpu0.num_idle_cycles              3699958327.970898                       # Number of idle cycles
-system.cpu0.num_busy_cycles              264893565.029101                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.066810                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.933190                       # Percentage of idle cycles
-system.cpu0.Branches                          7132898                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              2702955      5.71%      5.71% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 31171442     65.87%     71.59% # Class of executed instruction
-system.cpu0.op_class::IntMult                   51645      0.11%     71.69% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.69% # Class of executed instruction
+system.cpu0.num_mem_refs                     12460893                       # number of memory refs
+system.cpu0.num_load_insts                    7443480                       # Number of load instructions
+system.cpu0.num_store_insts                   5017413                       # Number of store instructions
+system.cpu0.num_idle_cycles              3699956428.707181                       # Number of idle cycles
+system.cpu0.num_busy_cycles              264895448.292820                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.066811                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.933189                       # Percentage of idle cycles
+system.cpu0.Branches                          7133641                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2703037      5.71%      5.71% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 31175022     65.87%     71.59% # Class of executed instruction
+system.cpu0.op_class::IntMult                   51696      0.11%     71.70% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.70% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                  25566      0.05%     71.75% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     71.75% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     71.75% # Class of executed instruction
@@ -496,98 +483,98 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.75% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.75% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.75% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.75% # Class of executed instruction
-system.cpu0.op_class::MemRead                 7616230     16.10%     87.85% # Class of executed instruction
-system.cpu0.op_class::MemWrite                5023298     10.62%     98.46% # Class of executed instruction
-system.cpu0.op_class::IprAccess                727657      1.54%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7616572     16.09%     87.85% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5023515     10.61%     98.46% # Class of executed instruction
+system.cpu0.op_class::IprAccess                727706      1.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  47320449                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1172797                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.333348                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11236424                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1173216                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.577455                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  47324770                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1172753                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.332741                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11237004                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1173173                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.578301                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        144706500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.333348                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986979                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986979                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          419                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.332741                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986978                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986978                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          420                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3          371                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.818359                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         50906675                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        50906675                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6342506                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6342506                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4600881                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4600881                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138108                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       138108                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145430                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       145430                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10943387                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10943387                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10943387                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10943387                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       934212                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       934212                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       249094                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       249094                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13595                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13595                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3          372                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.820312                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         50908772                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        50908772                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6342827                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6342827                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4601104                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4601104                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138127                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       138127                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145435                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       145435                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10943931                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10943931                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10943931                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10943931                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       934208                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       934208                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       249079                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       249079                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13580                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13580                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5739                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total         5739                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1183306                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1183306                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1183306                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1183306                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42884699000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  42884699000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  16803448000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  16803448000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    151690000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    151690000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     97426500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     97426500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  59688147000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  59688147000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  59688147000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  59688147000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7276718                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7276718                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4849975                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4849975                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       151703                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       151703                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       151169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       151169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12126693                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12126693                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12126693                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12126693                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.128384                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.128384                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051360                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051360                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089616                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089616                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037964                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037964                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097579                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.097579                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097579                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.097579                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45904.675812                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 45904.675812                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67458.260737                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 67458.260737                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11157.778595                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11157.778595                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16976.215369                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16976.215369                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50441.852741                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50441.852741                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50441.852741                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50441.852741                       # average overall miss latency
+system.cpu0.dcache.demand_misses::cpu0.data      1183287                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1183287                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1183287                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1183287                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42886334500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  42886334500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  16793569500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  16793569500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    151760500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    151760500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     94775500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     94775500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  59679904000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  59679904000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  59679904000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  59679904000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7277035                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7277035                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4850183                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4850183                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       151707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       151707                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       151174                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       151174                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12127218                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12127218                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12127218                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12127218                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.128378                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.128378                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051355                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051355                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089515                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089515                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037963                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037963                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097573                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.097573                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097573                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097573                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.623043                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.696496                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50435.696496                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -596,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       672822                       # number of writebacks
-system.cpu0.dcache.writebacks::total           672822                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       934212                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       934212                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249094                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249094                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13595                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13595                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       672821                       # number of writebacks
+system.cpu0.dcache.writebacks::total           672821                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       934208                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       934208                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249079                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249079                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13580                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13580                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5739                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total         5739                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1183306                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1183306                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1183306                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1183306                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7080                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7080                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10780                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10780                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17860                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17860                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  41950487000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41950487000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  16554354000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  16554354000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    138095000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    138095000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     91687500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     91687500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58504841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  58504841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  58504841000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  58504841000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1566158000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1566158000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2451078500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2451078500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4017236500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4017236500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.128384                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.128384                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051360                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051360                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089616                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089616                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037964                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037964                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097579                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.097579                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097579                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.097579                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44904.675812                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44904.675812                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66458.260737                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66458.260737                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10157.778595                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10157.778595                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15976.215369                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15976.215369                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49441.852741                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49441.852741                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49441.852741                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49441.852741                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221208.757062                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221208.757062                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227372.773655                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227372.773655                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224929.255319                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224929.255319                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1183287                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1183287                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1183287                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1183287                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7086                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7086                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10784                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10784                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17870                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17870                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  41952126500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41952126500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  16544490500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  16544490500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    138180500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    138180500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     89036500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     89036500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58496617000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  58496617000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  58496617000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  58496617000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1567540500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1567540500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2452068500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2452068500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4019609000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4019609000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.128378                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.128378                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051355                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051355                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089515                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089515                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037963                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037963                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097573                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.097573                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097573                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.097573                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           686460                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          506.490701                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           46633355                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           686972                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.882468                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           686592                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          506.490691                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           46637544                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           687104                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.875524                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      58998281500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   506.490701                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   506.490691                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.989240                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.989240                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3          417                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48007543                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48007543                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     46633355                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       46633355                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     46633355                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        46633355                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     46633355                       # number of overall hits
-system.cpu0.icache.overall_hits::total       46633355                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       687094                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       687094                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       687094                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        687094                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       687094                       # number of overall misses
-system.cpu0.icache.overall_misses::total       687094                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10621840000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10621840000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10621840000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10621840000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10621840000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10621840000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     47320449                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47320449                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     47320449                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47320449                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     47320449                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47320449                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014520                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014520                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014520                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014520                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014520                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014520                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15459.078379                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15459.078379                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15459.078379                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15459.078379                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15459.078379                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15459.078379                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         48011996                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48011996                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     46637544                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       46637544                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     46637544                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        46637544                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     46637544                       # number of overall hits
+system.cpu0.icache.overall_hits::total       46637544                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       687226                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       687226                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       687226                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        687226                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       687226                       # number of overall misses
+system.cpu0.icache.overall_misses::total       687226                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10626395500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10626395500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10626395500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10626395500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10626395500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10626395500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     47324770                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     47324770                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     47324770                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     47324770                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     47324770                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     47324770                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014521                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014521                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014521                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014521                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014521                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014521                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15462.737877                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15462.737877                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -724,53 +711,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       686460                       # number of writebacks
-system.cpu0.icache.writebacks::total           686460                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       687094                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       687094                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       687094                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       687094                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       687094                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       687094                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9934746000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9934746000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9934746000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9934746000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9934746000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9934746000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014520                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014520                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014520                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14459.078379                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 14459.078379                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 14459.078379                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       686592                       # number of writebacks
+system.cpu0.icache.writebacks::total           686592                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       687226                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       687226                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       687226                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       687226                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       687226                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       687226                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9939169500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9939169500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9939169500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9939169500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9939169500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9939169500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014521                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014521                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014521                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2510685                       # DTB read hits
+system.cpu1.dtb.read_hits                     2511145                       # DTB read hits
 system.cpu1.dtb.read_misses                      2993                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  239364                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1829711                       # DTB write hits
+system.cpu1.dtb.write_hits                    1829996                       # DTB write hits
 system.cpu1.dtb.write_misses                      342                       # DTB write misses
 system.cpu1.dtb.write_acv                          29                       # DTB write access violations
 system.cpu1.dtb.write_accesses                 105248                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4340396                       # DTB hits
+system.cpu1.dtb.data_hits                     4341141                       # DTB hits
 system.cpu1.dtb.data_misses                      3335                       # DTB misses
 system.cpu1.dtb.data_acv                           29                       # DTB access violations
 system.cpu1.dtb.data_accesses                  344612                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1990327                       # ITB hits
+system.cpu1.itb.fetch_hits                    1990273                       # ITB hits
 system.cpu1.itb.fetch_misses                     1216                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1991543                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1991489                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -783,32 +770,32 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3965188292                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3965186264                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2870                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     81053                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   27549     38.53%     38.53% # number of times we switched to this ipl
+system.cpu1.kern.inst.quiesce                    2869                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     81047                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   27546     38.52%     38.52% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::22                   1971      2.76%     41.28% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::30                    524      0.73%     42.01% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  41464     57.99%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               71508                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    26681     48.22%     48.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_count::31                  41461     57.99%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               71502                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    26678     48.22%     48.22% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::22                    1971      3.56%     51.78% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::30                     524      0.95%     52.73% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   26157     47.27%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                55333                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1912242644500     96.45%     96.45% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              731132000      0.04%     96.49% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              374834500      0.02%     96.51% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            69244798000      3.49%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1982593409000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.968493                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_good::31                   26154     47.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                55327                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1912240588500     96.45%     96.45% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              731240000      0.04%     96.49% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              374509500      0.02%     96.51% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            69246057000      3.49%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1982592395000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.968489                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.630836                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.773802                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.630810                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.773783                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
 system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
@@ -827,10 +814,10 @@ system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu1.kern.callpal::wripir                  435      0.59%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2066      2.79%      3.38% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 2066      2.79%      3.39% # number of callpals executed
 system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                65186     88.12%     91.52% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                65180     88.12%     91.52% # number of callpals executed
 system.cpu1.kern.callpal::rdps                   2261      3.06%     94.57% # number of callpals executed
 system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.57% # number of callpals executed
 system.cpu1.kern.callpal::wrusp                     4      0.01%     94.58% # number of callpals executed
@@ -839,164 +826,164 @@ system.cpu1.kern.callpal::rti                    3826      5.17%     99.76% # nu
 system.cpu1.kern.callpal::callsys                 136      0.18%     99.94% # number of callpals executed
 system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 73976                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2114                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 73970                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2115                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2922                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2921                       # number of protection mode switches
 system.cpu1.kern.mode_good::kernel                912                      
 system.cpu1.kern.mode_good::user                  464                      
 system.cpu1.kern.mode_good::idle                  448                      
-system.cpu1.kern.mode_switch_good::kernel     0.431410                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::kernel     0.431206                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.153320                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::idle      0.153372                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     0.331636                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       19465916000      0.98%      0.98% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1729420000      0.09%      1.07% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1961398071000     98.93%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel       19470103000      0.98%      0.98% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1729907500      0.09%      1.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1961392382500     98.93%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    2067                       # number of times the context was actually changed
-system.cpu1.committedInsts                   13677260                       # Number of instructions committed
-system.cpu1.committedOps                     13677260                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             12615003                       # Number of integer alu accesses
+system.cpu1.committedInsts                   13686479                       # Number of instructions committed
+system.cpu1.committedOps                     13686479                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             12624111                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                178612                       # Number of float alu accesses
-system.cpu1.num_func_calls                     430048                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1358006                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    12615003                       # number of integer instructions
+system.cpu1.num_func_calls                     430158                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1359705                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    12624111                       # number of integer instructions
 system.cpu1.num_fp_insts                       178612                       # number of float instructions
-system.cpu1.num_int_register_reads           17367613                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           9253143                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           17383206                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           9260208                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads               93246                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes              95234                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4364552                       # number of memory refs
-system.cpu1.num_load_insts                    2525340                       # Number of load instructions
-system.cpu1.num_store_insts                   1839212                       # Number of store instructions
-system.cpu1.num_idle_cycles              3912229588.998027                       # Number of idle cycles
-system.cpu1.num_busy_cycles              52958703.001973                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.013356                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.986644                       # Percentage of idle cycles
-system.cpu1.Branches                          1948315                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               733682      5.36%      5.36% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  8093046     59.16%     64.52% # Class of executed instruction
-system.cpu1.op_class::IntMult                   23046      0.17%     64.69% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     64.69% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  14372      0.11%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     64.79% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1986      0.01%     64.81% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.81% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2600021     19.01%     83.81% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1840236     13.45%     97.26% # Class of executed instruction
-system.cpu1.op_class::IprAccess                374235      2.74%    100.00% # Class of executed instruction
+system.cpu1.num_mem_refs                      4365297                       # number of memory refs
+system.cpu1.num_load_insts                    2525800                       # Number of load instructions
+system.cpu1.num_store_insts                   1839497                       # Number of store instructions
+system.cpu1.num_idle_cycles              3912233484.998027                       # Number of idle cycles
+system.cpu1.num_busy_cycles              52952779.001973                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.013354                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.986646                       # Percentage of idle cycles
+system.cpu1.Branches                          1950120                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               733810      5.36%      5.36% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  8101284     59.18%     64.54% # Class of executed instruction
+system.cpu1.op_class::IntMult                   23184      0.17%     64.71% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.71% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  14372      0.10%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1986      0.01%     64.83% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.83% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2600475     19.00%     83.82% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1840521     13.44%     97.27% # Class of executed instruction
+system.cpu1.op_class::IprAccess                374211      2.73%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  13680624                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           173715                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          481.481115                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            4164110                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           174227                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            23.900486                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      90323581500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.481115                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.940393                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.940393                       # Average percentage of cache occupancy
+system.cpu1.op_class::total                  13689843                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           173686                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          481.983606                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4164884                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           174198                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.908908                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      90321767000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.983606                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.941374                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.941374                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         17605365                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        17605365                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2339052                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2339052                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1706902                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1706902                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        50404                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        50404                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        53074                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        53074                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      4045954                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         4045954                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      4045954                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        4045954                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       123499                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       123499                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        65580                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        65580                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9274                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9274                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6110                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         6110                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       189079                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        189079                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       189079                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       189079                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1557395000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1557395000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1879104500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1879104500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     85318500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     85318500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     99555000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     99555000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   3436499500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   3436499500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   3436499500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   3436499500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2462551                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2462551                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1772482                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1772482                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        59678                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        59678                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        59184                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        59184                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4235033                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4235033                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4235033                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4235033                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050151                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.050151                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036999                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.036999                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155401                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155401                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103237                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103237                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044646                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.044646                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044646                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044646                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12610.587940                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12610.587940                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28653.621531                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 28653.621531                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9199.751995                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9199.751995                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16293.780687                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16293.780687                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18174.940104                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18174.940104                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18174.940104                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18174.940104                       # average overall miss latency
+system.cpu1.dcache.tags.tag_accesses         17608316                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        17608316                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2339523                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2339523                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1707175                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1707175                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        50425                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        50425                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        53078                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        53078                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      4046698                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         4046698                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      4046698                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        4046698                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       123485                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       123485                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        65589                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        65589                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9256                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         9256                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6109                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         6109                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       189074                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        189074                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       189074                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       189074                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1555964500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1555964500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1870805000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1870805000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     85075000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     85075000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     96955500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     96955500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   3426769500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   3426769500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   3426769500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   3426769500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2463008                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2463008                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1772764                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1772764                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        59681                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        59681                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        59187                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        59187                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      4235772                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4235772                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4235772                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4235772                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050136                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.050136                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036998                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.036998                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155091                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155091                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103215                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103215                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044637                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.044637                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044637                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044637                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12600.433251                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12600.433251                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28523.151748                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 28523.151748                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9191.335350                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9191.335350                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15870.928139                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15870.928139                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18123.959402                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18123.959402                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18123.959402                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18123.959402                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1005,128 +992,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       119750                       # number of writebacks
-system.cpu1.dcache.writebacks::total           119750                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       123499                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       123499                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65580                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        65580                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9274                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9274                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6110                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         6110                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       189079                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       189079                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       189079                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       189079                       # number of overall MSHR misses
+system.cpu1.dcache.writebacks::writebacks       119736                       # number of writebacks
+system.cpu1.dcache.writebacks::total           119736                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       123485                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       123485                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65589                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        65589                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9256                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9256                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6109                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         6109                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       189074                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       189074                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       189074                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       189074                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          118                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total          118                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3348                       # number of WriteReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3348                       # number of WriteReq MSHR uncacheable
 system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3466                       # number of overall MSHR uncacheable misses
 system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3466                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1433896000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1433896000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1813524500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1813524500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     76044500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     76044500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     93445000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     93445000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3247420500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3247420500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3247420500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3247420500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1432479500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1432479500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1805216000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1805216000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     75819000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     75819000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     90846500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     90846500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3237695500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3237695500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3237695500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3237695500                       # number of overall MSHR miss cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     25051000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     25051000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    789483500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    789483500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    814534500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    814534500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.050151                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.050151                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036999                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036999                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155401                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155401                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103237                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103237                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044646                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.044646                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044646                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.044646                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11610.587940                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11610.587940                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27653.621531                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27653.621531                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8199.751995                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8199.751995                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15293.780687                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15293.780687                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17174.940104                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17174.940104                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17174.940104                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17174.940104                       # average overall mshr miss latency
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    789482000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    789482000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    814533000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    814533000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.050136                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.050136                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036998                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036998                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155091                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155091                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103215                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103215                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044637                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.044637                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044637                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.044637                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8191.335350                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8191.335350                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.497013                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.497013                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235007.068667                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235007.068667                       # average overall mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           331421                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          442.918144                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           13348652                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           331933                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            40.214899                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1976561020500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   442.918144                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.865074                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.865074                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           331505                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          442.932847                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           13357787                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           332017                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.232238                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1975288394500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   442.932847                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.865103                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.865103                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14012598                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14012598                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     13348652                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       13348652                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     13348652                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        13348652                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     13348652                       # number of overall hits
-system.cpu1.icache.overall_hits::total       13348652                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       331973                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       331973                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       331973                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        331973                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       331973                       # number of overall misses
-system.cpu1.icache.overall_misses::total       331973                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4541836000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4541836000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4541836000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4541836000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4541836000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4541836000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13680625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13680625                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13680625                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13680625                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13680625                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13680625                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024266                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024266                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024266                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024266                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024266                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024266                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13681.341555                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13681.341555                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13681.341555                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13681.341555                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13681.341555                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13681.341555                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14021901                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14021901                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     13357787                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       13357787                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     13357787                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        13357787                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     13357787                       # number of overall hits
+system.cpu1.icache.overall_hits::total       13357787                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       332057                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       332057                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       332057                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        332057                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       332057                       # number of overall misses
+system.cpu1.icache.overall_misses::total       332057                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4541544500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4541544500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4541544500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4541544500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4541544500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4541544500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13689844                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13689844                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13689844                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13689844                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13689844                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13689844                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024256                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024256                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024256                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024256                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024256                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024256                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13677.002744                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13677.002744                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1135,32 +1122,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       331421                       # number of writebacks
-system.cpu1.icache.writebacks::total           331421                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       331973                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       331973                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       331973                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       331973                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       331973                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       331973                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4209863000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4209863000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4209863000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4209863000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4209863000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4209863000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024266                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024266                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024266                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.341555                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.341555                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.341555                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       331505                       # number of writebacks
+system.cpu1.icache.writebacks::total           331505                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       332057                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       332057                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       332057                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       332057                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       332057                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       332057                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4209487500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4209487500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4209487500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4209487500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4209487500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4209487500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024256                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024256                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024256                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024256                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1174,37 +1161,37 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55680                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55680                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14048                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7379                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7379                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               55684                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              55684                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14066                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2476                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42652                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42672                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  126106                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56192                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  126126                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56264                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9884                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        82434                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        82507                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2744058                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             15110500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2744131                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             15127500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1214,29 +1201,29 @@ system.iobus.reqLayer6.occupancy                10000                       # La
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy              175000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15842500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15843000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2460000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6039500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6055000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               83000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215050235                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215669663                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28524000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28540000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41695                       # number of replacements
-system.iocache.tags.tagsinuse                0.566864                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.566874                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1775104150000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.566864                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035429                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035429                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1775103309000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.566874                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035430                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035430                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1252,8 +1239,8 @@ system.iocache.overall_misses::tsunami.ide          175                       #
 system.iocache.overall_misses::total              175                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21956883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21956883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5428160352                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5428160352                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5245212780                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5245212780                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21956883                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21956883                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21956883                       # number of overall miss cycles
@@ -1276,17 +1263,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 125467.902857                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130635.356950                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130635.356950                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 125467.902857                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 125467.902857                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            14                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1302,8 +1289,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          175
 system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13206883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13206883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3350560352                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3350560352                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165805993                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3165805993                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     13206883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     13206883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     13206883                       # number of overall MSHR miss cycles
@@ -1318,197 +1305,197 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80635.356950                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80635.356950                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76189.016004                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76189.016004                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   342160                       # number of replacements
-system.l2c.tags.tagsinuse                65166.105156                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3684821                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407166                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.049923                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   342144                       # number of replacements
+system.l2c.tags.tagsinuse                65164.214079                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3686310                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407150                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.053936                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              12928623000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54852.926968                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4798.887710                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5355.521606                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      119.450047                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       39.318825                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.836989                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073225                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.081719                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.001823                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54851.914684                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4798.806705                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5354.570072                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.data       39.330879                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.836974                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.081704                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.data       0.000600                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994356                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.994327                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65006                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          513                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5372                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6320                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52699                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5381                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6294                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52712                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.991913                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 35902652                       # Number of tag accesses
-system.l2c.tags.data_accesses                35902652                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       792572                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          792572                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       746399                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          746399                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             184                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             546                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 730                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            39                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
+system.l2c.tags.tag_accesses                 35907872                       # Number of tag accesses
+system.l2c.tags.data_accesses                35907872                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       792557                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          792557                       # number of WritebackDirty hits
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+system.l2c.WritebackClean_hits::total          746952                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data             186                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_hits::total                 734                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            40                       # number of SCUpgradeReq hits
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 system.l2c.SCUpgradeReq_hits::total                63                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           124130                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            48550                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172680                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        674563                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        331022                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1005585                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       659479                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       113775                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           773254                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              674563                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              783609                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                 1951519                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             674563                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             783609                       # number of overall hits
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-system.l2c.overall_hits::cpu1.data             162325                       # number of overall hits
-system.l2c.overall_hits::total                1951519                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          2975                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1806                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4781                       # number of UpgradeReq misses
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 system.l2c.SCUpgradeReq_misses::cpu0.data          926                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total            1858                       # number of SCUpgradeReq misses
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 system.l2c.ReadExReq_misses::cpu0.data         114977                       # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::total             122857                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        12505                       # number of ReadCleanReq misses
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 system.l2c.ReadSharedReq_misses::cpu1.data          337                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         271876                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             12505                       # number of demand (read+write) misses
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-system.l2c.overall_misses::total               408188                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      3844000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     36525000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     40369000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3483500                       # number of SCUpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::total      4459500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  14619274000                       # number of ReadExReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total  15659763500                       # number of ReadExReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::total   1765537000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  33667193000                       # number of ReadSharedReq miss cycles
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-system.l2c.ReadSharedReq_miss_latency::total  33710461500                       # number of ReadSharedReq miss cycles
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-system.l2c.overall_miss_latency::cpu1.data   1083758000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    51135762000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       792572                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       792572                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       746399                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       746399                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.SCUpgradeReq_accesses::cpu0.data          965                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.overall_accesses::total            2359707                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941754                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.767857                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.867538                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.959585                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.291658                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.002953                       # miss rate for ReadSharedReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1292.100840                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20224.252492                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  8443.631040                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3761.879050                       # average SCUpgradeReq miss latency
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 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1517,8 +1504,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
@@ -1527,238 +1514,237 @@ system.l2c.overall_mshr_hits::cpu1.inst            11                       # nu
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
 system.l2c.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
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 system.l2c.ReadExReq_mshr_misses::cpu0.data       114977                       # number of ReadExReq MSHR misses
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-system.l2c.demand_mshr_miss_latency::cpu0.data  44421307000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    114749500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1001588000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  47052637000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1514992500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  44421307000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    114749500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1001588000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  47052637000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1477620500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses::total        21336                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    204336000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    124703500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    329039500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     63412000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     64097500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    127509500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  13468621000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    958037500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  14426658500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1517585500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    113934001                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1631519501                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  30953725000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     39899000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  30993624000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1517585500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  44422346000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    113934001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    997936500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  47051802001                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1517585500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  44422346000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    113934001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    997936500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  47051802001                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1478927500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23575500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1501196000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2327025500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    750968500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   3077994000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3804646000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    774544000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4579190000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1502503000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2327963000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    750967000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   3078930000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3806890500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    774542500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4581433000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941754                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.867538                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.959585                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.974895                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967205                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.480860                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.139642                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.415708                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013193                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.291658                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002953                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260136                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.330320                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.048182                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.172978                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.330320                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.048182                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.172978                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71657.478992                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71685.769657                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71668.165656                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71322.894168                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71535.407725                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71429.494080                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.551649                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122041.814721                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 117463.339492                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121224.486760                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113986.583879                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118393.175074                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113992.046006                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114927.472601                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121892.174760                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 115275.081644                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114927.472601                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121892.174760                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 115275.081644                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208703.460452                       # average ReadReq mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941102                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767698                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.866957                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.958592                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.975866                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967170                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.480886                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.139579                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.415710                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013178                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.291657                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002954                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260147                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.330323                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.048176                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.172959                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018196                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.330323                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002795                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.048176                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.172959                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 115277.837125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 115277.837125                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208557.377049                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215865.074212                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.614098                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217864.807475                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213026.091825                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223469.128679                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214723.342399                       # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                7198                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292693                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14128                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14128                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       120940                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261948                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            16888                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11786                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            7203                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            123166                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           122293                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        285495                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7204                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292685                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14132                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14132                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       120936                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262098                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            16894                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          11785                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            123162                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           122291                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        285481                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42652                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1193065                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1235717                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124827                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124827                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1360544                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82434                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31153280                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31235714                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42672                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1185820                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1228492                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83437                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83437                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1311929                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82507                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31152000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31234507                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33893954                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            22770                       # Total snoops (count)
-system.membus.snoop_fanout::samples            883282                       # Request fanout histogram
+system.membus.pkt_size::total                33892747                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            22774                       # Total snoops (count)
+system.membus.snoop_fanout::samples            883255                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  883282    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  883255    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              883282                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            40488000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              883255                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40521000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1327709899                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1327609723                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2192713302                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2178253250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69791959                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             898617                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      4790563                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2395444                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       362000                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1241                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1181                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      4790864                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2395593                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       361656                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1242                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1182                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           60                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq               7198                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2107005                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14128                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14128                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       913531                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       746399                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          756600                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           17054                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11849                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          28903                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           297620                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          297620                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1019067                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1080755                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq               7204                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2107176                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14132                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14132                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       913504                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1018097                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          816785                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           17065                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11848                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28913                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           297603                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297603                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1019283                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1080704                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1917007                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3544626                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       867499                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       539645                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               6868777                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     78714432                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118015028                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     34273664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     18604942                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              249608066                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          484792                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2873097                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.137110                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.344206                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2061018                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3585479                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       995618                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       558881                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7200996                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     87922688                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118013949                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     42467904                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     18601358                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              267005899                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          484765                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          2873241                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.136986                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.344076                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2479406     86.30%     86.30% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 393455     13.69%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2479885     86.31%     86.31% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 393120     13.68%     99.99% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                    234      0.01%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2873097                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4223463995                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2873241                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4223821996                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           297883                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1030900979                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1031213250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1802313287                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1802267282                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         499097220                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         499176813                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         293862892                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         293823888                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index bc2bfd41e..04e45bbeb 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,13 +4,13 @@ sim_seconds                                  1.941276                       # Nu
 sim_ticks                                1941275996000                       # Number of ticks simulated
 final_tick                               1941275996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 450874                       # Simulator instruction rate (inst/s)
-host_op_rate                                   450874                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15578984909                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 311244                       # Number of bytes of host memory used
-host_seconds                                   124.61                       # Real time elapsed on the host
-sim_insts                                    56182743                       # Number of instructions simulated
-sim_ops                                      56182743                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1255554                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1255553                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43383023327                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332188                       # Number of bytes of host memory used
+host_seconds                                    44.75                       # Real time elapsed on the host
+sim_insts                                    56182685                       # Number of instructions simulated
+sim_ops                                      56182685                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            844800                       # Number of bytes read from this memory
@@ -51,7 +51,7 @@ system.physmem.bytesReadSys                  25702272                       # To
 system.physmem.bytesWrittenSys                7410752                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                      117                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         303100                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               25225                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               25628                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               25541                       # Per bank write bursts
@@ -85,7 +85,7 @@ system.physmem.perBankWrBursts::13               7822                       # Pe
 system.physmem.perBankWrBursts::14               7863                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7687                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
+system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
 system.physmem.totGap                    1941264122500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
@@ -148,123 +148,112 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5487                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       51                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64945                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      509.715729                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     310.174215                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     406.042967                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15358     23.65%     23.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11454     17.64%     41.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4958      7.63%     48.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3153      4.85%     53.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2453      3.78%     57.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4205      6.47%     64.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1430      2.20%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2063      3.18%     69.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19871     30.60%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64945                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5113                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        78.517700                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2951.127633                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5110     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6734                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6941                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5812                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       34                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64912                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      509.974858                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     310.431433                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     406.117715                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15298     23.57%     23.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11509     17.73%     41.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4967      7.65%     48.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3096      4.77%     53.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2467      3.80%     57.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4201      6.47%     63.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1427      2.20%     66.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2061      3.18%     69.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19886     30.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64912                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5093                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        78.826036                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2956.913485                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5090     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5113                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5113                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.640524                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.158069                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.669047                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4483     87.68%     87.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              26      0.51%     88.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              11      0.22%     88.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             181      3.54%     91.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               5      0.10%     92.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              20      0.39%     92.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              39      0.76%     93.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.12%     93.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              12      0.23%     93.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              31      0.61%     94.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.06%     94.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.06%     94.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               9      0.18%     94.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     94.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              22      0.43%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              27      0.53%     95.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.04%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              26      0.51%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.06%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           161      3.15%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.10%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.04%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.06%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.08%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             4      0.08%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183            11      0.22%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             5      0.10%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5113                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2718840250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10246609000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.rdPerTurnAround::total            5093                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5093                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.729433                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.333640                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.082746                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23            4499     88.34%     88.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              29      0.57%     88.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39              20      0.39%     89.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47              41      0.81%     90.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55             209      4.10%     94.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63              11      0.22%     94.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71              11      0.22%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79              30      0.59%     95.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87             184      3.61%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-95               6      0.12%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              5      0.10%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111             4      0.08%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127             1      0.02%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135             8      0.16%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143             5      0.10%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167             4      0.08%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175             5      0.10%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183             5      0.10%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-191             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-199             2      0.04%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-215             7      0.14%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-247             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-263             4      0.08%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5093                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2720413750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10248182500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2007405000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6772.03                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6775.95                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25522.03                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25525.95                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.82                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.24                       # Average system read bandwidth in MiByte/s
@@ -274,55 +263,55 @@ system.physmem.busUtil                           0.13                       # Da
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.09                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     358828                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93469                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        22.10                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     358846                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93484                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   89.38                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.72                       # Row buffer hit rate for writes
+system.physmem.writeRowHitRate                  80.73                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3752025.30                       # Average gap between requests
 system.physmem.pageHitRate                      87.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  240377760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131158500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  240264360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131096625                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1565912400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                373358160                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            71534855790                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1102015656000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1302656006370                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.030850                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1833021874000                       # Time in different power states
+system.physmem_0.actBackEnergy            71567841690                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1101986721000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1302659881995                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.032847                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1832974788000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     64823460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     43430562250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     43477648250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  250606440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136739625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  250470360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136665375                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1565639400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                376773120                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            72705843270                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1100988474000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1302818763615                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.114691                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1831312114000                       # Time in different power states
+system.physmem_1.actBackEnergy            72629101890                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1101055791000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1302809128905                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.109728                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1831423384000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     64823460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     45140322250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     45029052250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9064657                       # DTB read hits
+system.cpu.dtb.read_hits                      9064642                       # DTB read hits
 system.cpu.dtb.read_misses                      10324                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
-system.cpu.dtb.write_hits                     6356207                       # DTB write hits
+system.cpu.dtb.write_hits                     6356200                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     15420864                       # DTB hits
+system.cpu.dtb.data_hits                     15420842                       # DTB hits
 system.cpu.dtb.data_misses                      11466                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
@@ -358,10 +347,10 @@ system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # nu
 system.cpu.kern.ipl_good::22                     1935      1.30%     50.69% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73545     49.31%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149156                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1860509805500     95.84%     95.84% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                94040000      0.00%     95.84% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               770515500      0.04%     95.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             79900901000      4.12%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1860509936500     95.84%     95.84% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                94066500      0.00%     95.84% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               770529000      0.04%     95.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             79900730000      4.12%    100.00% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::total         1941275262000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -426,32 +415,32 @@ system.cpu.kern.mode_switch_good::kernel     0.323121                       # fr
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081184                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::total      0.391952                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        48611852500      2.50%      2.50% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5602941000      0.29%      2.79% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1887060466500     97.21%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel        48613441500      2.50%      2.50% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5603081000      0.29%      2.79% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1887058737500     97.21%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
-system.cpu.committedInsts                    56182743                       # Number of instructions committed
-system.cpu.committedOps                      56182743                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52054633                       # Number of integer alu accesses
+system.cpu.committedInsts                    56182685                       # Number of instructions committed
+system.cpu.committedOps                      56182685                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52054580                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324393                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483394                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6468678                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52054633                       # number of integer instructions
+system.cpu.num_func_calls                     1483390                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6468674                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52054580                       # number of integer instructions
 system.cpu.num_fp_insts                        324393                       # number of float instructions
-system.cpu.num_int_register_reads            71322499                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38520900                       # number of times the integer registers were written
+system.cpu.num_int_register_reads            71322431                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38520860                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads               163609                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              166486                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15473474                       # number of memory refs
-system.cpu.num_load_insts                     9101503                       # Number of load instructions
-system.cpu.num_store_insts                    6371971                       # Number of store instructions
-system.cpu.num_idle_cycles               3583834697.998154                       # Number of idle cycles
-system.cpu.num_busy_cycles               298717294.001846                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.076938                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.923062                       # Percentage of idle cycles
-system.cpu.Branches                           8422724                       # Number of branches fetched
-system.cpu.op_class::No_OpClass               3200638      5.70%      5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu                  36231019     64.47%     70.17% # Class of executed instruction
+system.cpu.num_mem_refs                      15473452                       # number of memory refs
+system.cpu.num_load_insts                     9101488                       # Number of load instructions
+system.cpu.num_store_insts                    6371964                       # Number of store instructions
+system.cpu.num_idle_cycles               3583831790.000154                       # Number of idle cycles
+system.cpu.num_busy_cycles               298720201.999846                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.076939                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.923061                       # Percentage of idle cycles
+system.cpu.Branches                           8422715                       # Number of branches fetched
+system.cpu.op_class::No_OpClass               3200634      5.70%      5.70% # Class of executed instruction
+system.cpu.op_class::IntAlu                  36230987     64.47%     70.17% # Class of executed instruction
 system.cpu.op_class::IntMult                    61043      0.11%     70.28% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     70.28% # Class of executed instruction
 system.cpu.op_class::FloatAdd                   38085      0.07%     70.35% # Class of executed instruction
@@ -480,16 +469,16 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     70.35% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     70.35% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     70.35% # Class of executed instruction
-system.cpu.op_class::MemRead                  9328633     16.60%     86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite                 6378052     11.35%     98.30% # Class of executed instruction
+system.cpu.op_class::MemRead                  9328618     16.60%     86.95% # Class of executed instruction
+system.cpu.op_class::MemWrite                 6378045     11.35%     98.30% # Class of executed instruction
 system.cpu.op_class::IprAccess                 953470      1.70%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                   56194576                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           1390387                       # number of replacements
+system.cpu.op_class::total                   56194518                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           1390402                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.973391                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14048998                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1390899                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.100660                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            14048961                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1390914                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.100525                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         145150500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.973391                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999948                       # Average percentage of cache occupancy
@@ -499,72 +488,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          187
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63150492                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63150492                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7814415                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7814415                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5852271                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5852271                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183035                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183035                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          63150419                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63150419                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7814383                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7814383                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5852265                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5852265                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183036                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183036                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       199260                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199260                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13666686                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13666686                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13666686                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13666686                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069342                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069342                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304328                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304328                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17247                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17247                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373670                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373670                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  44771016500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  44771016500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  17634519000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  17634519000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232810500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    232810500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  62405535500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  62405535500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  62405535500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  62405535500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8883757                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8883757                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6156599                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6156599                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      13666648                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13666648                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13666648                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13666648                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069359                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069359                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304327                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304327                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17246                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17246                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1373686                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373686                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373686                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373686                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  44772641000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  44772641000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  17635172000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  17635172000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232797500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    232797500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  62407813000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  62407813000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  62407813000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  62407813000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8883742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8883742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6156592                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6156592                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200282                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200282                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       199260                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199260                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15040356                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15040356                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15040356                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15040356                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120370                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120370                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     15040334                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15040334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15040334                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15040334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120373                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120373                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049431                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.049431                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086114                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086114                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091332                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091332                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091332                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091332                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45429.786994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45429.786994                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086109                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086109                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091333                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091333                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091333                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091333                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45430.915799                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45430.915799                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -573,74 +562,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       834936                       # number of writebacks
-system.cpu.dcache.writebacks::total            834936                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069342                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069342                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304328                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304328                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17247                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17247                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373670                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373670                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373670                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373670                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       834944                       # number of writebacks
+system.cpu.dcache.writebacks::total            834944                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069359                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069359                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304327                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304327                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17246                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17246                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373686                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373686                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373686                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373686                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9653                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9653                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16583                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43701674500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43701674500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17330191000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17330191000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215563500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215563500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61031865500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  61031865500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61031865500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  61031865500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43703282000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43703282000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17330845000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17330845000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215551500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215551500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61034127000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61034127000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61034127000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61034127000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1526978500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1526978500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2172467000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2172467000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3699445500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3699445500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120370                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120370                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2172486500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2172486500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3699465000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3699465000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120373                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120373                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049431                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049431                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086114                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086114                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091332                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091332                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091332                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091332                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086109                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086109                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091333                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091333                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857                       # average overall mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            928920                       # number of replacements
-system.cpu.icache.tags.tagsinuse           506.355618                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55264986                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            929431                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.461096                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            928931                       # number of replacements
+system.cpu.icache.tags.tagsinuse           506.355616                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55264917                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            929442                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.460318                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       58592056500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   506.355618                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   506.355616                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.988976                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.988976                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
@@ -649,44 +638,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1            1
 system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57124168                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57124168                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     55264986                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55264986                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55264986                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55264986                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55264986                       # number of overall hits
-system.cpu.icache.overall_hits::total        55264986                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929591                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929591                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929591                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929591                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929591                       # number of overall misses
-system.cpu.icache.overall_misses::total        929591                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13686841500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13686841500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13686841500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13686841500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13686841500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13686841500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56194577                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56194577                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56194577                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56194577                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56194577                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56194577                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016542                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016542                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016542                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016542                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016542                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016542                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14723.509049                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14723.509049                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57124121                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57124121                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     55264917                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55264917                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55264917                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55264917                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55264917                       # number of overall hits
+system.cpu.icache.overall_hits::total        55264917                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929602                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929602                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929602                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929602                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929602                       # number of overall misses
+system.cpu.icache.overall_misses::total        929602                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13686117000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13686117000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13686117000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13686117000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13686117000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13686117000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56194519                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56194519                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56194519                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56194519                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56194519                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56194519                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016543                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016543                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016543                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016543                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016543                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016543                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14722.555459                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14722.555459                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -695,44 +684,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       928920                       # number of writebacks
-system.cpu.icache.writebacks::total            928920                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929591                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929591                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929591                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929591                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929591                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929591                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12757250500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12757250500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12757250500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12757250500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12757250500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12757250500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016542                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016542                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016542                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       928931                       # number of writebacks
+system.cpu.icache.writebacks::total            928931                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929602                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929602                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929602                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929602                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929602                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929602                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12756515000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12756515000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12756515000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12756515000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12756515000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12756515000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016543                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016543                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016543                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016543                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           336393                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65234.360010                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3930350                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        65234.360001                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3930403                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           401556                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.787800                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.787932                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      10619817000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4686.115262                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5475.418469                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4686.121272                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5475.418237                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.840345                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.071504                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.071505                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.083548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.995397                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
@@ -742,26 +731,26 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5220
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3221                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55822                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         37812565                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        37812565                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       834936                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       834936                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       928699                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       928699                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         37812972                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        37812972                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       834944                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       834944                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       928709                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       928709                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187491                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187491                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       916371                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       916371                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       814618                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       814618                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       916371                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002109                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918480                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       916371                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002109                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918480                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187490                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187490                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       916382                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       916382                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       814634                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       814634                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       916382                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1002124                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1918506                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       916382                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1002124                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1918506                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       116820                       # number of ReadExReq misses
@@ -776,66 +765,66 @@ system.cpu.l2cache.demand_misses::total        401991                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst        13200                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       388791                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       401991                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       320500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       320500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14900653000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14900653000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1727668500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1727668500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33719834000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  33719834000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1727668500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  48620487000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50348155500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1727668500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  48620487000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50348155500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       834936                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       834936                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       928699                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       928699                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       315000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       315000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14901349500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14901349500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1726796000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1726796000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33721236500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  33721236500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1726796000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  48622586000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50349382000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1726796000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  48622586000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50349382000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       834944                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       834944                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       928709                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       928709                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304311                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304311                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       929571                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       929571                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1086589                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1086589                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       929571                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1390900                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320471                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       929571                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1390900                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320471                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304310                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304310                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       929582                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       929582                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1086605                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1086605                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       929582                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1390915                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2320497                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       929582                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1390915                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2320497                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383884                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383884                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383885                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383885                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014200                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014200                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250298                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250298                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.250294                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.250294                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014200                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279525                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173237                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.279522                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.173235                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014200                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279525                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173237                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.279522                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.173235                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -866,106 +855,106 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9653
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9653                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16583                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       924500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       924500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13732453000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13732453000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1595668500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1595668500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31000124000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31000124000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1595668500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44732577000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  46328245500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1595668500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44732577000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  46328245500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       893500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       893500                       # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13733149500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1594796000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1594796000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31001526500                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44734676000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total  46329472000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1440322500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1440322500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2061377000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2061377000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3501699500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3501699500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2061396500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2061396500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3501719000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3501719000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383884                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383884                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383885                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383885                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250298                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250298                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.250294                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.250294                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279525                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173237                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279522                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173235                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279525                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173237                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279522                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173235                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256                       # average overall mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4639815                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319473                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1501                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4639867                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319499                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1502                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1136                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1136                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2023267                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2023294                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9653                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9653                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       950745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       928699                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       816471                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       928931                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       817743                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304311                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304311                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       929591                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1086762                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304310                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304310                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       929602                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1086778                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2787861                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4204279                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6992140                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118929280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142508140                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          261437420                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      419996                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2756910                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2788115                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4205589                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6993704                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    118944832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142509612                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          261454444                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      419988                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2756928                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.001015                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.031841                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.031847                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2754112     99.90%     99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2798      0.10%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2754129     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2799      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2756910                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4096881500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2756928                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4096926500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       293383                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1394386500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1394403000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2098115000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2098137500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1019,15 +1008,15 @@ system.iobus.reqLayer6.occupancy                10000                       # La
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy              174000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15817000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15817500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             1891500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6032000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6038000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           215014002                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215662167                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23513000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
@@ -1038,7 +1027,7 @@ system.iocache.tags.tagsinuse                1.339384                       # Cy
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1774106672000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         1774106669000                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::tsunami.ide     1.339384                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.083712                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.083712                       # Average percentage of cache occupancy
@@ -1057,8 +1046,8 @@ system.iocache.overall_misses::tsunami.ide          173                       #
 system.iocache.overall_misses::total              173                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21742883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21742883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5428926119                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5428926119                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5244713284                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5244713284                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::tsunami.ide     21742883                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_latency::total     21742883                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::tsunami.ide     21742883                       # number of overall miss cycles
@@ -1081,17 +1070,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 125681.404624                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total 125681.404624                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total 125681.404624                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            32                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs            29                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    14.500000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1107,8 +1096,8 @@ system.iocache.overall_mshr_misses::tsunami.ide          173
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13092883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     13092883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3351326119                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3351326119                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3165314984                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3165314984                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::tsunami.ide     13092883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::total     13092883                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::tsunami.ide     13092883                       # number of overall MSHR miss cycles
@@ -1123,8 +1112,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 75681.404624                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624                       # average overall mshr miss latency
@@ -1135,20 +1124,19 @@ system.membus.trans_dist::ReadResp             292274                       # Tr
 system.membus.trans_dist::WriteReq               9653                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9653                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty       115793                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261400                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261560                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              150                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             150                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            116683                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           116683                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq        285344                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139403                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172569                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1297386                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1139255                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1172421                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        83425                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        83425                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1255846                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44588                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30455296                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30499884                       # Cumulative packet size per connected master and slave (bytes)
@@ -1156,24 +1144,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                33157612                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              431                       # Total snoops (count)
-system.membus.snoop_fanout::samples            837681                       # Request fanout histogram
+system.membus.snoop_fanout::samples            837673                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  837681    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  837673    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              837681                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30116000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              837673                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            30122500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1287207146                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1287200967                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2143289352                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2143013000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69814679                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy             887117                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index e4317ec15..f7d0d7b39 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783867                       # Number of seconds simulated
-sim_ticks                                2783867052000                       # Number of ticks simulated
-final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783855                       # Number of seconds simulated
+sim_ticks                                2783854535000                       # Number of ticks simulated
+final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 624684                       # Simulator instruction rate (inst/s)
-host_op_rate                                   760453                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12180447765                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 563036                       # Number of bytes of host memory used
-host_seconds                                   228.55                       # Real time elapsed on the host
-sim_insts                                   142772879                       # Number of instructions simulated
-sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1852974                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2255698                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36130480826                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 581484                       # Number of bytes of host memory used
+host_seconds                                    77.05                       # Real time elapsed on the host
+sim_insts                                   142771651                       # Number of instructions simulated
+sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
@@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide           960                       # Nu
 system.physmem.bytes_read::total             11533384                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1207012                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8840896                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      8840960                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8858420                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858484                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              27313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             161845                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                189182                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::writebacks          138140                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142520                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142521                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               433574                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3708811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               433576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3708827                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4142936                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          433574                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3175761                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          433576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175798                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3182056                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3175761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3182093                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175798                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              433574                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3715106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              433576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3715122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7324992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7325048                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     10029                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                10029                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walkWaitTime::samples        10029                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           10029    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     10028                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                10028                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walkWaitTime::samples        10028                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           10028    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        10028                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0         6705500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6354     80.79%     80.79% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::4K          6353     80.79%     80.79% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::1M          1511     19.21%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7865                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        10029                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::total         7864                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        10028                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        10029                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7865                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        10028                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7864                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7865                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        17894                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7864                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        17892                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     31526223                       # DTB read hits
-system.cpu.dtb.read_misses                       8581                       # DTB read misses
-system.cpu.dtb.write_hits                    23124452                       # DTB write hits
+system.cpu.dtb.read_hits                     31525949                       # DTB read hits
+system.cpu.dtb.read_misses                       8580                       # DTB read misses
+system.cpu.dtb.write_hits                    23124104                       # DTB write hits
 system.cpu.dtb.write_misses                      1448                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -132,12 +132,12 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 31534804                       # DTB read accesses
-system.cpu.dtb.write_accesses                23125900                       # DTB write accesses
+system.cpu.dtb.read_accesses                 31534529                       # DTB read accesses
+system.cpu.dtb.write_accesses                23125552                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          54650675                       # DTB hits
-system.cpu.dtb.misses                           10029                       # DTB misses
-system.cpu.dtb.accesses                      54660704                       # DTB accesses
+system.cpu.dtb.hits                          54650053                       # DTB hits
+system.cpu.dtb.misses                           10028                       # DTB misses
+system.cpu.dtb.accesses                      54660081                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    147039346                       # ITB inst hits
+system.cpu.itb.inst_hits                    147038166                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -202,40 +202,40 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                147044108                       # ITB inst accesses
-system.cpu.itb.hits                         147039346                       # DTB hits
+system.cpu.itb.inst_accesses                147042928                       # ITB inst accesses
+system.cpu.itb.hits                         147038166                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     147044108                       # DTB accesses
-system.cpu.numCycles                       5567737188                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     147042928                       # DTB accesses
+system.cpu.numCycles                       5567712151                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3083                       # number of quiesce instructions executed
-system.cpu.committedInsts                   142772879                       # Number of instructions committed
-system.cpu.committedOps                     173803124                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             153162683                       # Number of integer alu accesses
+system.cpu.kern.inst.quiesce                     3080                       # number of quiesce instructions executed
+system.cpu.committedInsts                   142771651                       # Number of instructions committed
+system.cpu.committedOps                     173801592                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             153161279                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
-system.cpu.num_func_calls                    16873899                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18730330                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    153162683                       # number of integer instructions
+system.cpu.num_func_calls                    16873962                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18730275                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    153161279                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285059803                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          107179480                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           285057575                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          107178464                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            530854003                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            62364299                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      55939276                       # number of memory refs
-system.cpu.num_load_insts                    31855884                       # Number of load instructions
-system.cpu.num_store_insts                   24083392                       # Number of store instructions
-system.cpu.num_idle_cycles               5389653746.932674                       # Number of idle cycles
-system.cpu.num_busy_cycles               178083441.067325                       # Number of busy cycles
+system.cpu.num_cc_register_reads            530849543                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            62363904                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      55938616                       # number of memory refs
+system.cpu.num_load_insts                    31855585                       # Number of load instructions
+system.cpu.num_store_insts                   24083031                       # Number of store instructions
+system.cpu.num_idle_cycles               5389630193.939007                       # Number of idle cycles
+system.cpu.num_busy_cycles               178081957.060993                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
-system.cpu.Branches                          36396981                       # Number of branches fetched
+system.cpu.Branches                          36396978                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 121152838     68.36%     68.36% # Class of executed instruction
-system.cpu.op_class::IntMult                   116892      0.07%     68.43% # Class of executed instruction
+system.cpu.op_class::IntAlu                 121152037     68.36%     68.36% # Class of executed instruction
+system.cpu.op_class::IntMult                   116873      0.07%     68.43% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     68.43% # Class of executed instruction
@@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc               8569      0.00%     68.44% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 31855884     17.98%     86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite                24083392     13.59%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 31855585     17.98%     86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                24083031     13.59%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  177219912                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            819402                       # number of replacements
+system.cpu.op_class::total                  177218432                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            819392                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            53784483                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819914                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.597713                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            53783870                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819904                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.597765                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
@@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          286
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         219237582                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        219237582                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     30129052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30129052                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     22340110                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       22340110                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       395080                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        395080                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460136                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      52469162                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         52469162                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     52864242                       # number of overall hits
-system.cpu.dcache.overall_hits::total        52864242                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       396276                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        396276                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       301678                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       116120                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       116120                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         219235080                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        219235080                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     30128800                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30128800                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22339791                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22339791                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395065                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395065                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460122                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      52468591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52468591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     52863656                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52863656                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       396281                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396281                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301663                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301663                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       116121                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       116121                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8611                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8611                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       697954                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         697954                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       814074                       # number of overall misses
-system.cpu.dcache.overall_misses::total        814074                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     53678316                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     53678316                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_misses::cpu.data       697944                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697944                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       814065                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814065                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     30525081                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30525081                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641454                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641454                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     53166535                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53166535                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53677721                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53677721                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018482                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018482                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.227160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018481                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018481                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
@@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       682040                       # number of writebacks
-system.cpu.dcache.writebacks::total            682040                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682017                       # number of writebacks
+system.cpu.dcache.writebacks::total            682017                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1699214                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           145342721                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1699726                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             85.509500                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1698998                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           145341757                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699510                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.519801                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.663681                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.663679                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         148742185                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        148742185                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    145342721                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       145342721                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     145342721                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        145342721                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    145342721                       # number of overall hits
-system.cpu.icache.overall_hits::total       145342721                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1699732                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1699732                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1699732                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1699732                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1699732                       # number of overall misses
-system.cpu.icache.overall_misses::total       1699732                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.011559                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.011559                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         148740789                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        148740789                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    145341757                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145341757                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     145341757                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145341757                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    145341757                       # number of overall hits
+system.cpu.icache.overall_hits::total       145341757                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1699516                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699516                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1699516                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699516                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1699516                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699516                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    147041273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147041273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    147041273                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147041273                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147041273                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147041273                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.011558                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.011558                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1699214                       # number of writebacks
-system.cpu.icache.writebacks::total           1699214                       # number of writebacks
+system.cpu.icache.writebacks::writebacks      1698998                       # number of writebacks
+system.cpu.icache.writebacks::total           1698998                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109913                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65155.309141                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4525282                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        65155.314985                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4524855                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           175194                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            25.830120                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            25.827682                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.708883                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.628332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931995                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004344                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.704513                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.623437                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.744080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
@@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10699
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40582495                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40582495                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         40578944                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40578944                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7597                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          11222                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       682040                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       682040                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1667206                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1667206                       # number of WritebackClean hits
+system.cpu.l2cache.ReadReq_hits::total          11218                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       682017                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       682017                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1666999                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1666999                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151146                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151146                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681416                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1681416                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505440                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       505440                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681201                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1681201                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505445                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       505445                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7597                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681416                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656586                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2349224                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681201                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656576                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2348995                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7597                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681416                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656586                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2349224                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681201                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656576                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2348995                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
@@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker            2
 system.cpu.l2cache.overall_misses::cpu.inst        18298                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       163344                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       181651                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7604                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        11231                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       682040                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       682040                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1667206                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1667206                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11227                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       682017                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       682017                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1666999                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1666999                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1699714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521008                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699499                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1699499                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521013                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       521013                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7604                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819930                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2530875                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7608                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1699499                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819920                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2530646                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7604                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1699714                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819930                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699499                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819920                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530646                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000801                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000802                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494363                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494363                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010765                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029881                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029881                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494388                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494388                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010767                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010767                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029880                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029880                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010765                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199217                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071774                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199219                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071780                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010765                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199217                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071774                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199219                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071780                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101949                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101949                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101950                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101950                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5060356                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540713                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39274                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          420                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          420                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5059903                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540486                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          422                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq          67802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          67800                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288329                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       682040                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1667206                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       130096                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       682017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1698998                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       137375                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699732                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5084714                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574734                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699516                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       521013                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116074                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581970                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37000                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7714878                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215520120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308833                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        36996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7753470                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217540984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96306721                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          311939813                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      182974                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5319191                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018482                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.134685                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        73992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313958557                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      182975                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5318737                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018478                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.134674                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5220884     98.15%     98.15% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              98307      1.85%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5220455     98.15%     98.15% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              98282      1.85%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5319191                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5318737                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
@@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909961                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909893                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909961                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.909893                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq               40087                       # Tr
 system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       138139                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7977                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138140                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8203                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
@@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       506581                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total       613941                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 723072                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723299                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092412                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255449                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20586905                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586969                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples            434821                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index c3e49583c..df10533fc 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.802895                       # Number of seconds simulated
-sim_ticks                                2802894699500                       # Number of ticks simulated
-final_tick                               2802894699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.802883                       # Number of seconds simulated
+sim_ticks                                2802882879000                       # Number of ticks simulated
+final_tick                               2802882879000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 526774                       # Simulator instruction rate (inst/s)
-host_op_rate                                   641866                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10055912327                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 575028                       # Number of bytes of host memory used
-host_seconds                                   278.73                       # Real time elapsed on the host
-sim_insts                                   146828240                       # Number of instructions simulated
-sim_ops                                     178908039                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1272297                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1550275                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24287502010                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 596572                       # Number of bytes of host memory used
+host_seconds                                   115.40                       # Real time elapsed on the host
+sim_insts                                   146828562                       # Number of instructions simulated
+sim_ops                                     178908371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1108644                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          9410404                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           153876                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1082576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1109732                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          9413156                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           152660                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1082192                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11757100                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1108644                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       153876                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1262520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8452288                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11759340                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1109732                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       152660                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1262392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8477312                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8469852                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8494876                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             25776                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            147557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2559                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             16935                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             25793                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            147600                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             16929                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                192852                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          132067                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                192887                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          132458                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136458                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               136849                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           183                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              395535                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3357388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               54899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              386235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              395925                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3358384                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               54465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              386100                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4194628                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         395535                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          54899                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             450434                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3015557                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4195445                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         395925                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          54465                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             450391                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3024497                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6252                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3021823                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3015557                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3030764                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3024497                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          183                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             395535                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3363640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              54899                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             386249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             395925                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3364636                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              54465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             386114                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7216451                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7226208                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -118,29 +118,29 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     7967                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                7967                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         7967                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           7967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         7967                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                     7964                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7964                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         7964                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7964    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7964                       # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5082     77.32%     77.32% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1491     22.68%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6573                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7967                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5079     77.31%     77.31% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1491     22.69%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6570                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7964                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7967                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6573                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7964                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6570                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6573                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        14540                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6570                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        14534                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    20339720                       # DTB read hits
-system.cpu0.dtb.read_misses                      6874                       # DTB read misses
-system.cpu0.dtb.write_hits                   16391078                       # DTB write hits
+system.cpu0.dtb.read_hits                    20339777                       # DTB read hits
+system.cpu0.dtb.read_misses                      6871                       # DTB read misses
+system.cpu0.dtb.write_hits                   16391027                       # DTB write hits
 system.cpu0.dtb.write_misses                     1093                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
@@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults                        0                       # Nu
 system.cpu0.dtb.prefetch_faults                  1788                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                20346594                       # DTB read accesses
-system.cpu0.dtb.write_accesses               16392171                       # DTB write accesses
+system.cpu0.dtb.read_accesses                20346648                       # DTB read accesses
+system.cpu0.dtb.write_accesses               16392120                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         36730798                       # DTB hits
-system.cpu0.dtb.misses                           7967                       # DTB misses
-system.cpu0.dtb.accesses                     36738765                       # DTB accesses
+system.cpu0.dtb.hits                         36730804                       # DTB hits
+system.cpu0.dtb.misses                           7964                       # DTB misses
+system.cpu0.dtb.accesses                     36738768                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -204,7 +204,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2342                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2342                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         5700                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    97439331                       # ITB inst hits
+system.cpu0.itb.inst_hits                    97439598                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -221,40 +221,40 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                97442689                       # ITB inst accesses
-system.cpu0.itb.hits                         97439331                       # DTB hits
+system.cpu0.itb.inst_accesses                97442956                       # ITB inst accesses
+system.cpu0.itb.hits                         97439598                       # DTB hits
 system.cpu0.itb.misses                           3358                       # DTB misses
-system.cpu0.itb.accesses                     97442689                       # DTB accesses
-system.cpu0.numCycles                      5605791368                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     97442956                       # DTB accesses
+system.cpu0.numCycles                      5605767724                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1968                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   95426926                       # Number of instructions committed
-system.cpu0.committedOps                    115560427                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            100762696                       # Number of integer alu accesses
+system.cpu0.kern.inst.quiesce                    1965                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   95427136                       # Number of instructions committed
+system.cpu0.committedOps                    115560651                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            100762921                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
-system.cpu0.num_func_calls                    8000180                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     13204202                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   100762696                       # number of integer instructions
+system.cpu0.num_func_calls                    8000357                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     13204240                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   100762921                       # number of integer instructions
 system.cpu0.num_fp_insts                         9755                       # number of float instructions
-system.cpu0.num_int_register_reads          182457229                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          69135541                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          182457857                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          69135716                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           349971383                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           44907438                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     37873810                       # number of memory refs
-system.cpu0.num_load_insts                   20597310                       # Number of load instructions
-system.cpu0.num_store_insts                  17276500                       # Number of store instructions
-system.cpu0.num_idle_cycles              5488206876.247207                       # Number of idle cycles
-system.cpu0.num_busy_cycles              117584491.752793                       # Number of busy cycles
+system.cpu0.num_cc_register_reads           349972220                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           44907498                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     37873797                       # number of memory refs
+system.cpu0.num_load_insts                   20597358                       # Number of load instructions
+system.cpu0.num_store_insts                  17276439                       # Number of store instructions
+system.cpu0.num_idle_cycles              5488182951.223861                       # Number of idle cycles
+system.cpu0.num_busy_cycles              117584772.776139                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.020976                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.979024                       # Percentage of idle cycles
-system.cpu0.Branches                         21941499                       # Number of branches fetched
+system.cpu0.Branches                         21941714                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 78887256     67.49%     67.49% # Class of executed instruction
-system.cpu0.op_class::IntMult                  110639      0.09%     67.59% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 78887557     67.49%     67.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                  110635      0.09%     67.59% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     67.59% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     67.59% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     67.59% # Class of executed instruction
@@ -282,18 +282,18 @@ system.cpu0.op_class::SimdFloatMisc              8087      0.01%     67.60% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.60% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.60% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.60% # Class of executed instruction
-system.cpu0.op_class::MemRead                20597310     17.62%     85.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite               17276500     14.78%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                20597358     17.62%     85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite               17276439     14.78%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 116882065                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           693486                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          494.853665                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           35932410                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           693998                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            51.775956                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 116882349                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           693475                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.853481                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           35932424                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           693987                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.776797                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853665                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853481                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966511                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.966511                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -301,60 +301,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0          277
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         74113887                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        74113887                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     19108541                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       19108541                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15690389                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15690389                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346093                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       346093                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379629                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       379629                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363050                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       363050                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     34798930                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        34798930                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     35145023                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       35145023                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       373103                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       373103                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       295796                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       295796                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100321                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       100321                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6742                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6742                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18435                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        18435                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       668899                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        668899                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       769220                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       769220                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481644                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     19481644                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986185                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     15986185                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446414                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       446414                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386371                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       386371                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381485                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       381485                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     35467829                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     35467829                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     35914243                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     35914243                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019152                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.019152                       # miss rate for ReadReq accesses
+system.cpu0.dcache.tags.tag_accesses         74113882                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        74113882                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     19108626                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       19108626                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15690357                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15690357                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346080                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       346080                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379619                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       379619                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363029                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       363029                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     34798983                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        34798983                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     35145063                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       35145063                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       373096                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       373096                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       295789                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       295789                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100322                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       100322                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6740                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6740                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18444                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        18444                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       668885                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        668885                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       769207                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       769207                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481722                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     19481722                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986146                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     15986146                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446402                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       446402                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386359                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       386359                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381473                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       381473                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     35467868                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     35467868                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     35914270                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     35914270                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019151                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019151                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018503                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.018503                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224726                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224726                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017450                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017450                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048324                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048324                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224735                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224735                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017445                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017445                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048349                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048349                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018859                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.018859                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021418                       # miss rate for overall accesses
@@ -367,16 +367,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       693486                       # number of writebacks
-system.cpu0.dcache.writebacks::total           693486                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       693475                       # number of writebacks
+system.cpu0.dcache.writebacks::total           693475                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1109735                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.809992                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           96331417                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1110247                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            86.765753                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1109624                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.809991                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           96331795                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1110136                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            86.774769                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       6345717000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809992                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809991                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999629                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999629                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -384,32 +384,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0          212
 system.cpu0.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        195993602                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       195993602                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     96331417                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       96331417                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     96331417                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        96331417                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     96331417                       # number of overall hits
-system.cpu0.icache.overall_hits::total       96331417                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1110256                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1110256                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1110256                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1110256                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1110256                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1110256                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     97441673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     97441673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     97441673                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     97441673                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     97441673                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     97441673                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011394                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011394                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011394                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011394                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011394                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011394                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        195994025                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       195994025                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     96331795                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       96331795                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     96331795                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        96331795                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     96331795                       # number of overall hits
+system.cpu0.icache.overall_hits::total       96331795                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1110145                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1110145                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1110145                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1110145                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1110145                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1110145                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     97441940                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     97441940                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     97441940                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     97441940                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     97441940                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     97441940                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011393                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011393                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011393                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011393                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011393                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011393                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -418,8 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1109735                       # number of writebacks
-system.cpu0.icache.writebacks::total          1109735                       # number of writebacks
+system.cpu0.icache.writebacks::writebacks      1109624                       # number of writebacks
+system.cpu0.icache.writebacks::total          1109624                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
@@ -427,128 +427,128 @@ system.cpu0.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          249527                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16129.991654                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           2731505                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          265646                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           10.282500                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements          249486                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16123.886747                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           2730668                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          265599                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           10.281168                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      1471234000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.556147                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.076637                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.984336                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000156                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.984497                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16112                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.758477                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.070793                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.984012                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000107                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.984124                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16108                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5452                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7536                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2638                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.983398                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        59699237                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       59699237                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10182                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4496                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         14678                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       510201                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       510201                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1265145                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1265145                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94344                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total        94344                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1068613                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1068613                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       352244                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       352244                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10182                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4496                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1068613                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       446588                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1529879                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10182                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4496                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1068613                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       446588                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1529879                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          214                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          130                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          344                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26273                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26273                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18435                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18435                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175179                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       175179                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        41643                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        41643                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       127922                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       127922                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          214                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          130                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        41643                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       303101                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       345088                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          214                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          130                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        41643                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       303101                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       345088                       # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10396                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4626                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        15022                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       510201                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       510201                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      1265145                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      1265145                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26273                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        26273                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18435                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        18435                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269523                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       269523                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1110256                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1110256                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       480166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       480166                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10396                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4626                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      1110256                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       749689                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1874967                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10396                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4626                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1110256                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       749689                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1874967                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.020585                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.028102                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.022900                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5529                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7406                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2667                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.983154                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        59695806                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       59695806                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10175                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4509                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         14684                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       510631                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       510631                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      1264603                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      1264603                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94360                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total        94360                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1068362                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1068362                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       352230                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       352230                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10175                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4509                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1068362                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       446590                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        1529636                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10175                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4509                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1068362                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       446590                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1529636                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          216                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          118                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          334                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26269                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        26269                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18444                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        18444                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175160                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       175160                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        41783                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        41783                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       127928                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       127928                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          216                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker          118                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        41783                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       303088                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       345205                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          216                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker          118                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        41783                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       303088                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       345205                       # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10391                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4627                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        15018                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       510631                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       510631                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1264603                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1264603                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26269                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        26269                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18444                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        18444                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269520                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       269520                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1110145                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1110145                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       480158                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       480158                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10391                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4627                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1110145                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       749678                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1874841                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10391                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4627                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1110145                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       749678                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1874841                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.022240                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.649959                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.649959                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.037508                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.037508                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.266412                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.266412                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.020585                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.028102                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.037508                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404302                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.184050                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.020585                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.028102                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.037508                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404302                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.184050                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.649896                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.649896                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.037637                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.037637                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.266429                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.266429                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.037637                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404291                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.184125                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.037637                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404291                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.184125                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -557,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       192911                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          192911                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       193020                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          193020                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      3720245                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1860324                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27875                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       218142                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       215248                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         2894                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq         61416                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1651838                       # Transaction distribution
+system.cpu0.toL2Bus.snoop_filter.tot_requests      3720001                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1860202                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       218277                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       215192                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3085                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq         61410                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1651713                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        28341                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        28341                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       510201                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1265145                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        26273                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18435                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp        44708                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       269523                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       269523                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1110256                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       480166                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3327246                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2395284                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       510631                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1292468                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        26269                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18444                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp        44713                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       269520                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       269520                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1110145                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       480158                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3347958                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2402091                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28808                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          5764166                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    140768632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     92116612                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28796                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          5791673                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    142101304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     92552324                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         232968516                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     623122                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4318148                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.066969                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.252635                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         234736876                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     623160                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4317939                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.067042                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.252935                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           4031861     93.37%     93.37% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            283393      6.56%     99.93% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              2894      0.07%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           4031542     93.37%     93.37% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            283312      6.56%     99.93% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              3085      0.07%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4318148                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total       4317939                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -630,29 +630,29 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     3358                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                     3359                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                3359                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples         3359                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           3359    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         3359                       # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walksPending::samples  -1804206736                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0    -1804206736    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total  -1804206736                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1919     74.15%     74.15% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          669     25.85%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3358                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1919     74.12%     74.12% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          670     25.88%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2589                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3359                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2588                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3359                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2589                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         5946                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2589                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         5948                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12173916                       # DTB read hits
-system.cpu1.dtb.read_misses                      2852                       # DTB read misses
-system.cpu1.dtb.write_hits                    7587209                       # DTB write hits
+system.cpu1.dtb.read_hits                    12173929                       # DTB read hits
+system.cpu1.dtb.read_misses                      2853                       # DTB read misses
+system.cpu1.dtb.write_hits                    7587213                       # DTB write hits
 system.cpu1.dtb.write_misses                      506                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
@@ -663,12 +663,12 @@ system.cpu1.dtb.align_faults                        0                       # Nu
 system.cpu1.dtb.prefetch_faults                   290                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12176768                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7587715                       # DTB write accesses
+system.cpu1.dtb.read_accesses                12176782                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7587719                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         19761125                       # DTB hits
-system.cpu1.dtb.misses                           3358                       # DTB misses
-system.cpu1.dtb.accesses                     19764483                       # DTB accesses
+system.cpu1.dtb.hits                         19761142                       # DTB hits
+system.cpu1.dtb.misses                           3359                       # DTB misses
+system.cpu1.dtb.accesses                     19764501                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -716,7 +716,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1095                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1095                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         2829                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    53671575                       # ITB inst hits
+system.cpu1.itb.inst_hits                    53671686                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -733,40 +733,40 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                53673309                       # ITB inst accesses
-system.cpu1.itb.hits                         53671575                       # DTB hits
+system.cpu1.itb.inst_accesses                53673420                       # ITB inst accesses
+system.cpu1.itb.hits                         53671686                       # DTB hits
 system.cpu1.itb.misses                           1734                       # DTB misses
-system.cpu1.itb.accesses                     53673309                       # DTB accesses
-system.cpu1.numCycles                      5605320274                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     53673420                       # DTB accesses
+system.cpu1.numCycles                      5605296633                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   51401314                       # Number of instructions committed
-system.cpu1.committedOps                     63347612                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             56984241                       # Number of integer alu accesses
+system.cpu1.committedInsts                   51401426                       # Number of instructions committed
+system.cpu1.committedOps                     63347720                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             56984340                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
-system.cpu1.num_func_calls                    9170855                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      5967100                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    56984241                       # number of integer instructions
+system.cpu1.num_func_calls                    9170857                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      5967107                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    56984340                       # number of integer instructions
 system.cpu1.num_fp_insts                         1792                       # number of float instructions
-system.cpu1.num_int_register_reads          110674739                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          41298353                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          110674879                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          41298438                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           196268655                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           18894365                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     20026381                       # number of memory refs
-system.cpu1.num_load_insts                   12289537                       # Number of load instructions
-system.cpu1.num_store_insts                   7736844                       # Number of store instructions
-system.cpu1.num_idle_cycles              5539706759.565366                       # Number of idle cycles
-system.cpu1.num_busy_cycles              65613514.434634                       # Number of busy cycles
+system.cpu1.num_cc_register_reads           196268976                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           18894428                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     20026400                       # number of memory refs
+system.cpu1.num_load_insts                   12289552                       # Number of load instructions
+system.cpu1.num_store_insts                   7736848                       # Number of store instructions
+system.cpu1.num_idle_cycles              5539683011.597479                       # Number of idle cycles
+system.cpu1.num_busy_cycles              65613621.402521                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.011706                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.988294                       # Percentage of idle cycles
-system.cpu1.Branches                         15217493                       # Number of branches fetched
+system.cpu1.Branches                         15217504                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 45401310     69.36%     69.36% # Class of executed instruction
-system.cpu1.op_class::IntMult                   28388      0.04%     69.40% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 45401392     69.36%     69.36% # Class of executed instruction
+system.cpu1.op_class::IntMult                   28394      0.04%     69.40% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     69.40% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
@@ -794,80 +794,80 @@ system.cpu1.op_class::SimdFloatMisc              3319      0.01%     69.41% # Cl
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead                12289537     18.77%     88.18% # Class of executed instruction
-system.cpu1.op_class::MemWrite                7736844     11.82%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                12289552     18.77%     88.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite                7736848     11.82%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  65459464                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           191938                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          472.735415                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           19503509                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           192292                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           101.426523                       # Average number of references to valid blocks.
+system.cpu1.op_class::total                  65459571                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           191946                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          472.736016                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           19503521                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           192300                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           101.422366                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     105851601500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.735415                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923311                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.923311                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.736016                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923313                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.923313                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         39751979                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        39751979                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     11858694                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       11858694                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      7397500                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       7397500                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50099                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        50099                       # number of SoftPFReq hits
+system.cpu1.dcache.tags.tag_accesses         39752021                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        39752021                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     11858700                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       11858700                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      7397505                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       7397505                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50100                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        50100                       # number of SoftPFReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91447                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        91447                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72436                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        72436                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     19256194                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        19256194                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     19306293                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       19306293                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       136630                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       136630                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        92462                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        92462                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30719                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        30719                       # number of SoftPFReq misses
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72417                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        72417                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     19256205                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        19256205                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     19306305                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       19306305                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       136638                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       136638                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        92461                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        92461                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30718                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        30718                       # number of SoftPFReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5318                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         5318                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22543                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        22543                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       229092                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        229092                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       259811                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       259811                       # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995324                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     11995324                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489962                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7489962                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22562                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        22562                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       229099                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        229099                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       259817                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       259817                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995338                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     11995338                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489966                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      7489966                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80818                       # number of SoftPFReq accesses(hits+misses)
 system.cpu1.dcache.SoftPFReq_accesses::total        80818                       # number of SoftPFReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96765                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        96765                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94979                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        94979                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     19485286                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     19485286                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     19566104                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     19566104                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011390                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.011390                       # miss rate for ReadReq accesses
+system.cpu1.dcache.demand_accesses::cpu1.data     19485304                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     19485304                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     19566122                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     19566122                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011391                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.011391                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012345                       # miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::total     0.012345                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380101                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380101                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380089                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380089                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054958                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054958                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237347                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237347                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011757                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.011757                       # miss rate for demand accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237547                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237547                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011758                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.011758                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
@@ -878,42 +878,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       191938                       # number of writebacks
-system.cpu1.dcache.writebacks::total           191938                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks       191946                       # number of writebacks
+system.cpu1.dcache.writebacks::total           191946                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           523373                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.711129                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           53148780                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           523885                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           101.451235                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           523401                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.711077                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           53148863                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           523913                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           101.445971                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle      76931404500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711129                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711077                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975998                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.975998                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        107869215                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       107869215                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     53148780                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       53148780                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     53148780                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        53148780                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     53148780                       # number of overall hits
-system.cpu1.icache.overall_hits::total       53148780                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       523885                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       523885                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       523885                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        523885                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       523885                       # number of overall misses
-system.cpu1.icache.overall_misses::total       523885                       # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672665                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     53672665                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     53672665                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     53672665                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     53672665                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     53672665                       # number of overall (read+write) accesses
+system.cpu1.icache.tags.tag_accesses        107869465                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       107869465                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     53148863                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       53148863                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     53148863                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        53148863                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     53148863                       # number of overall hits
+system.cpu1.icache.overall_hits::total       53148863                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       523913                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       523913                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       523913                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        523913                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       523913                       # number of overall misses
+system.cpu1.icache.overall_misses::total       523913                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672776                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     53672776                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     53672776                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     53672776                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     53672776                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     53672776                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009761                       # miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_miss_rate::total     0.009761                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009761                       # miss rate for demand accesses
@@ -928,8 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       523373                       # number of writebacks
-system.cpu1.icache.writebacks::total           523373                       # number of writebacks
+system.cpu1.icache.writebacks::writebacks       523401                       # number of writebacks
+system.cpu1.icache.writebacks::total           523401                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
@@ -937,127 +937,127 @@ system.cpu1.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           47555                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15235.297156                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1184961                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           62593                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           18.931206                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements           47378                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15226.816500                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1184475                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           62425                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           18.974369                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.335617                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.010990                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.929623                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000143                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     1.255151                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.017200                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.929171                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000077                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000123                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.929889                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15019                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_percent::total     0.929371                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           20                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15027                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          530                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9526                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4963                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.916687                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        24500378                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       24500378                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3621                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1913                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total          5534                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks       121109                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total       121109                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       583044                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       583044                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19763                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        19763                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       510346                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       510346                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99093                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        99093                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3621                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1913                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       510346                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       118856                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         634736                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3621                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1913                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       510346                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       118856                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        634736                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          336                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          271                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          607                       # number of ReadReq misses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9441                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5060                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001221                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.917175                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        24501973                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       24501973                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3627                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1923                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total          5550                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks       121108                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total       121108                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       583081                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       583081                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19862                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        19862                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       510444                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       510444                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99124                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        99124                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3627                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1923                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       510444                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       118986                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         634980                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3627                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1923                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       510444                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       118986                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        634980                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          338                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          268                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          606                       # number of ReadReq misses
 system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28846                       # number of UpgradeReq misses
 system.cpu1.l2cache.UpgradeReq_misses::total        28846                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22543                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22543                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43853                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        43853                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13539                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        13539                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73574                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        73574                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          336                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          271                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        13539                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data       117427                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       131573                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          336                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          271                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        13539                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       117427                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       131573                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3957                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2184                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total         6141                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks       121109                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total       121109                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       583044                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       583044                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22562                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        22562                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43753                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        43753                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13469                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        13469                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73550                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        73550                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          338                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          268                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        13469                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data       117303                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       131378                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          338                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          268                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        13469                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data       117303                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       131378                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2191                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total         6156                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks       121108                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total       121108                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       583081                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       583081                       # number of WritebackClean accesses(hits+misses)
 system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28846                       # number of UpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.UpgradeReq_accesses::total        28846                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22543                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        22543                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63616                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        63616                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       523885                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       523885                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       172667                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       172667                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3957                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2184                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       523885                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       236283                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       766309                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3957                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2184                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       523885                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       236283                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       766309                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.084913                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.124084                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.098844                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22562                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        22562                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63615                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        63615                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       523913                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       523913                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       172674                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       172674                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3965                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2191                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       523913                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       236289                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       766358                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3965                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2191                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       523913                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       236289                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       766358                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.098441                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.689339                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.689339                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025843                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025843                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.426103                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.426103                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.084913                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.124084                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025843                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.496976                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.171697                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.084913                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.124084                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025843                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.496976                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.171697                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.687778                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.687778                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025708                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025708                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.425947                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.425947                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025708                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.496439                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.171432                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025708                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.496439                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.171432                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1066,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        32818                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           32818                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        32706                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           32706                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1533421                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       773256                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1533509                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       773310                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11158                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       165978                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       164041                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         12749                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       709301                       # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       166217                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       164146                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2071                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         12750                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       709337                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         2505                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         2505                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       121109                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       583044                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       121108                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       594239                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::UpgradeReq        28846                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22543                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        51389                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        63616                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        63616                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       523885                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       172667                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1562572                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       776509                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22562                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        51408                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        63615                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        63615                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       523913                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       172674                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1571581                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       778800                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12078                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2357775                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     66454020                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     27282414                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12080                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2369077                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     67028804                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     27426222                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24156                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          93773822                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     347349                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1819817                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.108136                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.313960                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          94492418                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     347790                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1820349                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.108308                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.314409                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1624967     89.29%     89.29% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            192913     10.60%     99.89% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              1937      0.11%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1625261     89.28%     89.28% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            193017     10.60%     99.89% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              2071      0.11%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1819817                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total       1820349                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30995                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30995                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59419                       # Transaction distribution
@@ -1161,14 +1161,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484014                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36442                       # number of replacements
-system.iocache.tags.tagsinuse               14.586092                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.586086                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         246641286009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.586092                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.911631                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.911631                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide    14.586086                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.911630                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.911630                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1209,175 +1209,175 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   107037                       # number of replacements
-system.l2c.tags.tagsinuse                62176.956554                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     241620                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   167464                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     1.442818                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   107729                       # number of replacements
+system.l2c.tags.tagsinuse                62410.633039                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     243914                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168410                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     1.448334                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   47954.224141                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.010653                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030815                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7778.474758                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4056.241083                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1664.556464                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      718.418639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.731723                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   48132.772899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.010469                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030814                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.data     4071.663088                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        60421                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        60675                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1839                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::4        45269                       # Occupied blocks per task id
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 system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.921951                       # Percentage of cache occupancy per task id
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-system.l2c.WritebackDirty_hits::total          225729                       # number of WritebackDirty hits
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-system.l2c.SCUpgradeReq_misses::cpu0.data          754                       # number of SCUpgradeReq misses
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-system.l2c.demand_accesses::total              324902                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker           82                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           70                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          41643                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         237651                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           36                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           27                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          13539                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          31854                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             324902                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.951582                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.980947                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.958672                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.920635                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.994093                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.964072                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.907631                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.834889                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.899485                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.097561                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.402493                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.128084                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.176823                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.087388                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.202323                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.097561                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.402493                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.621491                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.176823                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.532523                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.565789                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.097561                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.402493                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.621491                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.176823                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.532523                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.565789                       # miss rate for overall accesses
+system.l2c.ReadExReq_accesses::cpu0.data       150448                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        18862                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           169310                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           85                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           60                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        41783                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        87265                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           34                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           35                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        13469                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data        12858                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       155589                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker           85                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           60                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           41783                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          237713                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           34                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           35                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           13469                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           31720                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              324899                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker           85                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           60                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          41783                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         237713                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           34                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           35                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          13469                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          31720                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             324899                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946459                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965875                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.951165                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.900978                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.967960                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.940619                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.907609                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.838829                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.899947                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.401551                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.128207                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.176331                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.087494                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.202302                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.401551                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.621489                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.176331                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.534269                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.565856                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.401551                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.621489                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.176331                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.534269                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.565856                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1386,51 +1386,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95877                       # number of writebacks
-system.l2c.writebacks::total                    95877                       # number of writebacks
+system.l2c.writebacks::writebacks               96268                       # number of writebacks
+system.l2c.writebacks::total                    96268                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               43996                       # Transaction distribution
-system.membus.trans_dist::ReadResp              75712                       # Transaction distribution
+system.membus.trans_dist::ReadResp              75724                       # Transaction distribution
 system.membus.trans_dist::WriteReq              30846                       # Transaction distribution
 system.membus.trans_dist::WriteResp             30846                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       132067                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8465                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60519                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40906                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           15741                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            196031                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           151891                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         31716                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       132458                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8718                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            60357                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40887                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15566                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            152312                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           151914                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         31728                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107876                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       660645                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       782029                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109155                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109155                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 891184                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       617022                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       738406                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109394                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109394                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 847800                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162766                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17927560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18117342                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17954824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18144606                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2332288                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2332288                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20449630                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20476894                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            581009                       # Request fanout histogram
+system.membus.snoop_fanout::samples            537526                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  581009    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  537526    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              581009                       # Request fanout histogram
+system.membus.snoop_fanout::total              537526                       # Request fanout histogram
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
 system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
@@ -1472,41 +1472,41 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       863003                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       444472                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       128485                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           9552                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         9071                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          481                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests       862694                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       444199                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       128774                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           9862                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         9376                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          486                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq              44000                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            301629                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            301670                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             30846                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            30846                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       225729                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           38612                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           60623                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40978                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         101601                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           213528                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          213528                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       257629                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1143706                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       415843                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1559549                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34428348                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10418866                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               44847214                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          180208                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1117804                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.282168                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.451010                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty       225726                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           64248                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           60580                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         41006                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         101586                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           213448                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          213448                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       257670                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1161849                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       423225                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1585074                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34444668                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10399858                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               44844526                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          180900                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          1118187                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.282688                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.451270                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 802876     71.83%     71.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 314447     28.13%     99.96% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    481      0.04%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 802575     71.77%     71.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 315126     28.18%     99.96% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    486      0.04%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1117804                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            1118187                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 4c4524faa..ef75cc834 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783867                       # Number of seconds simulated
-sim_ticks                                2783867052000                       # Number of ticks simulated
-final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783855                       # Number of seconds simulated
+sim_ticks                                2783854535000                       # Number of ticks simulated
+final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 540254                       # Simulator instruction rate (inst/s)
-host_op_rate                                   657673                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10534181577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560556                       # Number of bytes of host memory used
-host_seconds                                   264.27                       # Real time elapsed on the host
-sim_insts                                   142772879                       # Number of instructions simulated
-sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1173204                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1428188                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22875895912                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 581200                       # Number of bytes of host memory used
+host_seconds                                   121.69                       # Real time elapsed on the host
+sim_insts                                   142771651                       # Number of instructions simulated
+sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
@@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide           960                       # Nu
 system.physmem.bytes_read::total             11533384                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1207012                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8840896                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      8840960                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8858420                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858484                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              27313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             161845                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                189182                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::writebacks          138140                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142520                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142521                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            161                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               433574                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3708811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               433576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3708827                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4142936                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          433574                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3175761                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          433576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175798                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6295                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3182056                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3175761                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3182093                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175798                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           161                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              433574                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3715106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              433576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3715122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7324992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7325048                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     10029                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                10029                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walkWaitTime::samples        10029                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           10029    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     10028                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                10028                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walkWaitTime::samples        10028                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           10028    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        10028                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0         6705500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6354     80.79%     80.79% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::4K          6353     80.79%     80.79% # Table walker page sizes translated
 system.cpu.dtb.walker.walkPageSizes::1M          1511     19.21%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7865                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        10029                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::total         7864                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        10028                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        10029                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7865                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        10028                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7864                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7865                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        17894                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7864                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        17892                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     31526223                       # DTB read hits
-system.cpu.dtb.read_misses                       8581                       # DTB read misses
-system.cpu.dtb.write_hits                    23124452                       # DTB write hits
+system.cpu.dtb.read_hits                     31525949                       # DTB read hits
+system.cpu.dtb.read_misses                       8580                       # DTB read misses
+system.cpu.dtb.write_hits                    23124104                       # DTB write hits
 system.cpu.dtb.write_misses                      1448                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -132,12 +132,12 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1613                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 31534804                       # DTB read accesses
-system.cpu.dtb.write_accesses                23125900                       # DTB write accesses
+system.cpu.dtb.read_accesses                 31534529                       # DTB read accesses
+system.cpu.dtb.write_accesses                23125552                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          54650675                       # DTB hits
-system.cpu.dtb.misses                           10029                       # DTB misses
-system.cpu.dtb.accesses                      54660704                       # DTB accesses
+system.cpu.dtb.hits                          54650053                       # DTB hits
+system.cpu.dtb.misses                           10028                       # DTB misses
+system.cpu.dtb.accesses                      54660081                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    147039346                       # ITB inst hits
+system.cpu.itb.inst_hits                    147038166                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -202,40 +202,40 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                147044108                       # ITB inst accesses
-system.cpu.itb.hits                         147039346                       # DTB hits
+system.cpu.itb.inst_accesses                147042928                       # ITB inst accesses
+system.cpu.itb.hits                         147038166                       # DTB hits
 system.cpu.itb.misses                            4762                       # DTB misses
-system.cpu.itb.accesses                     147044108                       # DTB accesses
-system.cpu.numCycles                       5567737188                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     147042928                       # DTB accesses
+system.cpu.numCycles                       5567712151                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3083                       # number of quiesce instructions executed
-system.cpu.committedInsts                   142772879                       # Number of instructions committed
-system.cpu.committedOps                     173803124                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             153162683                       # Number of integer alu accesses
+system.cpu.kern.inst.quiesce                     3080                       # number of quiesce instructions executed
+system.cpu.committedInsts                   142771651                       # Number of instructions committed
+system.cpu.committedOps                     173801592                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             153161279                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11484                       # Number of float alu accesses
-system.cpu.num_func_calls                    16873899                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18730330                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    153162683                       # number of integer instructions
+system.cpu.num_func_calls                    16873962                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     18730275                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    153161279                       # number of integer instructions
 system.cpu.num_fp_insts                         11484                       # number of float instructions
-system.cpu.num_int_register_reads           285059803                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          107179480                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           285057575                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          107178464                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8772                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            530854003                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            62364299                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      55939276                       # number of memory refs
-system.cpu.num_load_insts                    31855884                       # Number of load instructions
-system.cpu.num_store_insts                   24083392                       # Number of store instructions
-system.cpu.num_idle_cycles               5389653746.932674                       # Number of idle cycles
-system.cpu.num_busy_cycles               178083441.067325                       # Number of busy cycles
+system.cpu.num_cc_register_reads            530849543                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            62363904                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      55938616                       # number of memory refs
+system.cpu.num_load_insts                    31855585                       # Number of load instructions
+system.cpu.num_store_insts                   24083031                       # Number of store instructions
+system.cpu.num_idle_cycles               5389630193.939007                       # Number of idle cycles
+system.cpu.num_busy_cycles               178081957.060993                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.031985                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.968015                       # Percentage of idle cycles
-system.cpu.Branches                          36396981                       # Number of branches fetched
+system.cpu.Branches                          36396978                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 121152838     68.36%     68.36% # Class of executed instruction
-system.cpu.op_class::IntMult                   116892      0.07%     68.43% # Class of executed instruction
+system.cpu.op_class::IntAlu                 121152037     68.36%     68.36% # Class of executed instruction
+system.cpu.op_class::IntMult                   116873      0.07%     68.43% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     68.43% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     68.43% # Class of executed instruction
@@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc               8569      0.00%     68.44% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     68.44% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     68.44% # Class of executed instruction
-system.cpu.op_class::MemRead                 31855884     17.98%     86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite                24083392     13.59%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 31855585     17.98%     86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite                24083031     13.59%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  177219912                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            819402                       # number of replacements
+system.cpu.op_class::total                  177218432                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            819392                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.997174                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            53784483                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819914                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.597713                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            53783870                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819904                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.597765                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          23053500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997174                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
@@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          286
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         219237582                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        219237582                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     30129052                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        30129052                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     22340110                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       22340110                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       395080                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        395080                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       457347                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460136                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      52469162                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         52469162                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     52864242                       # number of overall hits
-system.cpu.dcache.overall_hits::total        52864242                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       396276                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        396276                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       301678                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       116120                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       116120                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data         8612                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         8612                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         219235080                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        219235080                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     30128800                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        30128800                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22339791                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22339791                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       395065                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        395065                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       457334                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460122                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      52468591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         52468591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     52863656                       # number of overall hits
+system.cpu.dcache.overall_hits::total        52863656                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       396281                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        396281                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       301663                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       301663                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       116121                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       116121                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8611                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         8611                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       697954                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         697954                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       814074                       # number of overall misses
-system.cpu.dcache.overall_misses::total        814074                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511200                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     53167116                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     53678316                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     53678316                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_misses::cpu.data       697944                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         697944                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       814065                       # number of overall misses
+system.cpu.dcache.overall_misses::total        814065                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     30525081                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     30525081                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22641454                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22641454                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511186                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     53166535                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     53166535                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     53677721                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     53677721                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012982                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012982                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.227152                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018482                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018482                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013323                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.227160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.227160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018481                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.018481                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.013128                       # miss rate for demand accesses
@@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       682040                       # number of writebacks
-system.cpu.dcache.writebacks::total            682040                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       682017                       # number of writebacks
+system.cpu.dcache.writebacks::total            682017                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1699214                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.663681                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           145342721                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1699726                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             85.509500                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1698998                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.663679                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           145341757                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1699510                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             85.519801                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle        7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.663681                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.663679                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         148742185                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        148742185                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    145342721                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       145342721                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     145342721                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        145342721                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    145342721                       # number of overall hits
-system.cpu.icache.overall_hits::total       145342721                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1699732                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1699732                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1699732                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1699732                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1699732                       # number of overall misses
-system.cpu.icache.overall_misses::total       1699732                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    147042453                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    147042453                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.011559                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.011559                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
+system.cpu.icache.tags.tag_accesses         148740789                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        148740789                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    145341757                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       145341757                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     145341757                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        145341757                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    145341757                       # number of overall hits
+system.cpu.icache.overall_hits::total       145341757                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1699516                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1699516                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1699516                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1699516                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1699516                       # number of overall misses
+system.cpu.icache.overall_misses::total       1699516                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    147041273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    147041273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    147041273                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    147041273                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    147041273                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    147041273                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.011558                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.011558                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1699214                       # number of writebacks
-system.cpu.icache.writebacks::total           1699214                       # number of writebacks
+system.cpu.icache.writebacks::writebacks      1698998                       # number of writebacks
+system.cpu.icache.writebacks::total           1698998                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           109913                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65155.309141                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4525282                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        65155.314985                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4524855                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           175194                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            25.830120                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            25.827682                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931998                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.708883                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.628332                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.931995                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.004344                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9168.704513                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  7219.623437                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.744080                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
@@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10699
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        50641                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996033                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40582495                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40582495                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7601                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         40578944                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40578944                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7597                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3621                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          11222                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       682040                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       682040                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1667206                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1667206                       # number of WritebackClean hits
+system.cpu.l2cache.ReadReq_hits::total          11218                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       682017                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       682017                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1666999                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1666999                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           28                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           28                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       151146                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       151146                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681416                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1681416                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505440                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       505440                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7601                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       151131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       151131                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1681201                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1681201                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       505445                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       505445                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7597                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         3621                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1681416                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       656586                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2349224                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7601                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst      1681201                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       656576                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2348995                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7597                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         3621                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1681416                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       656586                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2349224                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1681201                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       656576                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2348995                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
@@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker            2
 system.cpu.l2cache.overall_misses::cpu.inst        18298                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       163344                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       181651                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7608                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7604                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        11231                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       682040                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       682040                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1667206                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1667206                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11227                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       682017                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       682017                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1666999                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1666999                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       298922                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1699714                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521008                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7608                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       298907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1699499                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1699499                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       521013                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       521013                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7604                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         3623                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1699714                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819930                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2530875                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7608                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1699499                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819920                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2530646                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7604                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         3623                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1699714                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819930                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2530875                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1699499                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819920                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2530646                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000552                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000801                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000802                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989840                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494363                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.494363                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010765                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029881                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029881                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.494388                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.494388                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010767                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010767                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.029880                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.029880                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000552                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010765                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.199217                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071774                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.199219                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.071780                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000921                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000552                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010765                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.199217                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071774                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.199219                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.071780                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101949                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101949                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       101950                       # number of writebacks
+system.cpu.l2cache.writebacks::total           101950                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5060356                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540713                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39274                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          420                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          420                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5059903                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2540486                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          422                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq          67802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2288542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq          67800                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2288329                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27546                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27546                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       682040                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1667206                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       130096                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       682017                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1698998                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       137375                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2756                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       298922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       298922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699732                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5084714                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574734                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       298907                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1699516                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       521013                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5116074                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581970                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18430                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        37000                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7714878                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215520120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96308833                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        36996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7753470                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217540984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96306721                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        36860                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        74000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          311939813                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      182974                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5319191                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018482                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.134685                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        73992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313958557                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      182975                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5318737                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018478                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.134674                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5220884     98.15%     98.15% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              98307      1.85%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5220455     98.15%     98.15% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              98282      1.85%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5319191                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5318737                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
@@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909961                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909893                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909961                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.909893                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq               40087                       # Tr
 system.membus.trans_dist::ReadResp              74202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       138139                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7977                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138140                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8203                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
@@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       506581                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total       613941                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 723072                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723299                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092412                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255385                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18092476                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     18255449                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20586905                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586969                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples            434821                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 35b76497a..13b640b18 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,160 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.871850                       # Number of seconds simulated
-sim_ticks                                2871850306000                       # Number of ticks simulated
-final_tick                               2871850306000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.871782                       # Number of seconds simulated
+sim_ticks                                2871782342000                       # Number of ticks simulated
+final_tick                               2871782342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 312956                       # Simulator instruction rate (inst/s)
-host_op_rate                                   378531                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6832247646                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 599868                       # Number of bytes of host memory used
-host_seconds                                   420.34                       # Real time elapsed on the host
-sim_insts                                   131546959                       # Number of instructions simulated
-sim_ops                                     159110973                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 937604                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1134083                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            20478123685                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 614632                       # Number of bytes of host memory used
+host_seconds                                   140.24                       # Real time elapsed on the host
+sim_insts                                   131486349                       # Number of instructions simulated
+sim_ops                                     159039994                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1178404                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1267556                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8608576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1156004                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1264932                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8602496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           129300                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           549908                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       341632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           151508                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           548500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       349120                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12076912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1178404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       129300                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1307704                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8530240                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12074032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1156004                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       151508                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1307512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8524352                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8547804                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8541916                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26866                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20325                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       134509                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26516                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20284                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134414                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2175                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8613                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5338                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2522                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8591                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5455                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197850                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          133285                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                197805                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          133193                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               137676                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               137584                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           111                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              410329                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              441373                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2997571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              402539                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              440469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2995525                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               45023                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              191482                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       118959                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               52757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              190996                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       121569                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4205272                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         410329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          45023                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             455352                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2970294                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4204369                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         402539                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          52757                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             455296                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2968314                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6102                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2976410                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2970294                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2974430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2968314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          111                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             410329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             447475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2997571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             402539                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             446571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2995525                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              45023                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             191496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       118959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              52757                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             191010                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       121569                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7181682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197850                       # Number of read requests accepted
-system.physmem.writeReqs                       137676                       # Number of write requests accepted
-system.physmem.readBursts                      197850                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     137676                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12652352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8560960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12076912                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8547804                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7178799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197805                       # Number of read requests accepted
+system.physmem.writeReqs                       137584                       # Number of write requests accepted
+system.physmem.readBursts                      197805                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     137584                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12650304                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8554240                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12074032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8541916                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          64578                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11583                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11800                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11971                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11847                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               20098                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11961                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12460                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12487                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11821                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12495                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11828                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11338                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11476                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11922                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11270                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11336                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8288                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8566                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8821                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8522                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7854                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8398                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8910                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8793                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8333                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8912                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8495                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8357                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8083                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7998                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7822                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7613                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11699                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11843                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11790                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11735                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               20524                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11797                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12442                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12572                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12187                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12631                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11774                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11306                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11587                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11723                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11020                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11031                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8350                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8610                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8670                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8312                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8160                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8304                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8940                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8786                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8636                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9040                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8341                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8261                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8330                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7860                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7712                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7348                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2871849883000                       # Total gap between requests
+system.physmem.totGap                    2871781902000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  188090                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  188045                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 133285                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    138613                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15680                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     10206                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8777                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7036                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5467                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4577                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3339                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        81                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       56                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 133193                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138723                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     15603                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     10240                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8695                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3833                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3359                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        91                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       65                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -184,161 +184,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5092                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6617                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7823                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8913                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       80                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        87676                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      241.950454                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     136.764211                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.933653                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46396     52.92%     52.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17641     20.12%     73.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5908      6.74%     79.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3515      4.01%     83.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2504      2.86%     86.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1565      1.78%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          855      0.98%     89.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          945      1.08%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8347      9.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          87676                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6535                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.251262                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      585.438505                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6533     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8505                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      107                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        87582                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      242.110023                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     136.595388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     304.444001                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46635     53.25%     53.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17297     19.75%     73.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6011      6.86%     79.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3421      3.91%     83.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2493      2.85%     86.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1531      1.75%     88.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          857      0.98%     89.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          971      1.11%     90.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8366      9.55%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          87582                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6415                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        30.812159                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      590.882305                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6413     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6535                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6535                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.469013                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.883832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.598321                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5330     81.56%     81.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             483      7.39%     88.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              73      1.12%     90.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             153      2.34%     92.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              33      0.50%     92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             123      1.88%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              36      0.55%     95.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              26      0.40%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              25      0.38%     96.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.23%     96.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.09%     96.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             152      2.33%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.03%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.40%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.11%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.20%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.05%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::244-247             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6535                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4503336233                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8210079983                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    988465000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22779.44                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6415                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6415                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.835542                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.951972                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       14.109397                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5337     83.20%     83.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             463      7.22%     90.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              65      1.01%     91.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              41      0.64%     92.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              43      0.67%     92.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              15      0.23%     92.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              61      0.95%     93.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     94.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             120      1.87%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.19%     96.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.19%     96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              75      1.17%     97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.14%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.39%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              75      1.17%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.03%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.05%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.17%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             3      0.05%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             5      0.08%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6415                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4510532456                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8216676206                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    988305000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22819.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41529.44                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  41569.54                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.21                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165103                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     78678                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.88                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165067                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     78671                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   83.51                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.81                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8559246.92                       # Average gap between requests
-system.physmem.pageHitRate                      73.54                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  341250840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  186198375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 812814600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                441624960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           187575236160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            85820448015                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1647828636000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1923006208950                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.605484                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2741162536487                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95897360000                       # Time in different power states
+system.physmem.writeRowHitRate                  58.85                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8562540.52                       # Average gap between requests
+system.physmem.pageHitRate                      73.56                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  341273520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  186210750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 814335600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                441495360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           187570659120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            86023351485                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1647608604750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1922985930585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.614762                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2740794855198                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95895020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34789668513                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     35089613552                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  321579720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  175465125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 729183000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                425172240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           187575236160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            84866434740                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1648665489750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1922758560735                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.519251                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2742561244982                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95897360000                       # Time in different power states
+system.physmem_1.actEnergy                  320846400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  175065000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 727412400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                424621440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           187570659120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            84787415640                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1648692759000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1922698779000                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.514771                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2742610583350                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95895020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     33391555518                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     33276576650                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
@@ -394,56 +396,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     8830                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                8830                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1617                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7213                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         8830                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           8830    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         8830                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         7312                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6252.045789                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767         7284     99.62%     99.62% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           24      0.33%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         7312                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                     8793                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                8793                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1631                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7162                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         8793                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           8793    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         8793                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         7275                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  5725.376750                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         6764     92.98%     92.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767          475      6.53%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151           28      0.38%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            4      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-147455            2      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         7275                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5742     78.53%     78.53% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1570     21.47%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7312                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8830                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5691     78.23%     78.23% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1584     21.77%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7275                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8793                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8830                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7312                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8793                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7275                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7312                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        16142                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7275                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        16068                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25809403                       # DTB read hits
-system.cpu0.dtb.read_misses                      7606                       # DTB read misses
-system.cpu0.dtb.write_hits                   19327142                       # DTB write hits
-system.cpu0.dtb.write_misses                     1224                       # DTB write misses
+system.cpu0.dtb.read_hits                    25747110                       # DTB read hits
+system.cpu0.dtb.read_misses                      7587                       # DTB read misses
+system.cpu0.dtb.write_hits                   19248161                       # DTB write hits
+system.cpu0.dtb.write_misses                     1206                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3761                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3752                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1861                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1822                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      321                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25817009                       # DTB read accesses
-system.cpu0.dtb.write_accesses               19328366                       # DTB write accesses
+system.cpu0.dtb.read_accesses                25754697                       # DTB read accesses
+system.cpu0.dtb.write_accesses               19249367                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         45136545                       # DTB hits
-system.cpu0.dtb.misses                           8830                       # DTB misses
-system.cpu0.dtb.accesses                     45145375                       # DTB accesses
+system.cpu0.dtb.hits                         44995271                       # DTB hits
+system.cpu0.dtb.misses                           8793                       # DTB misses
+system.cpu0.dtb.accesses                     45004064                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -481,15 +486,13 @@ system.cpu0.itb.walker.walkWaitTime::samples         3674
 system.cpu0.itb.walker.walkWaitTime::0           3674    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         3674                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkCompletionTime::samples         2576                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6240.244766                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2261     87.77%     87.77% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          282     10.95%     98.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           30      1.16%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  7309.377161                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767         2541     98.64%     98.64% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535           33      1.28%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::total         2576                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   1809154500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     1809154500    100.00%    100.00% # Table walker pending requests distribution
@@ -504,7 +507,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2576                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2576                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         6250                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   121850168                       # ITB inst hits
+system.cpu0.itb.inst_hits                   121581439                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3674                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -521,172 +524,172 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               121853842                       # ITB inst accesses
-system.cpu0.itb.hits                        121850168                       # DTB hits
+system.cpu0.itb.inst_accesses               121585113                       # ITB inst accesses
+system.cpu0.itb.hits                        121581439                       # DTB hits
 system.cpu0.itb.misses                           3674                       # DTB misses
-system.cpu0.itb.accesses                    121853842                       # DTB accesses
-system.cpu0.numCycles                      5743700612                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                    121585113                       # DTB accesses
+system.cpu0.numCycles                      5743564684                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1892                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  118029542                       # Number of instructions committed
-system.cpu0.committedOps                    142673635                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            126253590                       # Number of integer alu accesses
+system.cpu0.kern.inst.quiesce                    1899                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  117764996                       # Number of instructions committed
+system.cpu0.committedOps                    142323546                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            125936873                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                 11483                       # Number of float alu accesses
-system.cpu0.num_func_calls                   12792333                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     16043976                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   126253590                       # number of integer instructions
+system.cpu0.num_func_calls                   12772448                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     16008688                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   125936873                       # number of integer instructions
 system.cpu0.num_fp_insts                        11483                       # number of float instructions
-system.cpu0.num_int_register_reads          232324144                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          87654298                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          231719006                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          87450436                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                8771                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2716                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           516734560                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           53610723                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     46299073                       # number of memory refs
-system.cpu0.num_load_insts                   26069844                       # Number of load instructions
-system.cpu0.num_store_insts                  20229229                       # Number of store instructions
-system.cpu0.num_idle_cycles              5455076908.366100                       # Number of idle cycles
-system.cpu0.num_busy_cycles              288623703.633900                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050250                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949750                       # Percentage of idle cycles
-system.cpu0.Branches                         29603215                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           515468589                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           53496392                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     46152180                       # number of memory refs
+system.cpu0.num_load_insts                   26006060                       # Number of load instructions
+system.cpu0.num_store_insts                  20146120                       # Number of store instructions
+system.cpu0.num_idle_cycles              5455990176.452100                       # Number of idle cycles
+system.cpu0.num_busy_cycles              287574507.547900                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050069                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949931                       # Percentage of idle cycles
+system.cpu0.Branches                         29546529                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2315      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                100054313     68.31%     68.31% # Class of executed instruction
-system.cpu0.op_class::IntMult                  112340      0.08%     68.39% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              8369      0.01%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.39% # Class of executed instruction
-system.cpu0.op_class::MemRead                26069844     17.80%     86.19% # Class of executed instruction
-system.cpu0.op_class::MemWrite               20229229     13.81%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 99842345     68.33%     68.33% # Class of executed instruction
+system.cpu0.op_class::IntMult                  112141      0.08%     68.41% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8311      0.01%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.41% # Class of executed instruction
+system.cpu0.op_class::MemRead                26006060     17.80%     86.21% # Class of executed instruction
+system.cpu0.op_class::MemWrite               20146120     13.79%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 146476410                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           740882                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          488.760528                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           44216040                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           741394                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            59.639058                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 146117292                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           732778                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          487.345221                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           44083181                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           733290                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            60.116981                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1836359000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   488.760528                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.954610                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.954610                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   487.345221                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.951846                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.951846                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         90957934                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        90957934                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     24496228                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       24496228                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     18570022                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18570022                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       327271                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       327271                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374846                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       374846                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       372508                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       372508                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     43066250                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        43066250                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     43393521                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       43393521                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       423502                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       423502                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       340254                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       340254                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133712                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       133712                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22535                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22535                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19849                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        19849                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       763756                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        763756                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       897468                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       897468                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5717292500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5717292500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6989183500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6989183500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    344979500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    344979500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    511150000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    511150000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1456500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1456500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  12706476000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  12706476000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  12706476000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  12706476000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     24919730                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     24919730                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     18910276                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     18910276                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       460983                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       460983                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397381                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       397381                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       392357                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       392357                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     43830006                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     43830006                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     44290989                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     44290989                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016995                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.016995                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017993                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017993                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.290058                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.290058                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056709                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056709                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050589                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050589                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017425                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.017425                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020263                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.020263                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         90667478                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        90667478                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     24441740                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       24441740                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     18494582                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18494582                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       326232                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       326232                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374079                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       374079                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371656                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       371656                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     42936322                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        42936322                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     43262554                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       43262554                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       418013                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       418013                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       337667                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       337667                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133440                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       133440                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22337                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        22337                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19808                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19808                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       755680                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        755680                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       889120                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       889120                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5665137000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5665137000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6926542000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6926542000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    343483500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    343483500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    502731000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    502731000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1840500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1840500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  12591679000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  12591679000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  12591679000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  12591679000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     24859753                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     24859753                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     18832249                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     18832249                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       459672                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       459672                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396416                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       396416                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391464                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391464                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     43692002                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     43692002                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     44151674                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     44151674                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016815                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.016815                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017930                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017930                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.290294                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.290294                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056347                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056347                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050600                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050600                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017296                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.017296                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020138                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.020138                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -695,147 +698,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       740882                       # number of writebacks
-system.cpu0.dcache.writebacks::total           740882                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25304                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25304                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15852                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15852                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        25304                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        25304                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        25304                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        25304                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       398198                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       398198                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       340254                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       340254                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106613                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       106613                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6683                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6683                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19849                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        19849                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       738452                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       738452                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       845065                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       845065                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31860                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31860                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28553                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28553                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60413                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60413                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4887280000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4887280000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6648929500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6648929500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1745313500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1745313500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    102495000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102495000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    491343000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    491343000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1414500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1414500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11536209500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11536209500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13281523000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13281523000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6641550500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6641550500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5414724500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5414724500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12056275000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12056275000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015979                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015979                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017993                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017993                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231273                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.231273                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016818                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016818                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050589                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050589                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019080                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.019080                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       732778                       # number of writebacks
+system.cpu0.dcache.writebacks::total           732778                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25286                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25286                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            2                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15664                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15664                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        25288                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        25288                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        25288                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        25288                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       392727                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       392727                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337665                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       337665                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106338                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       106338                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6673                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6673                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19808                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19808                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       730392                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       730392                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       836730                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       836730                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31820                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31820                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60319                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60319                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4843447000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4843447000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6588824500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6588824500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1737105000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737105000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    102846500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102846500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    482970000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    482970000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1793500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1793500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11432271500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11432271500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13169376500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13169376500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629050000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629050000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5400878000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5400878000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12029928000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12029928000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015798                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015798                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017930                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017930                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231335                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.231335                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016833                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016833                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050600                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050600                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016717                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016717                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018951                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018951                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1154605                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.321447                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          120695042                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1155117                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           104.487287                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1147265                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.321425                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          120433653                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1147777                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           104.927746                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      14862010000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321447                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321425                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998675                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998675                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        244855462                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       244855462                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    120695042                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      120695042                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    120695042                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       120695042                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    120695042                       # number of overall hits
-system.cpu0.icache.overall_hits::total      120695042                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1155126                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1155126                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1155126                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1155126                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1155126                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1155126                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12352499000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12352499000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12352499000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12352499000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12352499000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12352499000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    121850168                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    121850168                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    121850168                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    121850168                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    121850168                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    121850168                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009480                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009480                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009480                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009480                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009480                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009480                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10693.637750                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10693.637750                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        244310664                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       244310664                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    120433653                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      120433653                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    120433653                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       120433653                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    120433653                       # number of overall hits
+system.cpu0.icache.overall_hits::total      120433653                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1147786                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1147786                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1147786                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1147786                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1147786                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1147786                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12247651500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  12247651500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  12247651500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  12247651500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  12247651500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  12247651500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    121581439                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    121581439                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    121581439                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    121581439                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    121581439                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    121581439                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009440                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.009440                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009440                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.009440                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009440                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.009440                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10670.675108                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10670.675108                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -844,330 +849,331 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1154605                       # number of writebacks
-system.cpu0.icache.writebacks::total          1154605                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1155126                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1155126                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1155126                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1155126                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1155126                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1155126                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1147265                       # number of writebacks
+system.cpu0.icache.writebacks::total          1147265                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147786                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1147786                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1147786                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1147786                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1147786                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1147786                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11774936000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11774936000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11774936000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11774936000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11774936000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11774936000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11673758500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11673758500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11673758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11673758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11673758500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11673758500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009480                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009480                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009480                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009440                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009440                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009440                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1946486                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1946511                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           22                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935691                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1935756                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           57                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       246425                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          273842                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16083.519419                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3089138                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          289977                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           10.653045                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       245684                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          272679                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16060.422672                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3064880                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          288783                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           10.613090                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     0.644607                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.130850                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1489.168531                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.890721                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000039                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     0.514376                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.125186                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1500.655266                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.888619                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000031                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.090892                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.981660                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1031                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.091593                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.980250                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1021                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15101                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          282                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          325                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          414                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15080                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          262                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          312                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          434                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3285                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7655                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3857                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062927                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3313                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7651                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3839                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062317                       # Percentage of cache occupancy per task id
 system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.921692                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        63340451                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       63340451                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        11537                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4979                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         16516                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       507696                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       507696                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1358751                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1358751                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       241135                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       241135                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1108628                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1108628                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       416937                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       416937                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        11537                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4979                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1108628                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       658072                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1783216                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        11537                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4979                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1108628                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       658072                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1783216                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          155                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           97                       # number of ReadReq misses
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920410                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        62824015                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       62824015                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10929                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4820                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         15749                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       500939                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       500939                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      1350193                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      1350193                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       238805                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       238805                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1101574                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1101574                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       411559                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       411559                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10929                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4820                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1101574                       # number of demand (read+write) hits
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 system.cpu0.l2cache.ReadReq_misses::total          252                       # number of ReadReq misses
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 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.153728                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040254                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040254                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.184864                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.184864                       # miss rate for ReadSharedReq accesses
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-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040254                       # miss rate for demand accesses
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-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.013257                       # miss rate for overall accesses
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-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040254                       # miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635                       # average ReadReq miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3115.228867                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2182.322112                       # average SCUpgradeReq miss latency
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-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595                       # average ReadExReq miss latency
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-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394                       # average ReadSharedReq miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           32                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154915                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154915                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040262                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040262                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186221                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186221                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.015671                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015925                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040262                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.174999                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.094472                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.015671                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015925                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040262                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.174999                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.094472                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26744.047619                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2960.224385                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2960.224385                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2038.385777                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2038.385777                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 191277.444444                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 191277.444444                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63728.093019                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63728.093019                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71202.631351                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71202.631351                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34385.924675                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34385.924675                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71202.631351                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43696.806930                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 50566.094058                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71202.631351                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43696.806930                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 50566.094058                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       232272                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          232272                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1851                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1851                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           57                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           57                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1908                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         1908                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1908                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         1908                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          155                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           97                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       231522                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          231522                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1822                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1822                       # number of ReadExReq MSHR hits
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+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           60                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1882                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1882                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         1882                       # number of overall MSHR hits
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 system.cpu0.l2cache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264558                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       264558                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55316                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55316                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19844                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19844                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41952                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41952                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46498                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46498                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94500                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94500                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          155                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136452                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       183202                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46498                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136452                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total       447760                       # number of overall MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264994                       # number of HardPFReq MSHR misses
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55084                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55084                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19799                       # number of SCUpgradeReq MSHR misses
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41954                       # number of ReadExReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31860                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40882                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28553                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28553                       # number of WriteReq MSHR uncacheable
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60413                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69435                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5294500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20402670222                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20402670222                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1434169000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1434169000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    342730000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    342730000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1097997                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1097997                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2366849000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2366849000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3059185500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3059185500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2673492000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2673492000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1958500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5040341000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8104821000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5040341000                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total  28507491222                       # number of overall MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6386259500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7572471000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5200454500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5200454500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6374077000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7560288500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5187014000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5187014000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11586714000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12772925500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015029                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11561091000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12747302500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015749                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1176,117 +1182,117 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.147232                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.147232                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040254                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184753                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184753                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171329                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093075                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171329                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148467                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148467                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040262                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186102                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.186102                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.172612                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093508                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.172612                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227483                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229255                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      3935499                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1983981                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        29039                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       320941                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       317478                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3463                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq         63971                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1779248                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28553                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28553                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       740475                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1358751                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       190136                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       311790                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85728                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41989                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       112642                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           35                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       304006                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       300714                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1155126                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       580591                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3227                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3461069                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2699694                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12104                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27735                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6200602                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    146461624                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    102248167                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        20304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        46768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         248776863                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     987005                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      2997932                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.122336                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.331180                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      3905249                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1969182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28911                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       320342                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       316677                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3665                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq         63843                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1765873                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       732965                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1379104                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       189043                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       312150                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        85708                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41941                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       112560                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       301555                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       298207                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1147786                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       575214                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3299                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3460881                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2681738                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11926                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27058                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6181603                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    146919352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    101652834                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        19592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        44412                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         248636190                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     986669                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      2981108                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.123159                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.332339                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2634639     87.88%     87.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            359830     12.00%     99.88% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              3463      0.12%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2617624     87.81%     87.81% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            359819     12.07%     99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              3665      0.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       2997932                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3917122496                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       2981108                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3885976496                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115533329                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115188451                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1741711000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1730701000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1278424980                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1266054481                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu0.toL2Bus.respLayer2.occupancy      7028000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     16050485                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     15961487                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1317,57 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     2352                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                2352                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          487                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1865                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         2352                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           2352    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         2352                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1706                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5645.878722                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         1558     91.32%     91.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          139      8.15%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151            5      0.29%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.18%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     2346                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                2346                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          473                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1873                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         2346                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           2346    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         2346                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1700                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5957.546231                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1554     91.41%     91.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          135      7.94%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            5      0.29%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            5      0.29%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1706                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1700                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples  -1207257828                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0    -1207257828    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total  -1207257828                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1219     71.45%     71.45% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          487     28.55%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1706                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2352                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1227     72.18%     72.18% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          473     27.82%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1700                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2346                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2352                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1706                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2346                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1700                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1706                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         4058                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1700                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         4046                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3283088                       # DTB read hits
-system.cpu1.dtb.read_misses                      1969                       # DTB read misses
-system.cpu1.dtb.write_hits                    2849660                       # DTB write hits
-system.cpu1.dtb.write_misses                      383                       # DTB write misses
+system.cpu1.dtb.read_hits                     3334779                       # DTB read hits
+system.cpu1.dtb.read_misses                      1954                       # DTB read misses
+system.cpu1.dtb.write_hits                    2915242                       # DTB write hits
+system.cpu1.dtb.write_misses                      392                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1653                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1652                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   218                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3285057                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2850043                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3336733                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2915634                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6132748                       # DTB hits
-system.cpu1.dtb.misses                           2352                       # DTB misses
-system.cpu1.dtb.accesses                      6135100                       # DTB accesses
+system.cpu1.dtb.hits                          6250021                       # DTB hits
+system.cpu1.dtb.misses                           2346                       # DTB misses
+system.cpu1.dtb.accesses                      6252367                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1405,21 +1411,20 @@ system.cpu1.itb.walker.walkWaitTime::samples         1376
 system.cpu1.itb.walker.walkWaitTime::0           1376    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::total         1376                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkCompletionTime::samples          819                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5216.232861                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          112     13.68%     13.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          592     72.28%     85.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383           66      8.06%     94.02% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479            7      0.85%     94.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5150.797327                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          116     14.16%     14.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          577     70.45%     84.62% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383           76      9.28%     93.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479            8      0.98%     94.87% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.24%     95.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           24      2.93%     98.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            5      0.61%     98.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.73%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           22      2.69%     97.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.98%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.61%     99.51% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.24%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.24%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::total          819                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples  -1208095828                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0    -1208095828    100.00%    100.00% # Table walker pending requests distribution
@@ -1434,7 +1439,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          819                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total          819                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         2195                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    13713445                       # ITB inst hits
+system.cpu1.itb.inst_hits                    13920333                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1376                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1451,171 +1456,171 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                13714821                       # ITB inst accesses
-system.cpu1.itb.hits                         13713445                       # DTB hits
+system.cpu1.itb.inst_accesses                13921709                       # ITB inst accesses
+system.cpu1.itb.hits                         13920333                       # DTB hits
 system.cpu1.itb.misses                           1376                       # DTB misses
-system.cpu1.itb.accesses                     13714821                       # DTB accesses
-system.cpu1.numCycles                      5742759797                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     13921709                       # DTB accesses
+system.cpu1.numCycles                      5742623362                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2753                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   13517417                       # Number of instructions committed
-system.cpu1.committedOps                     16437338                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             14911378                       # Number of integer alu accesses
+system.cpu1.kern.inst.quiesce                    2722                       # number of quiesce instructions executed
+system.cpu1.committedInsts                   13721353                       # Number of instructions committed
+system.cpu1.committedOps                     16716448                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             15155011                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     901174                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1468136                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    14911378                       # number of integer instructions
+system.cpu1.num_func_calls                     915079                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1497955                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    15155011                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads           27063131                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          10536793                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           27537464                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          10698089                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            60344215                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            5099594                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6349896                       # number of memory refs
-system.cpu1.num_load_insts                    3389045                       # Number of load instructions
-system.cpu1.num_store_insts                   2960851                       # Number of store instructions
-system.cpu1.num_idle_cycles              5696813538.222876                       # Number of idle cycles
-system.cpu1.num_busy_cycles              45946258.777124                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.008001                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.991999                       # Percentage of idle cycles
-system.cpu1.Branches                          2418797                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            61338598                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            5194112                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6464162                       # number of memory refs
+system.cpu1.num_load_insts                    3439477                       # Number of load instructions
+system.cpu1.num_store_insts                   3024685                       # Number of store instructions
+system.cpu1.num_idle_cycles              5696031009.438875                       # Number of idle cycles
+system.cpu1.num_busy_cycles              46592352.561125                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.008113                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.991887                       # Percentage of idle cycles
+system.cpu1.Branches                          2464329                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 10377527     61.94%     61.94% # Class of executed instruction
-system.cpu1.op_class::IntMult                   24492      0.15%     62.08% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.08% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              3134      0.02%     62.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.10% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.10% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3389045     20.23%     82.33% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2960851     17.67%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 10543721     61.89%     61.89% # Class of executed instruction
+system.cpu1.op_class::IntMult                   24250      0.14%     62.04% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.04% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3188      0.02%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.05% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3439477     20.19%     82.24% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3024685     17.76%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  16755073                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           144073                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          473.219627                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5912733                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           144418                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            40.941801                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     106295131000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.219627                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924257                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.924257                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          345                       # Occupied blocks per task id
+system.cpu1.op_class::total                  17035345                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           148314                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          469.091453                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6019898                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           148666                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            40.492769                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     106291978000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.091453                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.916194                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.916194                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.673828                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12441829                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12441829                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3018165                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3018165                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2685196                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2685196                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41245                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        41245                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69563                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        69563                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61182                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61182                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5703361                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5703361                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5744606                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5744606                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       110713                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       110713                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        77621                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        77621                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23905                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        23905                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16417                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16417                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23076                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23076                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       188334                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        188334                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       212239                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       212239                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1730591500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1730591500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2713528000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2713528000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    316809000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    316809000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    632764000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    632764000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3307000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3307000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4444119500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4444119500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4444119500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4444119500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3128878                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3128878                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2762817                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2762817                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        65150                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        65150                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        85980                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        85980                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84258                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        84258                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      5891695                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      5891695                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      5956845                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      5956845                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035384                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035384                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028095                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.028095                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.366922                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.366922                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190940                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190940                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.273873                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273873                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031966                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031966                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035629                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035629                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           33                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12680697                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12680697                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3066133                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3066133                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2748576                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2748576                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41842                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        41842                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69851                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        69851                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61610                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61610                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5814709                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5814709                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5856551                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5856551                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       112800                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       112800                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        79377                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        79377                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24461                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        24461                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16636                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16636                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23088                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23088                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       192177                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        192177                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       216638                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       216638                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1758096000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1758096000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2710284000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2710284000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320294000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    320294000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    628163500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    628163500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3848000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3848000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4468380000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4468380000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4468380000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4468380000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3178933                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3178933                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2827953                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2827953                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66303                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        66303                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86487                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        86487                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84698                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        84698                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6006886                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6006886                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6073189                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6073189                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035484                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.035484                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028069                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.028069                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.368927                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.368927                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.192353                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.192353                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.272592                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.272592                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031993                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031993                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035671                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035671                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1624,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       144073                       # number of writebacks
-system.cpu1.dcache.writebacks::total           144073                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          168                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11530                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11530                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          168                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          168                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          168                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110545                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       110545                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        77621                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        77621                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23508                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23508                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4887                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4887                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23076                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23076                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       188166                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       188166                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       211674                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       211674                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3107                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3107                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2430                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2430                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5537                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5537                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1611627000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1611627000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2635907000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2635907000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    421753500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    421753500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88480500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88480500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    609718000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    609718000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3277000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3277000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4247534000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4247534000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4669287500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4669287500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    430617000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    430617000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    292641500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    292641500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    723258500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    723258500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035331                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035331                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028095                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028095                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.360829                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.360829                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056839                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056839                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.273873                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273873                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031937                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031937                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035535                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035535                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       148314                       # number of writebacks
+system.cpu1.dcache.writebacks::total           148314                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          199                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          199                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11732                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11732                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          199                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          199                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          199                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          199                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       112601                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       112601                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79377                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        79377                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        24003                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        24003                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4904                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4904                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23088                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23088                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       191978                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       191978                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       215981                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       215981                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3083                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3083                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2425                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2425                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5508                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5508                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1635811500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1635811500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2630907000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2630907000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    431572500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    431572500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89921000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89921000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    605110500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    605110500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3813000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3813000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4266718500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4266718500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4698291000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4698291000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439541500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439541500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    303268000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    303268000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742809500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742809500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035421                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035421                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028069                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028069                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.362020                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.362020                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056702                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056702                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.272592                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.272592                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031960                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031960                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035563                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035563                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           461792                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.311266                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           13251136                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           462304                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            28.663252                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     106195905000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.311266                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973264                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973264                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           463432                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.310833                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           13456384                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           463944                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            29.004328                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     106360036500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.310833                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973263                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.973263                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         27889184                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        27889184                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     13251136                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       13251136                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     13251136                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        13251136                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     13251136                       # number of overall hits
-system.cpu1.icache.overall_hits::total       13251136                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       462304                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       462304                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       462304                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        462304                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       462304                       # number of overall misses
-system.cpu1.icache.overall_misses::total       462304                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4149723500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4149723500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4149723500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4149723500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4149723500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4149723500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13713440                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13713440                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13713440                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13713440                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13713440                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13713440                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033712                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.033712                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033712                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.033712                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033712                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.033712                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8976.179094                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8976.179094                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8976.179094                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8976.179094                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8976.179094                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8976.179094                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         28304600                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        28304600                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     13456384                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       13456384                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     13456384                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        13456384                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     13456384                       # number of overall hits
+system.cpu1.icache.overall_hits::total       13456384                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       463944                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       463944                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       463944                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        463944                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       463944                       # number of overall misses
+system.cpu1.icache.overall_misses::total       463944                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4214272500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4214272500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4214272500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4214272500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4214272500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4214272500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13920328                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13920328                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13920328                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13920328                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13920328                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13920328                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033329                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.033329                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033329                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.033329                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033329                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.033329                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9083.580130                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9083.580130                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9083.580130                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9083.580130                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9083.580130                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9083.580130                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1773,437 +1778,448 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       461792                       # number of writebacks
-system.cpu1.icache.writebacks::total           461792                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       462304                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       462304                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       462304                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       462304                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       462304                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       462304                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       463432                       # number of writebacks
+system.cpu1.icache.writebacks::total           463432                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463944                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       463944                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       463944                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       463944                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       463944                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       463944                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3918571500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3918571500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3918571500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3918571500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3918571500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3918571500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3982300500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3982300500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3982300500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3982300500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3982300500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3982300500                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23546500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     23546500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033712                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.033712                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.033712                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8476.179094                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8476.179094                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8476.179094                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033329                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.033329                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.033329                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8583.580130                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8583.580130                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8583.580130                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       106104                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       106112                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       118303                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       118321                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           16                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        50448                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           30131                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14949.290291                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1034569                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           45193                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           22.892240                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        50079                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           31154                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14935.857031                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1041086                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           46286                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           22.492460                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.312401                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.041451                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   430.459574                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.885893                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000141                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000125                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026273                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.912432                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          971                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14059                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           54                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          913                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.202140                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.081939                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   484.280848                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.881732                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000195                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.029558                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.911612                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          981                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           38                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14113                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           47                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          926                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           27                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          390                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1365                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12304                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059265                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001953                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.858093                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        20957142                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       20957142                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2443                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1453                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total          3896                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks        89055                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total        89055                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       506752                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       506752                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        16650                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        16650                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       453968                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       453968                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        75407                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        75407                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2443                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1453                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       453968                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data        92057                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         549921                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2443                       # number of overall hits
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-system.cpu1.l2cache.ReadReq_misses::total          650                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28928                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28928                       # number of UpgradeReq misses
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-system.cpu1.l2cache.SCUpgradeReq_misses::total        23076                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32043                       # number of ReadExReq misses
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-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8336                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total         8336                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63533                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        63533                       # number of ReadSharedReq misses
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-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7078500                       # number of ReadReq miss cycles
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-system.cpu1.l2cache.ReadReq_miss_latency::total     13100000                       # number of ReadReq miss cycles
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-system.cpu1.l2cache.UpgradeReq_miss_latency::total     62132500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59033500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59033500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3231500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3231500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1646554500                       # number of ReadExReq miss cycles
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-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    475139500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    475139500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1418811000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1418811000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7078500                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3065365500                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7078500                       # number of overall miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3065365500                       # number of overall miss cycles
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-system.cpu1.l2cache.WritebackDirty_accesses::writebacks        89055                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total        89055                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       506752                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       506752                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28928                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        28928                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23076                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23076                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       462304                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       462304                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       138940                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       138940                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2792                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.142983                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1668                       # Occupied blocks per task id
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+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059875                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002319                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.861389                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        21151055                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       21151055                       # Number of data accesses
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+system.cpu1.l2cache.WritebackDirty_accesses::total        92001                       # number of WritebackDirty accesses(hits+misses)
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 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.658062                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.658062                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018031                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018031                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.457269                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.457269                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018031                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.509377                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.159763                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018031                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.509377                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.159763                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2147.832550                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2147.832550                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2558.220662                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2558.220662                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           32                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.639255                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.639255                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019198                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019198                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.451423                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.451423                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.124153                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.169109                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019198                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.500756                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.159980                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.124153                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.169109                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019198                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.500756                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.159980                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20162.808642                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2219.376661                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2219.376661                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2377.939966                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2377.939966                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3760000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3760000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50917.150306                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50917.150306                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59553.834063                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59553.834063                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22480.612085                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22480.612085                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59553.834063                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32014.890584                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 34263.785303                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59553.834063                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32014.890584                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 34263.785303                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        25259                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           25259                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           80                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total           80                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data           80                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data           80                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          349                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          301                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          650                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        18771                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        18771                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28928                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28928                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23076                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23076                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31963                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31963                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8336                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8336                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63533                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63533                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          349                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          301                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         8336                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        95496                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       104482                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          349                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          301                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         8336                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        95496                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        18771                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       123253                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        25848                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           25848                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           72                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        21105                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        21105                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28973                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28973                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23087                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23087                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8907                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8907                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63880                       # number of ReadSharedReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3107                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3284                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2430                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2430                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3083                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3260                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2425                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2425                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5537                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5714                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9200000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    917123117                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    917123117                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    588451500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    588451500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    436537000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    436537000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3051500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3051500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1446140000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1446140000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    425123500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    425123500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1037613000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1037613000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    425123500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2483753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2918076500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    425123500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2483753000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    917123117                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   3835199617                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5508                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5685                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9177500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    934365172                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    934365172                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    576596500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    576596500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    431875500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    431875500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3550000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3550000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1440609000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1440609000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    477004000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    477004000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1052781500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1052781500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    477004000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2493390500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2979572000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    477004000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2493390500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    934365172                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   3913937172                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    405408000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    427627000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    274409000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    274409000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414529000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436748000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    285072000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    285072000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    679817000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    702036000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.142983                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    699601000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    721820000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.141577                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.656419                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.656419                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018031                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.457269                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.457269                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.508951                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159641                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.508951                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637826                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637826                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019198                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.451423                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451423                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.500380                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159871                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.500380                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.188321                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191827                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3550000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3550000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1312846                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       662941                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10057                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       166384                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       164278                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2106                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         10119                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       648543                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2430                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2430                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       115438                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       506752                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        85166                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        22864                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        70245                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40855                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84598                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        55915                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        53326                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       462304                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       211564                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           31                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1378500                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707096                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4372                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7009                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2096977                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58614596                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     23813135                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7016                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          82445915                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     350196                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples       987919                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.185835                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.394416                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1324645                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       668824                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10099                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       169409                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       166956                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2453                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         10097                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       652790                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2425                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2425                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       119017                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       519745                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        86537                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        25449                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        70337                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40896                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        84740                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           48                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57665                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        55147                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       463944                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       215084                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           32                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1391674                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       722021                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4392                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7022                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2125109                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     59352772                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24485096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11212                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          83856176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     356096                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples       999531                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.187033                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.396182                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            806435     81.63%     81.63% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            179378     18.16%     99.79% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              2106      0.21%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            815039     81.54%     81.54% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            182039     18.21%     99.75% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              2453      0.25%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total        987919                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1267256999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total        999531                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1279051999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79126203                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79434008                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    693633000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    696093000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    311803500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    318231000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu1.toL2Bus.respLayer2.occupancy      2618000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      4217000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      4219000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
@@ -2226,9 +2242,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180868                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180892                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
@@ -2249,14 +2265,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2483990                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             48738000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2484086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             48746500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               322000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                32500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
@@ -2264,7 +2280,7 @@ system.iobus.reqLayer4.occupancy                16000                       # La
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer7.occupancy                93500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy               610000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               609000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               23500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
@@ -2274,7 +2290,7 @@ system.iobus.reqLayer14.occupancy               11500                       # La
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
@@ -2286,54 +2302,54 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6150500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6162500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            32045500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           186301036                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187117449                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36433                       # number of replacements
-system.iocache.tags.tagsinuse                1.018273                       # Cycle average of tags in use
+system.iocache.tags.replacements                36461                       # number of replacements
+system.iocache.tags.tagsinuse               14.380044                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         290654223000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.018273                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.063642                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.063642                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         290746348000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.380044                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.898753                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.898753                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
-system.iocache.tags.data_accesses              328203                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
+system.iocache.tags.data_accesses              328311                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          243                       # number of overall misses
-system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31405376                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31405376                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4738596660                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4738596660                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31405376                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31405376                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31405376                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31405376                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          255                       # number of overall misses
+system.iocache.overall_misses::total              255                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     32874877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32874877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4582462572                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4582462572                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32874877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32874877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32874877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32874877                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2342,40 +2358,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129240.230453                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129240.230453                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129240.230453                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129240.230453                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129240.230453                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           816                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128921.086275                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128921.086275                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128921.086275                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128921.086275                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128921.086275                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            19                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   79                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.329114                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     6.333333                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           36206                       # number of writebacks
+system.iocache.writebacks::total                36206                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19255376                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19255376                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2927396660                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2927396660                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19255376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19255376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19255376                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19255376                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20124877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20124877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2769551646                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2769551646                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     20124877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     20124877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     20124877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     20124877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2384,304 +2400,303 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 79240.230453                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 79240.230453                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 78921.086275                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 78921.086275                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   123618                       # number of replacements
-system.l2c.tags.tagsinuse                63093.840837                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     421259                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   187589                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.245649                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   123661                       # number of replacements
+system.l2c.tags.tagsinuse                63058.402721                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     421257                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   187718                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.244095                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13244.114990                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.878668                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.996497                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7731.277102                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2849.874177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954483                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1120.568935                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      367.321258                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1502.766604                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.202089                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000059                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.553468                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_blocks::cpu0.inst     7361.006580                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2805.566875                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954518                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1443.499308                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1814.508588                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        31859                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          131                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4716                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        27259                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2381                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        29068                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.489914                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.486130                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5836461                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5836461                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       257531                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          257531                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           32441                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1723                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               34164                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2115                       # number of SCUpgradeReq hits
+system.l2c.tags.occ_percent::cpu1.inst       0.022026                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1024        32009                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1022::3         5120                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        26618                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2          402                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2325                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        29253                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.488953                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.488419                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  5830329                       # Number of tag accesses
+system.l2c.tags.data_accesses                 5830329                       # Number of data accesses
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+system.l2c.WritebackDirty_hits::total          257370                       # number of WritebackDirty hits
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 system.l2c.SCUpgradeReq_hits::cpu1.data           899                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              3014                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4177                       # number of ReadExReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           81                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           92                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        28642                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        47295                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu1.data         4707                       # number of ReadSharedReq hits
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 system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
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 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
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+system.l2c.overall_miss_latency::cpu1.inst    313582000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1130739500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    857081845                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    27000838623                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       257370                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       257370                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        41649                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4173                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           45822                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2631                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2207                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          4838                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15229                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9162                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24391                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          100                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           74                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        46212                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        55659                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       182130                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           21                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           13                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst         8907                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data         5869                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8874                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       307859                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          100                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           74                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           46212                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           70888                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       182130                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           21                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           13                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst            8907                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           15031                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8874                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              332250                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          100                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           74                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          46212                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          70888                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       182130                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           21                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           13                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst           8907                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          15031                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8874                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             332250                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.225360                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.538941                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.253917                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.223109                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.592660                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.391691                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.729792                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.848832                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.774507                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.378754                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159471                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.265409                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.136991                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.550840                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.378754                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.281994                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.265409                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.570887                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.567260                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.378754                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.281994                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.265409                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.570887                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.567260                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3222.672065                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2313.472655                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  3046.927374                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6535.775128                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2084.097859                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3463.060686                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145769.929818                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130850.520766                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 139627.944524                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       135400                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       181000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131523.224590                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136244.592159                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       146500                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132648.900169                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140690.298507                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 143666.608423                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135400                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker       181000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 131523.224590                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 141540.470235                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       146500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 132648.900169                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 131772.462417                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 143261.803467                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       135400                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker       181000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 131523.224590                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 141540.470235                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       146500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 132648.900169                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 131772.462417                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 143261.803467                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2690,274 +2705,270 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               97095                       # number of writebacks
-system.l2c.writebacks::total                    97095                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           17                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 17                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                17                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         2818                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         2818                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9610                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2300                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11910                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          655                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1322                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1977                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11124                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         7851                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         18975                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            6                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks               96987                       # number of writebacks
+system.l2c.writebacks::total                    96987                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         2809                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         2809                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         9386                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2249                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11635                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          587                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1308                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1895                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        11114                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         7777                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         18891                       # number of ReadExReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            5                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17851                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8886                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134682                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17501                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8876                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134571                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2010                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          752                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5338                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       169528                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2357                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          804                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5455                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       169572                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        17851                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        20010                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134682                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        17501                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        19990                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134571                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2010                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         8603                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5338                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           188503                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker            6                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2357                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8581                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5455                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           188463                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker            5                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        17851                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        20010                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134682                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        17501                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        19990                       # number of overall MSHR misses
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 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
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-system.l2c.WriteReq_mshr_uncacheable::total        30983                       # number of WriteReq MSHR uncacheable
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    172861000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    897933500                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5812758500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5801306000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    349483000                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4715021500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    233050000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4948071500                       # number of WriteReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10527780000                       # number of overall MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    582533000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12153160500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    602849501                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12149519501                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.228532                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.571713                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.258497                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.236462                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.595227                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.396113                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.727011                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.854019                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.774680                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158165                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.137754                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.551743                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.279927                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.587155                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.568203                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.279927                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.587155                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.568203                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 133198.349040                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 133198.349040                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.225360                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.538941                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.253917                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.223109                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.592660                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.391691                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.729792                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.848832                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.774507                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159471                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.136991                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.550811                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.281994                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.570887                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.567233                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.281994                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.570887                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.567233                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 133263.982012                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 133263.982012                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               44163                       # Transaction distribution
-system.membus.trans_dist::ReadResp             213934                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30983                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30983                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       133285                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14406                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            73490                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          39839                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13966                       # Transaction distribution
+system.membus.trans_dist::ReadReq               44099                       # Transaction distribution
+system.membus.trans_dist::ReadResp             213926                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30924                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30924                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       133193                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14771                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            73670                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          39871                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39499                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18896                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        169771                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39385                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            18791                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        169827                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664172                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       786162                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108909                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108909                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 895071                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13776                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       650336                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       772080                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72955                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72955                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 845035                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18307596                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18498522                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20815642                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           120564                       # Total snoops (count)
-system.membus.snoop_fanout::samples            581920                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18297804                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18488238                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20806382                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           121083                       # Total snoops (count)
+system.membus.snoop_fanout::samples            581994                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  581920    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  581994    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              581920                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88268000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              581994                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88286500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11611500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11391000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           967762037                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           968108262                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1134685490                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1106274782                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64105002                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1388877                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3000,52 +3011,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       959770                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       518663                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       138023                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20272                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        19432                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          840                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              44166                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            467162                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30983                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30983                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       390842                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           84262                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          107575                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         42853                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         150428                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50605                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50605                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       423011                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       960339                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       518534                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       139328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20435                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        19626                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          809                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              44102                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            468032                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30924                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30924                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       390589                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105128                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          107757                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         42814                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         150571                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           82                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50426                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50426                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       423945                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1226424                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       245800                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1472224                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34332563                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3643847                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               37976410                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          437847                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           895583                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.335708                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.474219                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1240075                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       253445                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1493520                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34222158                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3776032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               37998190                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          438746                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           896439                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.337268                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.474682                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 595769     66.52%     66.52% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 298974     33.38%     99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    840      0.09%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 594908     66.36%     66.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 300722     33.55%     99.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    809      0.09%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             895583                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          863469481                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             896439                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          863728414                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           342622                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           360123                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         647119226                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         645946273                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         200312901                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         202615858                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index b6b1f5126..913ae877a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,83 +1,83 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.909596                       # Number of seconds simulated
-sim_ticks                                2909596171500                       # Number of ticks simulated
-final_tick                               2909596171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.909587                       # Number of seconds simulated
+sim_ticks                                2909586837500                       # Number of ticks simulated
+final_tick                               2909586837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 322522                       # Simulator instruction rate (inst/s)
-host_op_rate                                   388861                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8344730622                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560756                       # Number of bytes of host memory used
-host_seconds                                   348.67                       # Real time elapsed on the host
-sim_insts                                   112455206                       # Number of instructions simulated
-sim_ops                                     135585876                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 929184                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1120306                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24040663881                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 581600                       # Number of bytes of host memory used
+host_seconds                                   121.03                       # Real time elapsed on the host
+sim_insts                                   112457033                       # Number of instructions simulated
+sim_ops                                     135588117                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1186404                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8901796                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1186532                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8901860                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10089736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1186404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1186404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7511872                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10089928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1186532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1186532                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7512000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7529396                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7529524                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26991                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139610                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26993                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139611                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166625                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117373                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                166628                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117375                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121754                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121756                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               407756                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3059461                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               407801                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3059493                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3467744                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          407756                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             407756                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2581758                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3467822                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          407801                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             407801                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2581810                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6023                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2587780                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2581758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2587833                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2581810                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              407756                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3065484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              407801                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3065516                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6055525                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166625                       # Number of read requests accepted
-system.physmem.writeReqs                       121754                       # Number of write requests accepted
-system.physmem.readBursts                      166625                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121754                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10656448                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7541952                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10089736                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7529396                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6055654                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166628                       # Number of read requests accepted
+system.physmem.writeReqs                       121756                       # Number of write requests accepted
+system.physmem.readBursts                      166628                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121756                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10657408                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7542016                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10089928                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7529524                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          47113                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10077                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10695                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10661                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10660                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18797                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9659                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9663                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10485                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9664                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9666                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10487                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                9973                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               9232                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               8679                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9817                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9822                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10379                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9722                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9723                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
@@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::3                8171                       # Pe
 system.physmem.perBankWrBursts::4                7489                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7659                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7661                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               6695                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7534                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7533                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2909595814500                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2909586480500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157053                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157056                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117373                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    165628                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117375                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    165639                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       614                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,117 +159,114 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5923                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6296                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58778                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      309.611351                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.749688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.493771                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21450     36.49%     36.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14701     25.01%     61.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6086     10.35%     71.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3214      5.47%     77.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2550      4.34%     81.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1476      2.51%     84.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1054      1.79%     85.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1089      1.85%     87.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7158     12.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58778                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5758                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.915596                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      590.311059                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5757     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5904                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6826                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6035                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      197                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58742                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      309.818528                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     182.858167                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.750191                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21399     36.43%     36.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14737     25.09%     61.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6061     10.32%     71.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3228      5.50%     77.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2535      4.32%     81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1458      2.48%     84.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1057      1.80%     85.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1079      1.84%     87.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7188     12.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58742                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5615                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.654497                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      597.763680                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5614     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5758                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5758                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.465960                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.711564                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.116644                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4961     86.16%     86.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              87      1.51%     87.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              33      0.57%     88.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             172      2.99%     91.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              23      0.40%     91.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             160      2.78%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              50      0.87%     95.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.10%     95.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               7      0.12%     95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              22      0.38%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.03%     95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.10%     96.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             163      2.83%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               3      0.05%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              10      0.17%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.35%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.03%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            16      0.28%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5758                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1616458000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4738464250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    832535000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9708.05                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5615                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5615                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.987355                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.791633                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.100649                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4949     88.14%     88.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              78      1.39%     89.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              32      0.57%     90.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              46      0.82%     90.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              24      0.43%     91.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              20      0.36%     91.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              46      0.82%     92.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               4      0.07%     92.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             153      2.72%     95.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              11      0.20%     95.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.12%     95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              13      0.23%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              63      1.12%     96.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.09%     97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.09%     97.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.46%     97.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             103      1.83%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.04%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.14%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.12%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.07%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5615                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1624802000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4747089500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    832610000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9757.28                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28458.05                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28507.28                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
@@ -280,39 +277,39 @@ system.physmem.busUtilRead                       0.03                       # Da
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     136072                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89499                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.72                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10089485.76                       # Average gap between requests
-system.physmem.pageHitRate                      79.32                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  230958000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  126018750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 702124800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                392882400                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            90366604425                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1666484751750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1948343566605                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.628332                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2772164122000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     97157580000                       # Time in different power states
+system.physmem.readRowHits                     136095                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89528                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.73                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.96                       # Row buffer hit rate for writes
+system.physmem.avgGap                     10089278.46                       # Average gap between requests
+system.physmem.pageHitRate                      79.34                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  230829480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125948625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 702195000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392895360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           190039717920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            90325761075                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1666515907500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1948333254960                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.626580                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2772215900000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     97157320000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     40267816750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     40208512500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  213403680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116440500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 596622000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370740240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            88072375230                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1668497233500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1947907041630                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.478302                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2775541834250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     97157580000                       # Time in different power states
+system.physmem_1.actEnergy                  213260040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116362125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 596668800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                370733760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           190039717920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            88049301345                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1668512802000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1947898845990                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.477277                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2775567504000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     97157320000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     36896609250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     36861865500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -370,9 +367,9 @@ system.cpu.dtb.walker.walkWaitTime::samples         9546                       #
 system.cpu.dtb.walker.walkWaitTime::0            9546    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::total         9546                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkCompletionTime::samples         7382                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8540.848722                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8541.710442                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::0-32767         7377     99.93%     99.93% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
@@ -392,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7382
 system.cpu.dtb.walker.walkRequestOrigin::total        16928                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24520178                       # DTB read hits
+system.cpu.dtb.read_hits                     24520655                       # DTB read hits
 system.cpu.dtb.read_misses                       8124                       # DTB read misses
-system.cpu.dtb.write_hits                    19606457                       # DTB write hits
+system.cpu.dtb.write_hits                    19606816                       # DTB write hits
 system.cpu.dtb.write_misses                      1422                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -405,12 +402,12 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1650                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24528302                       # DTB read accesses
-system.cpu.dtb.write_accesses                19607879                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24528779                       # DTB read accesses
+system.cpu.dtb.write_accesses                19608238                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44126635                       # DTB hits
+system.cpu.dtb.hits                          44127471                       # DTB hits
 system.cpu.dtb.misses                            9546                       # DTB misses
-system.cpu.dtb.accesses                      44136181                       # DTB accesses
+system.cpu.dtb.accesses                      44137017                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -468,7 +465,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    115552414                       # ITB inst hits
+system.cpu.itb.inst_hits                    115554258                       # ITB inst hits
 system.cpu.itb.inst_misses                       4763                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -485,40 +482,40 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                115557177                       # ITB inst accesses
-system.cpu.itb.hits                         115552414                       # DTB hits
+system.cpu.itb.inst_accesses                115559021                       # ITB inst accesses
+system.cpu.itb.hits                         115554258                       # DTB hits
 system.cpu.itb.misses                            4763                       # DTB misses
-system.cpu.itb.accesses                     115557177                       # DTB accesses
-system.cpu.numCycles                       5819192343                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     115559021                       # DTB accesses
+system.cpu.numCycles                       5819173675                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
-system.cpu.committedInsts                   112455206                       # Number of instructions committed
-system.cpu.committedOps                     135585876                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             119891340                       # Number of integer alu accesses
+system.cpu.committedInsts                   112457033                       # Number of instructions committed
+system.cpu.committedOps                     135588117                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119893391                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
-system.cpu.num_func_calls                     9892021                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15230391                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    119891340                       # number of integer instructions
+system.cpu.num_func_calls                     9892146                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15230571                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119893391                       # number of integer instructions
 system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218059811                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           82644916                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           218063465                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82646448                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            489735153                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            51893214                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      45407055                       # number of memory refs
-system.cpu.num_load_insts                    24842618                       # Number of load instructions
-system.cpu.num_store_insts                   20564437                       # Number of store instructions
-system.cpu.num_idle_cycles               5379072985.844151                       # Number of idle cycles
-system.cpu.num_busy_cycles               440119357.155849                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.075632                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.924368                       # Percentage of idle cycles
-system.cpu.Branches                          25916470                       # Number of branches fetched
+system.cpu.num_cc_register_reads            489743456                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51893999                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45407924                       # number of memory refs
+system.cpu.num_load_insts                    24843119                       # Number of load instructions
+system.cpu.num_store_insts                   20564805                       # Number of store instructions
+system.cpu.num_idle_cycles               5379054575.844151                       # Number of idle cycles
+system.cpu.num_busy_cycles               440119099.155849                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.075633                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.924367                       # Percentage of idle cycles
+system.cpu.Branches                          25916787                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  93173703     67.17%     67.18% # Class of executed instruction
-system.cpu.op_class::IntMult                   114388      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93175095     67.17%     67.18% # Class of executed instruction
+system.cpu.op_class::IntMult                   114406      0.08%     67.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
@@ -546,18 +543,18 @@ system.cpu.op_class::SimdFloatMisc               8453      0.01%     67.26% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::MemRead                 24842618     17.91%     85.17% # Class of executed instruction
-system.cpu.op_class::MemWrite                20564437     14.83%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 24843119     17.91%     85.17% # Class of executed instruction
+system.cpu.op_class::MemWrite                20564805     14.83%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  138705936                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            819217                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.702336                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43235406                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819729                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             52.743536                       # Average number of references to valid blocks.
+system.cpu.op_class::total                  138708215                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            819223                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.702328                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            43236235                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819735                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.744161                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1736147500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.702336                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.702328                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999419                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999419                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -566,152 +563,152 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          344
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         177109321                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        177109321                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23112521                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23112521                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18823879                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18823879                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       392783                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        392783                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443242                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443242                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460216                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460216                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41936400                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41936400                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42329183                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42329183                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       399911                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        399911                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       298704                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       298704                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       118377                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       118377                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22757                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22757                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         177112671                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177112671                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23112983                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23112983                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18824226                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18824226                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392786                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392786                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443250                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443250                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460223                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460223                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41937209                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41937209                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42329995                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42329995                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       399912                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        399912                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       298709                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       298709                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       118381                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       118381                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22756                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22756                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       698615                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         698615                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       816992                       # number of overall misses
-system.cpu.dcache.overall_misses::total        816992                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   6486417000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   6486417000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  19109109000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  19109109000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    294489000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    294489000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       698621                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         698621                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       817002                       # number of overall misses
+system.cpu.dcache.overall_misses::total        817002                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   6488404500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   6488404500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19100944000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19100944000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    293896000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    293896000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  25595526000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  25595526000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  25595526000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  25595526000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23512432                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23512432                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19122583                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19122583                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511160                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511160                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465999                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465999                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460218                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460218                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42635015                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42635015                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43146175                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43146175                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  25589348500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  25589348500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  25589348500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  25589348500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23512895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23512895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19122935                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19122935                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511167                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511167                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466006                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466006                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460225                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42635830                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42635830                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43146997                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43146997                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017008                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.017008                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015620                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.015620                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231585                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.231585                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048835                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048835                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231590                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.231590                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048832                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048832                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.016386                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.018935                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.018935                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709                       # average LoadLockedReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36637.527107                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31328.979966                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36628.370032                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31321.035322                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          100                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       683842                       # number of writebacks
-system.cpu.dcache.writebacks::total            683842                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          930                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          930                       # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14247                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14247                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          930                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          930                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          930                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          930                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398981                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       398981                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298704                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298704                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116321                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       116321                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       683846                       # number of writebacks
+system.cpu.dcache.writebacks::total            683846                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          929                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          929                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14246                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14246                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          929                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          929                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          929                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          929                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398983                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       398983                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298709                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298709                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116322                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       116322                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8510                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total         8510                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       697685                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       697685                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       814006                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       814006                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       697692                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       697692                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       814014                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       814014                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6058107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6058107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18810405000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18810405000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1614233500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1614233500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6058749500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6058749500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18802235000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18802235000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1616519000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1616519000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115353500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115353500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24868512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24868512000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26482745500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26482745500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278172000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278172000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089977500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089977500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368149500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368149500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24860984500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24860984500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26477503500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26477503500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278149500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278149500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089976500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089976500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368126000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368126000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016969                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016969                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015620                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227563                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227563                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227562                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227562                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018262                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018262                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
@@ -720,34 +717,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016364
 system.cpu.dcache.demand_mshr_miss_rate::total     0.016364                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018866                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.018866                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1695565                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.436866                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           113856331                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1696077                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.129223                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1695721                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.436852                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113858019                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1696233                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.124044                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       29070355500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.436866                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.436852                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.996947                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -756,44 +753,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          195
 system.cpu.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         117248497                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        117248497                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    113856331                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113856331                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     113856331                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        113856331                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    113856331                       # number of overall hits
-system.cpu.icache.overall_hits::total       113856331                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1696083                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1696083                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1696083                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1696083                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1696083                       # number of overall misses
-system.cpu.icache.overall_misses::total       1696083                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  24267960000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  24267960000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  24267960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  24267960000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  24267960000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  24267960000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    115552414                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    115552414                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    115552414                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    115552414                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    115552414                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    115552414                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014678                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014678                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014678                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014678                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014678                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014678                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14308.238453                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14308.238453                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         117250497                       # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst  24272134000                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14309.383289                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -802,218 +799,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
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-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014678                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average overall mshr miss latency
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 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            87562                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64865.195753                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4544223                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           152797                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            29.740263                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87565                       # number of replacements
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+system.cpu.l2cache.tags.total_refs            4544536                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           152800                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            29.741728                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012652                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9701.731977                       # Average occupied blocks per requestor
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1857500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      1857500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1793500                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       159000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16383348000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2349142000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1612524000                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1615422500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       957500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       266000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2349142000                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       957500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       266000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2349142000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  17995872000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20346237500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7817                       # number of ReadReq accesses(hits+misses)
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 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4041                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        11858                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       683842                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       683842                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1664795                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1664795                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2763                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2763                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.WritebackDirty_accesses::writebacks       683846                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.WritebackClean_accesses::writebacks      1664945                       # number of WritebackClean accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2765                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::total      1696050                       # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.ReadSharedReq_accesses::total       523812                       # number of ReadSharedReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.itb.walker         4041                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1696050                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7817                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.itb.walker         4041                       # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::total      2527661                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000495                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.000759                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991676                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991676                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991682                       # miss rate for UpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.435610                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010599                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010599                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023237                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023237                       # miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000495                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010599                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172109                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.062932                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for overall accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000495                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010599                       # miss rate for overall accesses
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 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   677.919708                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   677.919708                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   654.084610                       # average UpgradeReq miss latency
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1022,31 +1019,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        81183                       # number of writebacks
-system.cpu.l2cache.writebacks::total            81183                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        81185                       # number of writebacks
+system.cpu.l2cache.writebacks::total            81185                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2740                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2740                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2742                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2742                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128915                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       128915                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17976                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17976                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12172                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12172                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        17976                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141087                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       159072                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.data       141086                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       159073                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        17976                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141087                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       159072                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        17978                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141086                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       159073                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
@@ -1058,139 +1055,139 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       887500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       246000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1133500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    194003500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    194003500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186544500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186544500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       139000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15094198000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15094198000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2169382000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2169382000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1490804000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1490804000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15093428000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15093428000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2171514500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2171514500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1493692500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1493692500                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       887500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2169382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16585002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  18755517500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2171514500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16587120500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  18759768500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       887500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       246000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2169382000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16585002000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  18755517500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2171514500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16587120500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18759768500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888826500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918592500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772574000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772574000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888804000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918570000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772572500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772572500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661400500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691166500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661376500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691142500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000759                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991676                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991676                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991682                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435610                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435610                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435599                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435599                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023237                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023237                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023239                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023239                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.062932                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172107                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062929                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.062932                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172107                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062929                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5052537                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536723                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38125                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5052863                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536887                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38132                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          581                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq          67213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2287321                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2287480                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       801217                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1664795                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       134627                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2763                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       801231                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1695721                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       141985                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2765                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696083                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       524040                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2767                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295944                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295944                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696239                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       524043                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5074972                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574565                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5106210                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581942                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13257                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25654                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7688448                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215130168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96426845                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25651                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7727060                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217119416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96427485                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16164                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31268                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          311604445                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      175875                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2773837                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.020867                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.142939                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313594321                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      175889                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2774012                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.020868                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.142944                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2715955     97.91%     97.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              57882      2.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2716123     97.91%     97.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              57889      2.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2773837                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4957294000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2774012                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4957617000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       380876                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2553146500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2553380500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1275944500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1275954500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
@@ -1246,7 +1243,7 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46338000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46336500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1280,25 +1277,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6287500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6279500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           186221548                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187058527                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36418                       # number of replacements
-system.iocache.tags.tagsinuse                1.084130                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084082                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         313812613000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.084130                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067758                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067758                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         313812610000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.084082                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067755                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067755                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1312,14 +1309,14 @@ system.iocache.demand_misses::realview.ide          228                       #
 system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          228                       # number of overall misses
 system.iocache.overall_misses::total              228                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28228376                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28228376                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4717653172                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4717653172                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28228376                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28228376                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28228376                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28228376                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28180377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28180377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4549133150                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4549133150                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28180377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28180377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28180377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28180377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1336,19 +1333,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123808.666667                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123808.666667                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123808.666667                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           910                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123598.144737                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123598.144737                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123598.144737                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   81                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.234568                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1362,14 +1359,14 @@ system.iocache.demand_mshr_misses::realview.ide          228
 system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16828376                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16828376                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2906453172                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2906453172                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16828376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16828376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16828376                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16828376                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16780377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16780377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736521626                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2736521626                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16780377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16780377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16780377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16780377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1378,68 +1375,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70545                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70548                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117373                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6392                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117375                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6608                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4499                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            127158                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           127158                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         30385                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30388                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       438817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       546409                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 655303                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       434329                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       541921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72885                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72885                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 614806                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465365                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302332                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465685                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17782485                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17782805                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              492                       # Total snoops (count)
-system.membus.snoop_fanout::samples            389997                       # Request fanout histogram
+system.membus.snoop_fanout::samples            390011                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  389997    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  390011    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              389997                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90470000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              390011                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90460500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1726000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1730500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           823068661                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           823136860                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          952238748                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          943248500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64113741                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1186623                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index db18bd84f..e0084d588 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,73 +1,73 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.783867                       # Number of seconds simulated
-sim_ticks                                2783867052000                       # Number of ticks simulated
-final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.783855                       # Number of seconds simulated
+sim_ticks                                2783854535000                       # Number of ticks simulated
+final_tick                               2783854535000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 540105                       # Simulator instruction rate (inst/s)
-host_op_rate                                   657491                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10531274508                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560892                       # Number of bytes of host memory used
-host_seconds                                   264.34                       # Real time elapsed on the host
-sim_insts                                   142772879                       # Number of instructions simulated
-sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1278958                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1556926                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24937950041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 579412                       # Number of bytes of host memory used
+host_seconds                                   111.63                       # Real time elapsed on the host
+sim_insts                                   142771651                       # Number of instructions simulated
+sim_ops                                     173801592                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           725796                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4660896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           724196                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4660000                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           481216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5663620                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           482816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5664516                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             11533000                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       725796                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       481216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       724196                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       482816                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1207012                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8840512                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      8840576                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8858036                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8858100                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             19794                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73345                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             19769                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73331                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7519                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             88495                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7544                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             88509                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                189176                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138133                       # Number of write requests responded to by this memory
+system.physmem.num_writes::writebacks          138134                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142514                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142515                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker           115                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              260715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1674252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              260141                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1673938                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              172859                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2034443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              173434                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2034774                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4142798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         260715                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         172859                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             433574                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3175623                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4142817                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         260141                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         173434                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3175660                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6292                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3181918                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3175623                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3181955                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3175660                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker          115                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             260715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1680544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             260141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1680230                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             172859                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2034446                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             173434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2034777                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7324716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7324772                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     5683                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                5683                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         5683                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           5683    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         5683                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                     5703                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                5703                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         5703                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           5703    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         5703                       # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3049     65.40%     65.40% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1613     34.60%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4662                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5683                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         3075     65.68%     65.68% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1607     34.32%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4682                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5703                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5683                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4662                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5703                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4682                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4662                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        10345                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4682                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        10385                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    15994593                       # DTB read hits
-system.cpu0.dtb.read_misses                      4788                       # DTB read misses
-system.cpu0.dtb.write_hits                   11285810                       # DTB write hits
-system.cpu0.dtb.write_misses                      895                       # DTB write misses
+system.cpu0.dtb.read_hits                    15997085                       # DTB read hits
+system.cpu0.dtb.read_misses                      4809                       # DTB read misses
+system.cpu0.dtb.write_hits                   11281852                       # DTB write hits
+system.cpu0.dtb.write_misses                      894                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        2813                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     394                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3234                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3232                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   773                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   770                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      200                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                15999381                       # DTB read accesses
-system.cpu0.dtb.write_accesses               11286705                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      202                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                16001894                       # DTB read accesses
+system.cpu0.dtb.write_accesses               11282746                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         27280403                       # DTB hits
-system.cpu0.dtb.misses                           5683                       # DTB misses
-system.cpu0.dtb.accesses                     27286086                       # DTB accesses
+system.cpu0.dtb.hits                         27278937                       # DTB hits
+system.cpu0.dtb.misses                           5703                       # DTB misses
+system.cpu0.dtb.accesses                     27284640                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -184,206 +184,206 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     2611                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2611                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2611                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2611    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2611                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                     2590                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2590                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2590                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2590    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2590                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0        6702500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1374     72.85%     72.85% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          512     27.15%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         1886                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         1366     72.81%     72.81% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          510     27.19%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1876                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2611                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2611                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2590                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2590                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1886                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1886                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4497                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    74779098                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2611                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1876                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1876                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4466                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    74797685                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2590                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        2813                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     394                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     403                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1917                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1907                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                74781709                       # ITB inst accesses
-system.cpu0.itb.hits                         74779098                       # DTB hits
-system.cpu0.itb.misses                           2611                       # DTB misses
-system.cpu0.itb.accesses                     74781709                       # DTB accesses
-system.cpu0.numCycles                      5536444792                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74800275                       # ITB inst accesses
+system.cpu0.itb.hits                         74797685                       # DTB hits
+system.cpu0.itb.misses                           2590                       # DTB misses
+system.cpu0.itb.accesses                     74800275                       # DTB accesses
+system.cpu0.numCycles                      5536444787                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3083                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   72626333                       # Number of instructions committed
-system.cpu0.committedOps                     87972335                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             77485858                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5256                       # Number of float alu accesses
-system.cpu0.num_func_calls                    8692525                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      9458276                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    77485858                       # number of integer instructions
-system.cpu0.num_fp_insts                         5256                       # number of float instructions
-system.cpu0.num_int_register_reads          144065688                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          54441738                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                4098                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1160                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           268855171                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           31825079                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     27911721                       # number of memory refs
-system.cpu0.num_load_insts                   16162181                       # Number of load instructions
-system.cpu0.num_store_insts                  11749540                       # Number of store instructions
-system.cpu0.num_idle_cycles              5353607317.458248                       # Number of idle cycles
-system.cpu0.num_busy_cycles              182837474.541752                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.033024                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.966976                       # Percentage of idle cycles
-system.cpu0.Branches                         18597106                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2189      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 61764727     68.82%     68.83% # Class of executed instruction
-system.cpu0.op_class::IntMult                   59660      0.07%     68.89% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              4403      0.00%     68.90% # Class of executed instruction
+system.cpu0.kern.inst.quiesce                    3080                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   72639178                       # Number of instructions committed
+system.cpu0.committedOps                     87981810                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             77492203                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5289                       # Number of float alu accesses
+system.cpu0.num_func_calls                    8694463                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      9459638                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    77492203                       # number of integer instructions
+system.cpu0.num_fp_insts                         5289                       # number of float instructions
+system.cpu0.num_int_register_reads          144072055                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          54447583                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                4067                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           268879809                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           31833575                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     27909868                       # number of memory refs
+system.cpu0.num_load_insts                   16164638                       # Number of load instructions
+system.cpu0.num_store_insts                  11745230                       # Number of store instructions
+system.cpu0.num_idle_cycles              5353616276.220466                       # Number of idle cycles
+system.cpu0.num_busy_cycles              182828510.779535                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.033023                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.966977                       # Percentage of idle cycles
+system.cpu0.Branches                         18600800                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2188      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 61776579     68.83%     68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult                   59680      0.07%     68.90% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              4414      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.90% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.90% # Class of executed instruction
-system.cpu0.op_class::MemRead                16162181     18.01%     86.91% # Class of executed instruction
-system.cpu0.op_class::MemWrite               11749540     13.09%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                16164638     18.01%     86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite               11745230     13.09%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  89742700                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           819402                       # number of replacements
+system.cpu0.op_class::total                  89752729                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           819392                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997174                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           53784414                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           819914                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            65.597629                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           53783791                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           819904                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            65.597669                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.821817                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    36.175357                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929339                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.070655                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   475.830580                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    36.166594                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.929357                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.070638                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          286                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        219237306                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       219237306                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     15302738                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     14826284                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       30129022                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     10898497                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     11441613                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      22340110                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186051                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       209007                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       395058                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       235059                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       222271                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       457330                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236765                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223371                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460136                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     26201235                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     26267897                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        52469132                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     26387286                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     26476904                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       52864190                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       197065                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       199241                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       396306                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       137741                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       163937                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       301678                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54401                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        61672                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       116073                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4662                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3967                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        219234764                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       219234764                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     15305281                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     14823482                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       30128763                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     10894769                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total      22339791                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       185755                       # number of SoftPFReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total       395041                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       234992                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       222324                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       457316                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236691                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       223431                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       460122                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     26200050                       # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::total       52863595                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       197438                       # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::cpu0.data       137575                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::total       301663                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54345                       # number of SoftPFReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total       116066                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4663                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3966                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         8629                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       334806                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       363178                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        697984                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       389207                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       424850                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       814057                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15499803                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     15025525                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     30525328                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     11036238                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     11605550                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     22641788                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       240452                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       270679                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       511131                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239721                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       226238                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       465959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236765                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223373                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460138                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     26536041                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     26631075                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     53167116                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     26776493                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     26901754                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     53678247                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.012714                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013260                       # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_misses::cpu0.data       335013                       # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total       814047                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     15502719                       # number of ReadReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_accesses::total     30525081                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     11032344                       # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_accesses::total       511107                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239655                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       226290                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       465945                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236691                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223433                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460124                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     26535063                       # number of demand (read+write) accesses
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+system.cpu0.dcache.overall_accesses::cpu0.data     26775163                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     26902479                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     53677642                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.012736                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013239                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.012983                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012481                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014126                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.013324                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.226245                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227842                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.227091                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.019448                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.017535                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.012470                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014134                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.013323                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.226343                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227747                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.227087                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.019457                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.017526                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.018519                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000009                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.012617                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013637                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.012625                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013629                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.013128                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.014535                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015793                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.014542                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.015786                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.015165                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       682264                       # number of writebacks
-system.cpu0.dcache.writebacks::total           682264                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks       682241                       # number of writebacks
+system.cpu0.dcache.writebacks::total           682241                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1699214                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.663681                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          145342721                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1699726                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            85.509500                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1698998                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.663679                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          145341757                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1699510                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            85.519801                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       7831491500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   455.127325                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    56.536356                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.888921                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.110423                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   455.121661                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    56.542018                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.888909                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.110434                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999343                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
@@ -413,44 +413,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1           77
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        148742185                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       148742185                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     73936444                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     71406277                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      145342721                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     73936444                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     71406277                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       145342721                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     73936444                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     71406277                       # number of overall hits
-system.cpu0.icache.overall_hits::total      145342721                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       844540                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       855192                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1699732                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       844540                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       855192                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1699732                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       844540                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       855192                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1699732                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     74780984                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     72261469                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    147042453                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     74780984                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     72261469                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    147042453                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     74780984                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     72261469                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    147042453                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011294                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011835                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011559                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011294                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011835                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011559                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011294                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011835                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011559                       # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses        148740789                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       148740789                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     73955506                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     71386251                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      145341757                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     73955506                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     71386251                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       145341757                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     73955506                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     71386251                       # number of overall hits
+system.cpu0.icache.overall_hits::total      145341757                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       844055                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       855461                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1699516                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       844055                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       855461                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1699516                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       844055                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       855461                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1699516                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74799561                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     72241712                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    147041273                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74799561                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     72241712                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    147041273                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74799561                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     72241712                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    147041273                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011284                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011842                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011558                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011284                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011842                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011558                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011284                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011842                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011558                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -459,8 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1699214                       # number of writebacks
-system.cpu0.icache.writebacks::total          1699214                       # number of writebacks
+system.cpu0.icache.writebacks::writebacks      1698998                       # number of writebacks
+system.cpu0.icache.writebacks::total          1698998                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -491,45 +491,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     6203                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                6203                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples         6203                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           6203    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         6203                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                     6189                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6189                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples         6189                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6189    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6189                       # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walksPending::samples   1000002000                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1000002000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1000002000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3703     73.18%     73.18% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1357     26.82%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5060                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6203                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         3697     73.27%     73.27% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1349     26.73%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5046                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6189                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6203                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5060                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6189                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5046                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5060                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        11263                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5046                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        11235                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    15529940                       # DTB read hits
-system.cpu1.dtb.read_misses                      5414                       # DTB read misses
-system.cpu1.dtb.write_hits                   11838406                       # DTB write hits
-system.cpu1.dtb.write_misses                      789                       # DTB write misses
+system.cpu1.dtb.read_hits                    15527164                       # DTB read hits
+system.cpu1.dtb.read_misses                      5392                       # DTB read misses
+system.cpu1.dtb.write_hits                   11842009                       # DTB write hits
+system.cpu1.dtb.write_misses                      797                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2817                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     523                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3183                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    3188                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   909                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   922                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      245                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                15535354                       # DTB read accesses
-system.cpu1.dtb.write_accesses               11839195                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      243                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                15532556                       # DTB read accesses
+system.cpu1.dtb.write_accesses               11842806                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         27368346                       # DTB hits
-system.cpu1.dtb.misses                           6203                       # DTB misses
-system.cpu1.dtb.accesses                     27374549                       # DTB accesses
+system.cpu1.dtb.hits                         27369173                       # DTB hits
+system.cpu1.dtb.misses                           6189                       # DTB misses
+system.cpu1.dtb.accesses                     27375362                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -559,107 +559,107 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     3041                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                3041                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walkWaitTime::samples         3041                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           3041    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         3041                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks                     3051                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3051                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walkWaitTime::samples         3051                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3051    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3051                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1721     81.53%     81.53% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          390     18.47%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2111                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K         1721     81.56%     81.56% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          389     18.44%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2110                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3041                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3041                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3051                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3051                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2111                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2111                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         5152                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    72259358                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3041                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2110                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2110                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         5161                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    72239602                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3051                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        2817                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     523                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     514                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2022                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2021                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                72262399                       # ITB inst accesses
-system.cpu1.itb.hits                         72259358                       # DTB hits
-system.cpu1.itb.misses                           3041                       # DTB misses
-system.cpu1.itb.accesses                     72262399                       # DTB accesses
-system.cpu1.numCycles                        88040649                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                72242653                       # ITB inst accesses
+system.cpu1.itb.hits                         72239602                       # DTB hits
+system.cpu1.itb.misses                           3051                       # DTB misses
+system.cpu1.itb.accesses                     72242653                       # DTB accesses
+system.cpu1.numCycles                        88015617                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   70146546                       # Number of instructions committed
-system.cpu1.committedOps                     85830789                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             75676825                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  6228                       # Number of float alu accesses
-system.cpu1.num_func_calls                    8181374                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      9272054                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    75676825                       # number of integer instructions
-system.cpu1.num_fp_insts                         6228                       # number of float instructions
-system.cpu1.num_int_register_reads          140994115                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          52737742                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4674                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1556                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           261998832                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           30539220                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     28027555                       # number of memory refs
-system.cpu1.num_load_insts                   15693703                       # Number of load instructions
-system.cpu1.num_store_insts                  12333852                       # Number of store instructions
-system.cpu1.num_idle_cycles              85384966.713327                       # Number of idle cycles
-system.cpu1.num_busy_cycles              2655682.286673                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030164                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969836                       # Percentage of idle cycles
-system.cpu1.Branches                         17799875                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                  148      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 59388111     67.89%     67.89% # Class of executed instruction
-system.cpu1.op_class::IntMult                   57232      0.07%     67.96% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4166      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.96% # Class of executed instruction
-system.cpu1.op_class::MemRead                15693703     17.94%     85.90% # Class of executed instruction
-system.cpu1.op_class::MemWrite               12333852     14.10%    100.00% # Class of executed instruction
+system.cpu1.committedInsts                   70132473                       # Number of instructions committed
+system.cpu1.committedOps                     85819782                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             75669076                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  6195                       # Number of float alu accesses
+system.cpu1.num_func_calls                    8179499                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      9270637                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    75669076                       # number of integer instructions
+system.cpu1.num_fp_insts                         6195                       # number of float instructions
+system.cpu1.num_int_register_reads          140985520                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          52730881                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4705                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           261969734                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           30530329                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     28028748                       # number of memory refs
+system.cpu1.num_load_insts                   15690947                       # Number of load instructions
+system.cpu1.num_store_insts                  12337801                       # Number of store instructions
+system.cpu1.num_idle_cycles              85360941.513009                       # Number of idle cycles
+system.cpu1.num_busy_cycles              2654675.486991                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.030161                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.969839                       # Percentage of idle cycles
+system.cpu1.Branches                         17796178                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                  149      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 59375458     67.88%     67.88% # Class of executed instruction
+system.cpu1.op_class::IntMult                   57193      0.07%     67.95% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4155      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.95% # Class of executed instruction
+system.cpu1.op_class::MemRead                15690947     17.94%     85.89% # Class of executed instruction
+system.cpu1.op_class::MemWrite               12337801     14.11%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  87477212                       # Class of executed instruction
+system.cpu1.op_class::total                  87465703                       # Class of executed instruction
 system.iobus.trans_dist::ReadReq                30164                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30164                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59002                       # Transaction distribution
@@ -711,14 +711,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480213                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                36430                       # number of replacements
-system.iocache.tags.tagsinuse                0.909961                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.909893                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36446                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         227409731009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     0.909961                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.056873                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.056873                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     0.909893                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.056868                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.056868                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -760,27 +760,27 @@ system.iocache.writebacks::writebacks           36190                       # nu
 system.iocache.writebacks::total                36190                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   109907                       # number of replacements
-system.l2c.tags.tagsinuse                65155.309141                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4528496                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                65155.314985                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4528037                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   175188                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    25.849350                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                    25.846730                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48764.072075                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924326                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   48764.087166                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.924325                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5143.224775                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4734.504525                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5143.112513                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4734.411223                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.978702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4025.377664                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2484.226979                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4025.485555                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2484.315404                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.744081                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.078479                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.072243                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.078478                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.072241                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061422                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037906                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061424                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.037908                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.994191                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65277                       # Occupied blocks per task id
@@ -792,156 +792,156 @@ system.l2c.tags.age_task_id_blocks_1024::3        10699                       #
 system.l2c.tags.age_task_id_blocks_1024::4        50642                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.996048                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 40608233                       # Number of tag accesses
-system.l2c.tags.data_accesses                40608233                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4700                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         2287                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5001                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         2453                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  14441                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks       682264                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          682264                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks      1667206                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total         1667206                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              15                       # number of UpgradeReq hits
+system.l2c.tags.tag_accesses                 40604434                       # Number of tag accesses
+system.l2c.tags.data_accesses                40604434                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4715                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         2284                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         4980                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         2427                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  14406                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks       682241                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          682241                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks      1666999                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total         1666999                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data              12                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              16                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            72515                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            78631                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               151146                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        833751                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        847665                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1681416                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       246350                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       259095                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           505445                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4700                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu0.inst              833751                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              318865                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5001                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst              847665                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              337726                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2352448                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4700                       # number of overall hits
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-system.l2c.overall_hits::cpu0.inst             833751                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             318865                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst             847665                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             337726                       # number of overall hits
-system.l2c.overall_hits::total                2352448                       # number of overall hits
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+system.l2c.ReadCleanReq_hits::cpu0.inst        833292                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        847909                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1681201                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       246688                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::total           505450                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::cpu1.inst              847909                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              337550                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2352188                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4715                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         2284                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             833292                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             319031                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         4980                       # number of overall hits
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+system.l2c.overall_hits::cpu1.inst             847909                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             337550                       # number of overall hits
+system.l2c.overall_hits::total                2352188                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            5                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                    8                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1249                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1479                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1250                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1478                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2728                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63964                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          83812                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63970                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          83806                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             147776                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        10779                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         7519                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        10754                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst         7544                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::total           18298                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         9778                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         5785                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data         9758                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data         5805                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::total          15563                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             10779                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             73742                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             10754                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             73728                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              7519                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             89597                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              7544                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             89611                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                181645                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            5                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            10779                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            73742                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            10754                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            73728                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             7519                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            89597                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             7544                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            89611                       # number of overall misses
 system.l2c.overall_misses::total               181645                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4705                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         2288                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5003                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         2453                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              14449                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks       682264                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       682264                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks      1667206                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total      1667206                       # number of WritebackClean accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4720                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         2285                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         4982                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         2427                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              14414                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks       682241                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       682241                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks      1666999                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total      1666999                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data         1262                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data         1494                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            2756                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       136479                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       162443                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           298922                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       844530                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       855184                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total       1699714                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       256128                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       264880                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       521008                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4705                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         2288                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          844530                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          392607                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5003                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         2453                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          855184                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          427323                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2534093                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4705                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         2288                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         844530                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         392607                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5003                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         2453                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         855184                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         427323                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2534093                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.000554                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989699                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989960                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data       136313                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       162594                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           298907                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst       844046                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst       855453                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total       1699499                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       256446                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       264567                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       521013                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4720                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         2285                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          844046                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          392759                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         4982                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         2427                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          855453                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          427161                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2533833                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4720                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         2285                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         844046                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         392759                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         4982                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         2427                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         855453                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         427161                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2533833                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.000555                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990491                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989290                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.989840                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.468673                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.515947                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.494363                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.012763                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008792                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010765                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.038176                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021840                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.469288                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.515431                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.494388                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.012741                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.008819                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010767                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.038051                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021942                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::total     0.029871                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.012763                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.187827                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.008792                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.209670                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.071680                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001063                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000437                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.012763                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.187827                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000400                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.008792                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.209670                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.071680                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.012741                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.187718                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.008819                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.209783                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.071688                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001059                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.012741                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.187718                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000401                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.008819                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.209783                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.071688                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -950,15 +950,15 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              101943                       # number of writebacks
-system.l2c.writebacks::total                   101943                       # number of writebacks
+system.l2c.writebacks::writebacks              101944                       # number of writebacks
+system.l2c.writebacks::total                   101944                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40087                       # Transaction distribution
 system.membus.trans_dist::ReadResp              74196                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27546                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27546                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       138133                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7977                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138134                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8203                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4507                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4509                       # Transaction distribution
@@ -972,17 +972,17 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         1946                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       506563                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::total       613923                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       109131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 723054                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       109358                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 723281                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         3892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18091644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18254617                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18091708                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18254681                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2331520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2331520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20586137                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20586201                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples            434809                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
@@ -1036,47 +1036,47 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5060706                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2541063                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        39274                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            420                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          420                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5060329                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2540912                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        39261                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            422                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          422                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              71244                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2291984                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              71251                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2291780                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27546                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27546                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       682264                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1667206                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          129872                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       682241                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1698998                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          137151                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq            2756                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2758                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           298922                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          298922                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1699732                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       521008                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5084714                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2574734                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20804                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41510                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7721762                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    215520120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96323169                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41608                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83020                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              311967917                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          182968                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5322627                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.018535                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.134877                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadExReq           298907                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          298907                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1699516                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       521013                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5116074                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2581970                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20766                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        41562                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7760372                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    217540984                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96321057                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41532                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        83124                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              313986697                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          182969                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          5322182                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.018547                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.134917                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5223970     98.15%     98.15% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  98657      1.85%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5223474     98.15%     98.15% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  98708      1.85%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5322627                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total            5322182                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 5188d100d..cd3a72dfc 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.909671                       # Number of seconds simulated
-sim_ticks                                2909670971500                       # Number of ticks simulated
-final_tick                               2909670971500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.909645                       # Number of seconds simulated
+sim_ticks                                2909644861500                       # Number of ticks simulated
+final_tick                               2909644861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 317481                       # Simulator instruction rate (inst/s)
-host_op_rate                                   382781                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8214526706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 561408                       # Number of bytes of host memory used
-host_seconds                                   354.21                       # Real time elapsed on the host
-sim_insts                                   112454909                       # Number of instructions simulated
-sim_ops                                     135585028                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 955579                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1152126                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24724694945                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 580436                       # Number of bytes of host memory used
+host_seconds                                   117.68                       # Real time elapsed on the host
+sim_insts                                   112454211                       # Number of instructions simulated
+sim_ops                                     135584166                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           523360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4648320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           522464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4660352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           663236                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4253220                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           664132                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4241316                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10089608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       523360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       663236                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             10089736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       522464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       664132                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1186596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7511936                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7511872                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data          8852                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data          8672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7529460                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7529396                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13465                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73133                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             13451                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73321                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             13529                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             66473                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             13543                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             66287                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166623                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117374                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                166625                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117373                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2213                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2168                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121755                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121754                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              179869                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1597541                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              179563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1601691                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              227942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1461753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              228252                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1457675                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3467611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         179869                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         227942                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             407811                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2581713                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3467686                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         179563                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         228252                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             407815                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2581714                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               3042                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data               2980                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2587736                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2581713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2587737                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2581714                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             179869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1600584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             179563                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1604733                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             227942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1464733                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             228252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1460655                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6055347                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166623                       # Number of read requests accepted
-system.physmem.writeReqs                       121755                       # Number of write requests accepted
-system.physmem.readBursts                      166623                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121755                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10657728                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7541440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10089608                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7529460                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6055424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166625                       # Number of read requests accepted
+system.physmem.writeReqs                       121754                       # Number of write requests accepted
+system.physmem.readBursts                      166625                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121754                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10658176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5824                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7541376                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10089736                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7529396                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       91                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          47111                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10080                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10697                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10654                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10657                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18793                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                9662                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9670                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10489                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10491                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9280                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                9982                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               9231                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8676                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8678                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               9823                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10380                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9722                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9718                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                8284                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8167                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8168                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7485                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
@@ -107,30 +107,30 @@ system.physmem.perBankWrBursts::7                7667                       # Pe
 system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               6694                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6468                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7527                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7260                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2909670614500                       # Total gap between requests
+system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2909644504500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157051                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157053                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117374                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    165647                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       611                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117373                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    165652                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       613                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -163,129 +163,134 @@ system.physmem.rdQLenPdf::30                        0                       # Wh
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                       202                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       189                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                       185                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                       184                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                       181                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                       176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       175                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                       172                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                      170                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                      169                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                      166                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      165                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5854                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7695                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5826                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6797                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      118                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       12                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58603                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      310.549016                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.176876                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.004841                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21372     36.47%     36.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14638     24.98%     61.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6011     10.26%     71.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3214      5.48%     77.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2514      4.29%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1548      2.64%     84.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1052      1.80%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1122      1.91%     87.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7132     12.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58603                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5730                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.058290                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      544.635756                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5727     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58581                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      310.672197                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.145957                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.231527                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21388     36.51%     36.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14603     24.93%     61.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5975     10.20%     71.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3225      5.51%     77.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2561      4.37%     81.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1528      2.61%     84.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1012      1.73%     85.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1135      1.94%     87.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7154     12.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58581                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5570                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.894255                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      552.382236                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5567     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            2      0.04%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5730                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5730                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.564572                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.725438                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.838937                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                17      0.30%      0.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                8      0.14%      0.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              11      0.19%      0.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4763     83.12%     83.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             132      2.30%     86.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              73      1.27%     87.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             203      3.54%     91.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              27      0.47%     91.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             153      2.67%     94.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              54      0.94%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.03%     95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.23%     95.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              23      0.40%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.09%     95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.12%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             171      2.98%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.09%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.10%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.42%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.05%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.19%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5730                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1612014000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4734395250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    832635000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9680.20                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5570                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5570                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.155117                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.796345                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       15.496905                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                17      0.31%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                8      0.14%      0.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              13      0.23%      0.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4758     85.42%     86.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             105      1.89%     88.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              66      1.18%     89.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              70      1.26%     90.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              40      0.72%     91.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              17      0.31%     91.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              48      0.86%     92.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.18%     92.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             152      2.73%     95.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               8      0.14%     95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.09%     95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.18%     95.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              62      1.11%     96.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.16%     97.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.02%     97.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.48%     97.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             105      1.89%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.04%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.04%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             4      0.07%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.04%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             7      0.13%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.04%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             5      0.09%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5570                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1610742500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4733255000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    832670000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9672.15                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28430.20                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28422.15                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
@@ -295,40 +300,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.26                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     136241                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89517                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.81                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        12.25                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     136266                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89520                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.82                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  75.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10089780.13                       # Average gap between requests
-system.physmem.pageHitRate                      79.38                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  230746320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125903250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 702187200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                392895360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           190045312080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            90312406830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1666579011000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1948388462040                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.625842                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2772320056250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     97160180000                       # Time in different power states
+system.physmem.avgGap                     10089654.60                       # Average gap between requests
+system.physmem.pageHitRate                      79.39                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  230678280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125866125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 702226200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           190043786400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            90291916755                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1666582969500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1948370345100                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.624992                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2772326098500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     97159400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     40187145000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     40158524000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  212292360                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  115834125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 596715600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370675440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           190045312080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            88507788255                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1668162009750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1948010627610                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.495988                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2774979616000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     97160180000                       # Time in different power states
+system.physmem_1.actEnergy                  212194080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  115780500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 596731200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                370662480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           190043786400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            88418921265                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1668225948000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1947984023925                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.492219                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2775082980250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     97159400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     37531027500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     37402333250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -378,59 +383,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     6370                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                6370                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1827                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4542                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walks                     6403                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                6403                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1830                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4572                       # Level at which table walker walks with short descriptors terminate
 system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples         6369                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           6369    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         6369                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         5319                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7408.984019                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         3974     74.71%     74.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1341     25.21%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::samples         6402                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           6402    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         6402                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         5332                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7407.871184                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         4008     75.17%     75.17% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1320     24.76%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::131072-147455            4      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         5319                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         5332                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   2989035968                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::mean     0.330748                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::stdev     0.470482                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     2000419000     66.93%     66.93% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::1      988616968     33.07%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   2989035968                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3517     66.13%     66.13% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1801     33.87%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5318                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6370                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         3528     66.18%     66.18% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1803     33.82%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5331                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6403                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6370                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5318                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6403                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5331                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5318                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        11688                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5331                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        11734                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12041748                       # DTB read hits
-system.cpu0.dtb.read_misses                      5569                       # DTB read misses
-system.cpu0.dtb.write_hits                    9609883                       # DTB write hits
-system.cpu0.dtb.write_misses                      801                       # DTB write misses
+system.cpu0.dtb.read_hits                    12042048                       # DTB read hits
+system.cpu0.dtb.read_misses                      5594                       # DTB read misses
+system.cpu0.dtb.write_hits                    9609454                       # DTB write hits
+system.cpu0.dtb.write_misses                      809                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     437                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3992                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3984                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   859                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   860                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      214                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12047317                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9610684                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12047642                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9610263                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21651631                       # DTB hits
-system.cpu0.dtb.misses                           6370                       # DTB misses
-system.cpu0.dtb.accesses                     21658001                       # DTB accesses
+system.cpu0.dtb.hits                         21651502                       # DTB hits
+system.cpu0.dtb.misses                           6403                       # DTB misses
+system.cpu0.dtb.accesses                     21657905                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -460,131 +465,131 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3218                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3218                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          687                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2531                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3218                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3218    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3218                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2361                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6544.721859                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::4096-6143          607     25.71%     25.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::10240-12287          660     27.95%     53.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::12288-14335          188      7.96%     61.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.39%     78.02% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.14% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::22528-24575          510     21.60%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-26623            6      0.25%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2361                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     3203                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3203                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          686                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2517                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3203                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3203    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3203                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2349                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6519.168051                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::4096-6143          600     25.54%     25.54% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::10240-12287          662     28.18%     53.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::12288-14335          191      8.13%     61.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.48%     78.33% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.46% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::22528-24575          498     21.20%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-26623            8      0.34%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2349                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   2000380500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     2000380500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   2000380500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1674     70.90%     70.90% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          687     29.10%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2361                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         1663     70.80%     70.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          686     29.20%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2349                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3218                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3218                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3203                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3203                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2361                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2361                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         5579                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    56731893                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3218                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2349                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2349                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         5552                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    56738612                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3203                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     437                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2380                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2371                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                56735111                       # ITB inst accesses
-system.cpu0.itb.hits                         56731893                       # DTB hits
-system.cpu0.itb.misses                           3218                       # DTB misses
-system.cpu0.itb.accesses                     56735111                       # DTB accesses
-system.cpu0.numCycles                      2910044257                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                56741815                       # ITB inst accesses
+system.cpu0.itb.hits                         56738612                       # DTB hits
+system.cpu0.itb.misses                           3203                       # DTB misses
+system.cpu0.itb.accesses                     56741815                       # DTB accesses
+system.cpu0.numCycles                      2910043779                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3034                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   55192175                       # Number of instructions committed
-system.cpu0.committedOps                     66601030                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             58838667                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5226                       # Number of float alu accesses
-system.cpu0.num_func_calls                    4816070                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7555391                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    58838667                       # number of integer instructions
-system.cpu0.num_fp_insts                         5226                       # number of float instructions
-system.cpu0.num_int_register_reads          106920418                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          40489001                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3747                       # number of times the floating registers were read
+system.cpu0.kern.inst.quiesce                    3033                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   55199902                       # Number of instructions committed
+system.cpu0.committedOps                     66610456                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             58846956                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5257                       # Number of float alu accesses
+system.cpu0.num_func_calls                    4818664                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7556613                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    58846956                       # number of integer instructions
+system.cpu0.num_fp_insts                         5257                       # number of float instructions
+system.cpu0.num_int_register_reads          106933232                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          40497320                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3778                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1482                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           240444662                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           25665883                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     22275144                       # number of memory refs
-system.cpu0.num_load_insts                   12196401                       # Number of load instructions
-system.cpu0.num_store_insts                  10078743                       # Number of store instructions
-system.cpu0.num_idle_cycles              2694612539.353109                       # Number of idle cycles
-system.cpu0.num_busy_cycles              215431717.646891                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.074030                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.925970                       # Percentage of idle cycles
-system.cpu0.Branches                         12738975                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                  134      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 45781986     67.21%     67.21% # Class of executed instruction
-system.cpu0.op_class::IntMult                   56167      0.08%     67.29% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.29% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3968      0.01%     67.30% # Class of executed instruction
+system.cpu0.num_cc_register_reads           240479401                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           25666284                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     22274939                       # number of memory refs
+system.cpu0.num_load_insts                   12196843                       # Number of load instructions
+system.cpu0.num_store_insts                  10078096                       # Number of store instructions
+system.cpu0.num_idle_cycles              2694635007.442764                       # Number of idle cycles
+system.cpu0.num_busy_cycles              215408771.557236                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.074023                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.925977                       # Percentage of idle cycles
+system.cpu0.Branches                         12742817                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                  133      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 45792240     67.22%     67.22% # Class of executed instruction
+system.cpu0.op_class::IntMult                   56099      0.08%     67.30% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3963      0.01%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::MemRead                12196401     17.90%     85.20% # Class of executed instruction
-system.cpu0.op_class::MemWrite               10078743     14.80%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                12196843     17.90%     85.21% # Class of executed instruction
+system.cpu0.op_class::MemWrite               10078096     14.79%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68117399                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           819062                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.702235                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43234880                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           819574                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            52.752869                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  68127374                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           819099                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.702232                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43234609                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           819611                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.750157                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1736913500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.309006                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.393230                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.084588                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914831                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.298558                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.403674                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.084567                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914851                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999418                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
@@ -592,264 +597,264 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1          344
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        177106290                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       177106290                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11353905                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     11758208                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23112113                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9226963                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      9596855                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18823818                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190234                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202489                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       392723                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213697                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       229550                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       443247                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221754                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       238460                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460214                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20580868                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21355063                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41935931                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20771102                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21557552                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       42328654                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       199783                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       200066                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       399849                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       149794                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       148846                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       298640                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58818                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59499                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       118317                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10855                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11895                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22750                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        177105423                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       177105423                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11354436                       # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::cpu0.data      9226475                       # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190286                       # number of SoftPFReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213920                       # number of LoadLockedReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total       443229                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221967                       # number of StoreCondReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total       460206                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20580911                       # number of demand (read+write) hits
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+system.cpu0.dcache.demand_hits::total        41935706                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20771197                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total       42328407                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       199328                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       399862                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       149618                       # number of WriteReq misses
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+system.cpu0.dcache.WriteReq_misses::total       298657                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58774                       # number of SoftPFReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total       118324                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10841                       # number of LoadLockedReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total        22760                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       349577                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       348912                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        698489                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       408395                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       408411                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       816806                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3309369500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3172445000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6481814500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9848447000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9257158000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  19105605000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137223000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    156952000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    294175000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data       348946                       # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::cpu0.data       407720                       # number of overall misses
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+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3302461000                       # number of ReadReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::total   6483327500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9863039500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9227377000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  19090416500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137120000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    157150000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    294270000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  13157816500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  12429603000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  25587419500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  13157816500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  12429603000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  25587419500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11553688                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     11958274                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23511962                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9376757                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9745701                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19122458                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249052                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261988                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       511040                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224552                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241445                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       465997                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221754                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238462                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460216                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     20930445                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     21703975                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     42634420                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     21179497                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     21965963                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     43145460                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017292                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016730                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.017006                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015975                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015273                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.236168                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227106                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231522                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048341                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049266                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048820                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data  13165500500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  12408243500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  25573744000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  13165500500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  12408243500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  25573744000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11553764                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     11958112                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23511876                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9376093                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9746256                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19122349                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249060                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261965                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       511025                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224761                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241228                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       465989                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221967                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238241                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460208                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20929857                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     21704368                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     42634225                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     21178917                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     21966333                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     43145250                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017252                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016770                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.017007                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015957                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015292                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.015618                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235983                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227320                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231542                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048233                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049410                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048842                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000008                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016702                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016076                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.016383                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019283                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018593                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.018931                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16564.820330                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15856.992193                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16210.655773                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65746.605338                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 62192.857047                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 63975.371685                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12641.455550                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13194.787726                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12930.769231                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016672                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016106                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.016384                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019251                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018625                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.018932                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16567.973391                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15861.981011                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16213.912550                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65921.476694                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61912.499413                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 63920.874113                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12648.279679                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13184.830942                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12929.261863                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37639.251152                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35623.890838                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36632.530362                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32218.358452                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30434.055400                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 31326.189450                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37729.334911                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35495.428709                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36611.379218                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.543756                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30328.882757                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31308.028593                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          148                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     6.727273                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       683867                       # number of writebacks
-system.cpu0.dcache.writebacks::total           683867                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          471                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          454                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          925                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7013                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7211                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14224                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          471                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          454                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          925                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          471                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          454                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          925                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       199312                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       199612                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       398924                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149794                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148846                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       298640                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57717                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58554                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       116271                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3842                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4684                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8526                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       683901                       # number of writebacks
+system.cpu0.dcache.writebacks::total           683901                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          477                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          439                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          916                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7004                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7232                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14236                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          477                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          439                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          916                       # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::cpu1.data          439                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          916                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       198851                       # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149618                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total       298657                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57662                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58611                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       116273                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3837                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4687                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8524                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       349106                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       348458                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       697564                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       406823                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       407012                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       813835                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14993                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16145                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       348469                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       349134                       # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15000                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16138                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13371                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14218                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13390                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14199                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28364                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30363                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28390                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30337                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3093759000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2959743000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6053502000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9698653000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9108312000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18806965000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    795616000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    818334500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1613950500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52173500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63283500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115457000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3086715500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2967879500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6054595000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9713421500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9078338000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18791759500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    797262500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    818412000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1615674500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52113500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63305500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115419000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12792412000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12068055000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  24860467000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13588028000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12886389500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  26474417500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3047137000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3231000000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6278137000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2491876500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2598064000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089940500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5539013500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5829064000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368077500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017251                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016692                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016967                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015975                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015273                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231747                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223499                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227518                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017110                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019400                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018296                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12800137000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12046217500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  24846354500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13597399500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12864629500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  26462029000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3048418500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3229696000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6278114500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2495078000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2594854500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089932500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5543496500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5824550500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368047000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017211                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016733                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016968                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015957                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015292                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015618                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231519                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223736                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227529                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017071                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019430                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018292                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000008                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016679                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016055                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016362                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019208                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018529                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018863                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016649                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016086                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016363                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019176                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018562                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018864                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1695832                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.436658                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          113855734                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1696344                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.118305                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1695677                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.436645                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          113855199                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1696189                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.124123                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      29075840500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst    60.007721                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.428938                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117203                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879744                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst    59.966796                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.469848                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117123                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879824                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
@@ -857,62 +862,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1          195
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        117248434                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       117248434                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     55890585                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     57965149                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      113855734                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     55890585                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     57965149                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       113855734                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     55890585                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     57965149                       # number of overall hits
-system.cpu0.icache.overall_hits::total      113855734                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       841308                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       855042                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1696350                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       841308                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       855042                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1696350                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       841308                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       855042                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1696350                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11907607000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12366012000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  24273619000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11907607000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  12366012000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  24273619000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11907607000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  12366012000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  24273619000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     56731893                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     58820191                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115552084                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     56731893                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     58820191                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115552084                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     56731893                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     58820191                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115552084                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014830                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014537                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014680                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014830                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014537                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014680                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014830                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014537                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014680                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14153.683312                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14462.461493                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.322369                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14153.683312                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14462.461493                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14309.322369                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14153.683312                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14462.461493                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14309.322369                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        117247589                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       117247589                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     55898438                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     57956761                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      113855199                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     55898438                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     57956761                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       113855199                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     55898438                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     57956761                       # number of overall hits
+system.cpu0.icache.overall_hits::total      113855199                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       840174                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       856021                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1696195                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       840174                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       856021                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1696195                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       840174                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       856021                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1696195                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11888847500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12382350500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  24271198000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11888847500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  12382350500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  24271198000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11888847500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  12382350500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  24271198000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     56738612                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     58812782                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115551394                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     56738612                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     58812782                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115551394                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     56738612                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     58812782                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115551394                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014808                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014555                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014679                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014808                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014555                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014679                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014808                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014555                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014679                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14150.458715                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14465.007868                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.202657                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14150.458715                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14465.007868                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14309.202657                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14150.458715                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14465.007868                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14309.202657                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -921,56 +926,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1695832                       # number of writebacks
-system.cpu0.icache.writebacks::total          1695832                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       841308                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       855042                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1696350                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       841308                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       855042                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1696350                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       841308                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       855042                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1696350                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1695677                       # number of writebacks
+system.cpu0.icache.writebacks::total          1695677                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       840174                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       856021                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1696195                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       840174                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       856021                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1696195                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       840174                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       856021                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1696195                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11066299000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11510970000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  22577269000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11066299000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11510970000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  22577269000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11066299000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11510970000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  22577269000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11048673500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11526329500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  22575003000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11048673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11526329500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  22575003000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11048673500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11526329500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  22575003000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1142893000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1142893000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014680                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014680                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014680                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014679                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014679                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014679                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.202657                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.202657                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.202657                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671                       # average ReadReq mshr uncacheable latency
@@ -1007,54 +1012,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     6967                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                6967                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2209                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4758                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         6967                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           6967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         6967                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5854                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7355.876792                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767         5853     99.98%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     6953                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6953                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2221                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4731                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples         6952                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6952    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6952                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5860                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7349.012526                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767         5859     99.98%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5854                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1639416500                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1639416500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1639416500                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3666     62.62%     62.62% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         2188     37.38%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5854                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6967                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total         5860                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples    292297068                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean    -4.609996                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1639785500    561.00%    561.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -1347488432   -461.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total    292297068                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3658     62.43%     62.43% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         2201     37.57%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5859                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6953                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6967                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5854                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6953                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5859                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5854                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        12821                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5859                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        12812                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12477838                       # DTB read hits
-system.cpu1.dtb.read_misses                      5947                       # DTB read misses
-system.cpu1.dtb.write_hits                    9996447                       # DTB write hits
-system.cpu1.dtb.write_misses                     1020                       # DTB write misses
+system.cpu1.dtb.read_hits                    12477429                       # DTB read hits
+system.cpu1.dtb.read_misses                      5926                       # DTB read misses
+system.cpu1.dtb.write_hits                    9996759                       # DTB write hits
+system.cpu1.dtb.write_misses                     1027                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     480                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    4688                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    4677                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   911                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   918                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      231                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12483785                       # DTB read accesses
-system.cpu1.dtb.write_accesses                9997467                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      228                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12483355                       # DTB read accesses
+system.cpu1.dtb.write_accesses                9997786                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         22474285                       # DTB hits
-system.cpu1.dtb.misses                           6967                       # DTB misses
-system.cpu1.dtb.accesses                     22481252                       # DTB accesses
+system.cpu1.dtb.hits                         22474188                       # DTB hits
+system.cpu1.dtb.misses                           6953                       # DTB misses
+system.cpu1.dtb.accesses                     22481141                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1084,85 +1092,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     3507                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                3507                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          840                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2667                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         3507                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           3507    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         3507                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2709                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7198.145608                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-16383         1959     72.31%     72.31% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-32767          749     27.65%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                     3501                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3501                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          842                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2659                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         3501                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3501    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3501                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2700                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7193.126612                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-16383         1956     72.44%     72.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-32767          743     27.52%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2709                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2700                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1638889000                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1638889000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1638889000                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1869     68.99%     68.99% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          840     31.01%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2709                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K         1858     68.81%     68.81% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          842     31.19%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2700                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3507                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3507                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3501                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3501                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2709                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2709                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         6216                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    58820191                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3507                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2700                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2700                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         6201                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    58812782                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3501                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     480                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2713                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2701                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                58823698                       # ITB inst accesses
-system.cpu1.itb.hits                         58820191                       # DTB hits
-system.cpu1.itb.misses                           3507                       # DTB misses
-system.cpu1.itb.accesses                     58823698                       # DTB accesses
-system.cpu1.numCycles                      2909297686                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                58816283                       # ITB inst accesses
+system.cpu1.itb.hits                         58812782                       # DTB hits
+system.cpu1.itb.misses                           3501                       # DTB misses
+system.cpu1.itb.accesses                     58816283                       # DTB accesses
+system.cpu1.numCycles                      2909245944                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   57262734                       # Number of instructions committed
-system.cpu1.committedOps                     68983998                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             61052130                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5870                       # Number of float alu accesses
-system.cpu1.num_func_calls                    5075478                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      7674901                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    61052130                       # number of integer instructions
-system.cpu1.num_fp_insts                         5870                       # number of float instructions
-system.cpu1.num_int_register_reads          111137302                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          42154976                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4637                       # number of times the floating registers were read
+system.cpu1.committedInsts                   57254309                       # Number of instructions committed
+system.cpu1.committedOps                     68973710                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             61043070                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5904                       # Number of float alu accesses
+system.cpu1.num_func_calls                    5072826                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      7673629                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    61043070                       # number of integer instructions
+system.cpu1.num_fp_insts                         5904                       # number of float instructions
+system.cpu1.num_int_register_reads          111123439                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          42146017                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4671                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               1234                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           249286409                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26228170                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     23131429                       # number of memory refs
-system.cpu1.num_load_insts                   12645834                       # Number of load instructions
-system.cpu1.num_store_insts                  10485595                       # Number of store instructions
-system.cpu1.num_idle_cycles              2689887383.006891                       # Number of idle cycles
-system.cpu1.num_busy_cycles              219410302.993109                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.075417                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.924583                       # Percentage of idle cycles
-system.cpu1.Branches                         13176890                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                 2203      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 47391308     67.14%     67.14% # Class of executed instruction
-system.cpu1.op_class::IntMult                   58256      0.08%     67.22% # Class of executed instruction
+system.cpu1.num_cc_register_reads           249248543                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26227592                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     23131346                       # number of memory refs
+system.cpu1.num_load_insts                   12645224                       # Number of load instructions
+system.cpu1.num_store_insts                  10486122                       # Number of store instructions
+system.cpu1.num_idle_cycles              2689856281.302534                       # Number of idle cycles
+system.cpu1.num_busy_cycles              219389662.697466                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.075411                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.924589                       # Percentage of idle cycles
+system.cpu1.Branches                         13172935                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                 2204      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 47380499     67.13%     67.14% # Class of executed instruction
+system.cpu1.op_class::IntMult                   58319      0.08%     67.22% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     67.22% # Class of executed instruction
@@ -1186,15 +1194,15 @@ system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.22% # Cl
 system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4483      0.01%     67.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4490      0.01%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.23% # Class of executed instruction
-system.cpu1.op_class::MemRead                12645834     17.92%     85.15% # Class of executed instruction
-system.cpu1.op_class::MemWrite               10485595     14.85%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                12645224     17.92%     85.14% # Class of executed instruction
+system.cpu1.op_class::MemWrite               10486122     14.86%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  70587679                       # Class of executed instruction
+system.cpu1.op_class::total                  70576858                       # Class of executed instruction
 system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
@@ -1245,7 +1253,7 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46334000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46333000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                98000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1279,25 +1287,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6288000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6279500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy            36457000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           186225545                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           187070020                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36418                       # number of replacements
-system.iocache.tags.tagsinuse                1.084397                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084263                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         313834390000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.084397                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067775                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067775                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         313834387000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.084263                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067766                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067766                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1311,14 +1319,14 @@ system.iocache.demand_misses::realview.ide          228                       #
 system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          228                       # number of overall misses
 system.iocache.overall_misses::total              228                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28184876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28184876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715128669                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715128669                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28184876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28184876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28184876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28184876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28181877                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28181877                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4548907143                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4548907143                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28181877                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28181877                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28181877                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28181877                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1335,19 +1343,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123617.877193                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123617.877193                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123617.877193                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123617.877193                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123617.877193                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           572                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123604.723684                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123604.723684                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123604.723684                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123604.723684                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123604.723684                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   60                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.533333                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1361,14 +1369,14 @@ system.iocache.demand_mshr_misses::realview.ide          228
 system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16784876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16784876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2903928669                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2903928669                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16784876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16784876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16784876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16784876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16781877                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16781877                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736290629                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2736290629                       # number of WriteLineReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total     16781877                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16781877                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16781877                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1377,266 +1385,266 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73617.877193                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73617.877193                       # average overall mshr miss latency
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+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442                       # average WriteLineReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 73604.723684                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    87560                       # number of replacements
-system.l2c.tags.tagsinuse                64865.201521                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4551354                       # Total number of references to valid blocks.
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-system.l2c.tags.avg_refs                    29.787323                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    87562                       # number of replacements
+system.l2c.tags.tagsinuse                64865.213908                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4551019                       # Total number of references to valid blocks.
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+system.l2c.tags.avg_refs                    29.784741                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50199.128097                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905025                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4090.007642                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2504.647366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.838092                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.data     2504.674114                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.inst     5610.818089                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2455.856604                       # Average occupied blocks per requestor
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 system.l2c.demand_miss_latency::cpu0.dtb.walker       530500                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.dtb.walker       530500                       # number of overall miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992764                       # miss rate for UpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadCleanReq_miss_rate::total     0.010599                       # miss rate for ReadCleanReq accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       132625                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total       132750                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   766.447368                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   589.285714                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   677.737226                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   728.941685                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   576.496674                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   653.719912                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127387.576454                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130882.108626                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130713.314950                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 130786.779020                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132840.091463                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131422.651934                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 132186.632158                       # average ReadSharedReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130592.049674                       # average ReadCleanReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::total 130763.335002                       # average ReadCleanReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 132393.147646                       # average ReadSharedReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 130882.108626                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 127312.938605                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 130592.049674                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 127291.892331                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 130713.314950                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 127723.428716                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 127879.805244                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 130894.915421                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 127668.756601                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 130882.108626                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 127312.938605                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 130592.049674                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 127291.892331                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 130713.314950                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 127723.428716                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 127879.805244                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 130894.915421                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 127668.756601                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 127843.801471                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1645,237 +1653,236 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81184                       # number of writebacks
-system.l2c.writebacks::total                    81184                       # number of writebacks
+system.l2c.writebacks::writebacks               81183                       # number of writebacks
+system.l2c.writebacks::total                    81183                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total               8                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1368                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1372                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2740                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1389                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1353                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67111                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        61802                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        128913                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         7825                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10154                       # number of ReadCleanReq MSHR misses
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 system.l2c.ReadCleanReq_mshr_misses::total        17979                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6560                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.data         5611                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::total        12171                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         7825                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        73671                       # number of demand (read+write) MSHR misses
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 system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        10154                       # number of demand (read+write) MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::total          159071                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14993                       # number of ReadReq MSHR uncacheable
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-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16145                       # number of ReadReq MSHR uncacheable
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 system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
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 system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
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 system.l2c.ReadReq_mshr_miss_latency::total       982000                       # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2859676500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3029132000                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5197717500                       # number of overall MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5463627500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11691463000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992764                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991676                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021347                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023239                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009301                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.180000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.164296                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.062758                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009301                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.180000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.164296                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.062758                       # mshr miss rate for overall accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.454046                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.417232                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.435672                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010600                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021303                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023238                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.180770                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.163541                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.062762                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.180770                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.163541                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.062762                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total       122750                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68045.356371                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68019.586105                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68032.640408                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646                       # average ReadSharedReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 117879.805244                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 117843.801471                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 117879.805244                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 117843.801471                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
 system.membus.trans_dist::ReadResp              70546                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117374                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6389                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4498                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117373                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6607                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4500                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            127155                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           127155                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            127157                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127157                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq         30386                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438813                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       546405                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 655299                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       434320                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       541912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72885                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        72885                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 614797                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15301948                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     15465301                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15302012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     15465365                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17782421                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17782485                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              492                       # Total snoops (count)
-system.membus.snoop_fanout::samples            389996                       # Request fanout histogram
+system.membus.snoop_fanout::samples            390010                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  389996    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  390010    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              389996                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90452500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              390010                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90443000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1723000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1721000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           823109916                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           823181865                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          952195249                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          943214000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64063181                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy            1187123                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -1918,60 +1925,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5053996                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2538070                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        38133                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5053855                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2538047                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        38136                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops            581                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              74719                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2295003                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              74697                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2294848                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       801245                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1665046                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          134452                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2763                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       801289                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1695677                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          141805                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2765                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2765                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295877                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295877                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1696350                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       523949                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2767                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295892                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295892                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1696195                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       523971                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5075755                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2574108                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18469                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34870                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7703202                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    215163192                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96418525                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26184                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48936                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              311656837                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          176461                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2781455                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021257                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.144239                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5106078                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2581570                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18395                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34840                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7740883                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    217113784                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96423069                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26060                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48732                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              313611645                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          176532                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          2781330                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021292                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.144357                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2722330     97.87%     97.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  59125      2.13%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2722109     97.87%     97.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  59221      2.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2781455                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4961451000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2781330                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4961202000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           380876                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           380377                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2553547000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2553314500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1275712000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1275768500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11923000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11880000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          22636000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          22657000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index ed0884673..926ea5f21 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.112152                       # Number of seconds simulated
-sim_ticks                                5112152301500                       # Number of ticks simulated
-final_tick                               5112152301500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5112151729000                       # Number of ticks simulated
+final_tick                               5112151729000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 646932                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1324411                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16530551683                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 604676                       # Number of bytes of host memory used
-host_seconds                                   309.26                       # Real time elapsed on the host
-sim_insts                                   200066731                       # Number of instructions simulated
-sim_ops                                     409580371                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1266983                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2593792                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32374197845                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 659352                       # Number of bytes of host memory used
+host_seconds                                   157.91                       # Real time elapsed on the host
+sim_insts                                   200067055                       # Number of instructions simulated
+sim_ops                                     409581065                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
@@ -21,16 +21,16 @@ system.physmem.bytes_read::pc.south_bridge.ide        28352
 system.physmem.bytes_read::total             11490752                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       846912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          846912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9270016                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9270016                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      9269888                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9269888                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              13233                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             165861                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                179543                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          144844                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               144844                       # Number of write requests responded to by this memory
+system.physmem.num_writes::writebacks          144842                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               144842                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.inst               165666                       # Total read bandwidth from this memory (bytes/s)
@@ -39,48 +39,48 @@ system.physmem.bw_read::pc.south_bridge.ide         5546                       #
 system.physmem.bw_read::total                 2247733                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          165666                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             165666                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1813329                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1813329                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1813329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1813305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1813305                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1813305                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              165666                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             2076445                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4061062                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4061038                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10224308568                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224307424                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.committedInsts                   200066731                       # Number of instructions committed
-system.cpu.committedOps                     409580371                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374583495                       # Number of integer alu accesses
+system.cpu.committedInsts                   200067055                       # Number of instructions committed
+system.cpu.committedOps                     409581065                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374584177                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                     2308877                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     40001070                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374583495                       # number of integer instructions
+system.cpu.num_func_calls                     2308905                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     40001120                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374584177                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           682689563                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          323557658                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           682690924                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          323558192                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            233837318                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           157316420                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      35667022                       # number of memory refs
-system.cpu.num_load_insts                    27243255                       # Number of load instructions
-system.cpu.num_store_insts                    8423767                       # Number of store instructions
-system.cpu.num_idle_cycles               9770324721.656570                       # Number of idle cycles
-system.cpu.num_busy_cycles               453983846.343430                       # Number of busy cycles
+system.cpu.num_cc_register_reads            233837631                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           157316591                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      35667176                       # number of memory refs
+system.cpu.num_load_insts                    27243343                       # Number of load instructions
+system.cpu.num_store_insts                    8423833                       # Number of store instructions
+system.cpu.num_idle_cycles               9770322790.617842                       # Number of idle cycles
+system.cpu.num_busy_cycles               453984633.382158                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.044402                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955598                       # Percentage of idle cycles
-system.cpu.Branches                          43152159                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                172754      0.04%      0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu                 373476545     91.18%     91.23% # Class of executed instruction
-system.cpu.op_class::IntMult                   144577      0.04%     91.26% # Class of executed instruction
-system.cpu.op_class::IntDiv                    123078      0.03%     91.29% # Class of executed instruction
+system.cpu.Branches                          43152262                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                172765      0.04%      0.04% # Class of executed instruction
+system.cpu.op_class::IntAlu                 373477070     91.18%     91.23% # Class of executed instruction
+system.cpu.op_class::IntMult                   144574      0.04%     91.26% # Class of executed instruction
+system.cpu.op_class::IntDiv                    123086      0.03%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::FloatCvt                      16      0.00%     91.29% # Class of executed instruction
@@ -107,16 +107,16 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
-system.cpu.op_class::MemRead                 27240665      6.65%     97.94% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8423767      2.06%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 27240752      6.65%     97.94% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8423833      2.06%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  409581402                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           1621902                       # number of replacements
+system.cpu.op_class::total                  409582096                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           1621909                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.999425                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20181182                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1622414                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.438984                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            20181333                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1622421                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.439024                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle           7549500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999425                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
@@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          282
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88836888                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88836888                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12023339                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12023339                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8096662                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8096662                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        58900                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         58900                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20120001                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20120001                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20178901                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20178901                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       905249                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        905249                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316707                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316707                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       402757                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       402757                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1221956                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1221956                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1624713                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1624713                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data     12928588                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12928588                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8413369                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8413369                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          88837527                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88837527                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12023410                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12023410                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8096819                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8096819                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        58904                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         58904                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      20120229                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20120229                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20179133                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20179133                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       905268                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        905268                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316618                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316618                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402753                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402753                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1221886                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1221886                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1624639                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1624639                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data     12928678                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12928678                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8413437                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8413437                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       461657                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total       461657                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21341957                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21341957                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21803614                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21803614                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070019                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070019                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037643                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037643                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872416                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.872416                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.057256                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.057256                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074516                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074516                       # miss rate for overall accesses
+system.cpu.dcache.demand_accesses::cpu.data     21342115                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21342115                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21803772                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21803772                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070020                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070020                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037632                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037632                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872407                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.872407                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057252                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057252                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074512                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074512                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -176,16 +176,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1535779                       # number of writebacks
-system.cpu.dcache.writebacks::total           1535779                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1535790                       # number of writebacks
+system.cpu.dcache.writebacks::total           1535790                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         7749                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.013997                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12940                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.014001                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        12936                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.sampled_refs         7763                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.666881                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013997                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.avg_refs     1.666366                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.014001                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313375                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313375                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
@@ -193,32 +193,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            5
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        52753                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        52753                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12941                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12941                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12941                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12941                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12941                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12941                       # number of overall hits
+system.cpu.dtb_walker_cache.tags.tag_accesses        52745                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52745                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12937                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12937                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12937                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12937                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12937                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12937                       # number of overall hits
 system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8957                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total         8957                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8957                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total         8957                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8957                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total         8957                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21898                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21898                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21898                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21898                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21898                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21898                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.409033                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.409033                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.409033                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21894                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21894                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21894                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21894                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.409108                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.409108                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.409108                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.409108                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.409108                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.409108                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -227,14 +227,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2453                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2453                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::writebacks         2897                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2897                       # number of writebacks
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            792216                       # number of replacements
+system.cpu.icache.tags.replacements            792340                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.662956                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           243675150                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            792728                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            307.388095                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           243675443                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            792852                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            307.340390                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      148913118500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.662956                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997389                       # Average percentage of cache occupancy
@@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          130
 system.cpu.icache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         245260620                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        245260620                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    243675150                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243675150                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243675150                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243675150                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243675150                       # number of overall hits
-system.cpu.icache.overall_hits::total       243675150                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       792735                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        792735                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       792735                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         792735                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       792735                       # number of overall misses
-system.cpu.icache.overall_misses::total        792735                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244467885                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244467885                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244467885                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244467885                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244467885                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244467885                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         245261161                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        245261161                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    243675443                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243675443                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243675443                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243675443                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243675443                       # number of overall hits
+system.cpu.icache.overall_hits::total       243675443                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       792859                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        792859                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       792859                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         792859                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       792859                       # number of overall misses
+system.cpu.icache.overall_misses::total        792859                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244468302                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244468302                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244468302                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244468302                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244468302                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244468302                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003243                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.003243                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003243                       # miss rate for demand accesses
@@ -279,18 +279,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       792216                       # number of writebacks
-system.cpu.icache.writebacks::total            792216                       # number of writebacks
+system.cpu.icache.writebacks::writebacks       792340                       # number of writebacks
+system.cpu.icache.writebacks::total            792340                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3586                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.026546                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.026555                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7763                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.tags.sampled_refs         3597                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.tags.avg_refs     2.158187                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026546                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189159                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.189159                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026555                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189160                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.189160                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
@@ -334,61 +334,61 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          545                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          545                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::writebacks          700                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          700                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           106204                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64823.931309                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4340224                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           106202                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64823.935074                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4340729                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           170162                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            25.506423                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            25.509391                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002478                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.135113                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2458.314401                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.135114                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2458.317021                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.792373                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.037511                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.159249                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.989135                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63958                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63960                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3349                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20908                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39411                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975922                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39255979                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39255979                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1538777                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1538777                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       792205                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       792205                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           21                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           21                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       179774                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       179774                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       779488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       779488                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6656                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2896                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1275198                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1284750                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6656                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2896                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       779488                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1454972                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2244012                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6656                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2896                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       779488                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1454972                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2244012                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1808                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1808                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3348                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20880                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39442                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975952                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         39254568                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39254568                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1539387                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1539387                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       792329                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       792329                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          312                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          312                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       179766                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       179766                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       779612                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       779612                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6533                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2871                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1275070                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1284474                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         6533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         2871                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       779612                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1454836                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2243852                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         6533                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         2871                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       779612                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1454836                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2243852                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1349                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1349                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       134647                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       134647                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13234                       # number of ReadCleanReq misses
@@ -407,50 +407,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker            5
 system.cpu.l2cache.overall_misses::cpu.inst        13234                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       166811                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       180051                       # number of overall misses
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      1538777                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      1538777                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       792205                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       792205                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1829                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1829                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314421                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314421                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       792722                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       792722                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6657                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2901                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1307362                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1316920                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6657                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2901                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       792722                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1621783                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2424063                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6657                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2901                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       792722                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1621783                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2424063                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988518                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988518                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428238                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.428238                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016694                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016694                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001724                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024602                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024428                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001724                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016694                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102857                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.074277                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001724                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016694                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102857                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.074277                       # miss rate for overall accesses
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      1539387                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      1539387                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       792329                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       792329                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1661                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1661                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314413                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314413                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       792846                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       792846                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6534                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2876                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1307234                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1316644                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6534                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         2876                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       792846                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1621647                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2423903                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6534                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         2876                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       792846                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1621647                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2423903                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.812161                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.812161                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428249                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.428249                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016692                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016692                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000153                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001739                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024605                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024433                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000153                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001739                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016692                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102865                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.074281                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000153                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001739                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016692                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102865                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.074281                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -459,44 +459,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        98177                       # number of writebacks
-system.cpu.l2cache.writebacks::total            98177                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        98175                       # number of writebacks
+system.cpu.l2cache.writebacks::total            98175                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4856313                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425286                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4856494                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425336                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11672                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1230                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1230                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq       13857337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      15971490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      15971629                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13943                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13943                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1538777                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       792205                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        88200                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       314426                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       314426                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       792735                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1321418                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2377675                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32613331                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        10293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        22163                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          35023462                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101436160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227550265                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       320000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       730240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          330036665                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      203470                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     18930684                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1539387                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       792340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        93857                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2200                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2200                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       314418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       314418                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       792859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1321433                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2378058                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32613747                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        12496                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        25663                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          35029964                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101452736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227551417                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       329920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       758656                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          330092729                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      203468                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     18930863                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.001304                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.042949                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           18911125     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           18911304     99.90%     99.90% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1              14428      0.08%     99.97% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2               5131      0.03%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
@@ -504,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Re
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       18930684                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       18930863                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq             10012057                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            10012057                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57724                       # Transaction distribution
@@ -558,14 +558,14 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                 13062828                       # Cumulative packet size per connected master and slave (bytes)
 system.iocache.tags.replacements                47568                       # number of replacements
-system.iocache.tags.tagsinuse                0.042441                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.042439                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47584                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         4994875253009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042441                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042439                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002652                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.002652                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -610,11 +610,11 @@ system.membus.trans_dist::ReadReq            13857337                       # Tr
 system.membus.trans_dist::ReadResp           13903644                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13943                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       144844                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8271                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2561                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2109                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            134351                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       144842                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8802                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2189                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1650                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            134346                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           134346                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq         46307                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1696                       # Transaction distribution
@@ -625,32 +625,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
 system.membus.pkt_count_system.apicbridge.master::total         3392                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20044316                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      7698244                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       470253                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28212813                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142283                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       142283                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28358488                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       469415                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28211975                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       142814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28358181                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10028276                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio     15396485                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17787328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43212089                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17787200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43211961                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3044480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3044480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                46263353                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                46263225                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples          14256561                       # Request fanout histogram
+system.membus.snoop_fanout::samples          14256182                       # Request fanout histogram
 system.membus.snoop_fanout::mean             1.000119                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.010906                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.010907                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                14254865     99.99%     99.99% # Request fanout histogram
+system.membus.snoop_fanout::1                14254486     99.99%     99.99% # Request fanout histogram
 system.membus.snoop_fanout::2                    1696      0.01%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total            14256561                       # Request fanout histogram
+system.membus.snoop_fanout::total            14256182                       # Request fanout histogram
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 0929c11b9..38633f47f 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,76 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.194947                       # Number of seconds simulated
-sim_ticks                                5194947216500                       # Number of ticks simulated
-final_tick                               5194947216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.194946                       # Number of seconds simulated
+sim_ticks                                5194946000500                       # Number of ticks simulated
+final_tick                               5194946000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 404245                       # Simulator instruction rate (inst/s)
-host_op_rate                                   779175                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16350714303                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 604972                       # Number of bytes of host memory used
-host_seconds                                   317.72                       # Real time elapsed on the host
-sim_insts                                   128436556                       # Number of instructions simulated
-sim_ops                                     247559476                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 842553                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1624008                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34079125299                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 659848                       # Number of bytes of host memory used
+host_seconds                                   152.44                       # Real time elapsed on the host
+sim_insts                                   128436892                       # Number of instructions simulated
+sim_ops                                     247560077                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            821184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9031104                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            821248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9031168                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9881024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       821184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8151488                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8151488                       # Number of bytes written to this memory
+system.physmem.bytes_read::total              9881152                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       821248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          821248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8151616                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8151616                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12831                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141111                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12832                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141112                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                154391                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          127367                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               127367                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                154393                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          127369                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               127369                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158074                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1738440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158086                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1738453                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1902045                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158074                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158074                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1569119                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1569119                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1569119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 1902070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158086                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158086                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1569144                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1569144                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1569144                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158074                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1738440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              158086                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1738453                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3471164                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        154391                       # Number of read requests accepted
-system.physmem.writeReqs                       127367                       # Number of write requests accepted
-system.physmem.readBursts                      154391                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     127367                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9871424                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8149376                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9881024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8151488                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                3471214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        154393                       # Number of read requests accepted
+system.physmem.writeReqs                       127369                       # Number of write requests accepted
+system.physmem.readBursts                      154393                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     127369                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9872000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8149824                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9881152                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8151616                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          55287                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10087                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9529                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9534                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                9814                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9652                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                9653                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10130                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9950                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9948                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                9317                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                9200                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                8918                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                9357                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9066                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9071                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9331                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               9713                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               9915                       # Per bank write bursts
@@ -79,53 +79,53 @@ system.physmem.perBankRdBursts::15              10131                       # Pe
 system.physmem.perBankWrBursts::0                8252                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7742                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7578                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7566                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7567                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7987                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                8326                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7980                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7984                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                7858                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7446                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7447                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                8118                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               7706                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7948                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7949                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               8417                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               8510                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               8023                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7877                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5194947155500                       # Total gap between requests
+system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5194945939500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154391                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154393                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 127367                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151032                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2782                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 127369                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    151022                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2785                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        67                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        39                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        36                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -156,115 +156,114 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10497                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7589                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6415                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        56850                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      316.988566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.004327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.313677                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          20115     35.38%     35.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13762     24.21%     59.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6339     11.15%     70.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3489      6.14%     76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2420      4.26%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1597      2.81%     83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1162      2.04%     85.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          977      1.72%     87.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6989     12.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          56850                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5891                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.179766                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      623.896687                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5890     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7744                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        56869                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      316.898416                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.066814                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.232113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          20064     35.28%     35.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13820     24.30%     59.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6395     11.25%     70.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3441      6.05%     76.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2422      4.26%     81.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1595      2.80%     83.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1163      2.05%     85.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          983      1.73%     87.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6986     12.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          56869                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5701                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.056657                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      634.190971                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5700     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5891                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5891                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.615006                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.434725                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       14.404388                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4837     82.11%     82.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             110      1.87%     83.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              36      0.61%     84.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             242      4.11%     88.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              18      0.31%     89.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             210      3.56%     92.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              69      1.17%     93.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               3      0.05%     93.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.22%     94.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              22      0.37%     94.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.14%     94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.10%     94.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             244      4.14%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.07%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              27      0.46%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            18      0.31%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5891                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1583291001                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4475309751                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    771205000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10265.05                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5701                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5700                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.339649                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.500075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       17.394307                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4849     85.07%     85.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             101      1.77%     86.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              44      0.77%     87.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              52      0.91%     88.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              17      0.30%     88.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              15      0.26%     89.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              60      1.05%     90.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.11%     90.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51             207      3.63%     93.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.18%     94.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.11%     94.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              16      0.28%     94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              91      1.60%     96.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.11%     96.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               3      0.05%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              36      0.63%     96.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83             144      2.53%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.19%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             9      0.16%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             4      0.07%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.05%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             2      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5700                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1573374325                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4465561825                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    771250000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10200.16                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29015.05                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28950.16                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
@@ -274,74 +273,74 @@ system.physmem.busUtil                           0.03                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     125535                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     99190                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     125550                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99170                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18437620.78                       # Average gap between requests
+system.physmem.writeRowHitRate                  77.86                       # Row buffer hit rate for writes
+system.physmem.avgGap                     18437354.72                       # Average gap between requests
 system.physmem.pageHitRate                      79.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  210727440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  114980250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 605896200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                410112720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           339308689200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           137072684295                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2996729192250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3474452282355                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.813767                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4985214188974                       # Time in different power states
+system.physmem_0.actEnergy                  210916440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  115083375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 605927400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                410119200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           339308180640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           137084456790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2996714193750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3474448877595                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.814114                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4985194974722                       # Time in different power states
 system.physmem_0.memoryStateTime::REF    173470440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36262439776                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     36280536278                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  219058560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  119526000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 597183600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                415011600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           339308689200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           137519874945                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2996336934750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3474516278655                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.826083                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4984554950984                       # Time in different power states
+system.physmem_1.actEnergy                  218998080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119493000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 597214800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                415018080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           339308180640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           137426526900                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2996414132250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3474499563750                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.823871                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4984690777488                       # Time in different power states
 system.physmem_1.memoryStateTime::REF    173470440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     36921702766                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     36784611512                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10389894433                       # number of cpu cycles simulated
+system.cpu.numCycles                      10389892001                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.committedInsts                   128436556                       # Number of instructions committed
-system.cpu.committedOps                     247559476                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             232158308                       # Number of integer alu accesses
+system.cpu.committedInsts                   128436892                       # Number of instructions committed
+system.cpu.committedOps                     247560077                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             232158810                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
-system.cpu.num_func_calls                     2315823                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23152916                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    232158308                       # number of integer instructions
+system.cpu.num_func_calls                     2315811                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23152999                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    232158810                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           434959182                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197962963                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434959716                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197963277                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132872914                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95460933                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22321110                       # number of memory refs
-system.cpu.num_load_insts                    13911495                       # Number of load instructions
-system.cpu.num_store_insts                    8409615                       # Number of store instructions
-system.cpu.num_idle_cycles               9773995534.086119                       # Number of idle cycles
-system.cpu.num_busy_cycles               615898898.913881                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.059279                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.940721                       # Percentage of idle cycles
-system.cpu.Branches                          26327382                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                172226      0.07%      0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu                 224809718     90.81%     90.88% # Class of executed instruction
-system.cpu.op_class::IntMult                   140099      0.06%     90.94% # Class of executed instruction
-system.cpu.op_class::IntDiv                    122815      0.05%     90.99% # Class of executed instruction
+system.cpu.num_cc_register_reads            132873102                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95461248                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22321002                       # number of memory refs
+system.cpu.num_load_insts                    13911426                       # Number of load instructions
+system.cpu.num_store_insts                    8409576                       # Number of store instructions
+system.cpu.num_idle_cycles               9774021635.086119                       # Number of idle cycles
+system.cpu.num_busy_cycles               615870365.913881                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.059276                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.940724                       # Percentage of idle cycles
+system.cpu.Branches                          26327440                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                172203      0.07%      0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu                 224810530     90.81%     90.88% # Class of executed instruction
+system.cpu.op_class::IntMult                   140088      0.06%     90.94% # Class of executed instruction
+system.cpu.op_class::IntDiv                    122745      0.05%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCvt                      16      0.00%     90.99% # Class of executed instruction
@@ -368,18 +367,18 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     90.99% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     90.99% # Class of executed instruction
-system.cpu.op_class::MemRead                 13906523      5.62%     96.60% # Class of executed instruction
-system.cpu.op_class::MemWrite                 8409615      3.40%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                 13906455      5.62%     96.60% # Class of executed instruction
+system.cpu.op_class::MemWrite                 8409576      3.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  247561012                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           1623700                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.995481                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20139431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1624212                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.399509                       # Average number of references to valid blocks.
+system.cpu.op_class::total                  247561613                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           1623668                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.995482                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20139358                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1624180                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.399708                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          81561500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.995481                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.995482                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999991                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -388,148 +387,148 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          353
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88718097                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88718097                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12002646                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12002646                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8075476                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8075476                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          88717633                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88717633                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12002599                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12002599                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8075450                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8075450                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data        59092                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total         59092                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20078122                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20078122                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20137214                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20137214                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       907311                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        907311                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       326143                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       326143                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       402797                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       402797                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1233454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1233454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1636251                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1636251                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13562069000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13562069000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18448528971                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18448528971                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  32010597971                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  32010597971                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  32010597971                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  32010597971                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12909957                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12909957                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8401619                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8401619                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       461889                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       461889                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21311576                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21311576                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21773465                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21773465                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070280                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070280                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038819                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.038819                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872065                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.872065                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.057877                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.057877                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.075149                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.075149                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.541692                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.541692                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56565.767075                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56565.767075                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.999808                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25951.999808                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.378706                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19563.378706                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        18014                       # number of cycles access was blocked
+system.cpu.dcache.demand_hits::cpu.data      20078049                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20078049                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20137141                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20137141                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       907290                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        907290                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       326130                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       326130                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       402796                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       402796                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1233420                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1233420                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1636216                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1636216                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13559380500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13559380500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18441171467                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18441171467                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  32000551967                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32000551967                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  32000551967                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32000551967                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12909889                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12909889                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8401580                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8401580                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       461888                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       461888                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21311469                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21311469                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21773357                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21773357                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070279                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070279                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038818                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.038818                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872064                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.872064                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.057876                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.057876                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075148                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075148                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14944.924445                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14944.924445                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56545.461831                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56545.461831                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25944.570355                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25944.570355                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19557.657404                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        19286                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               511                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               514                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.252446                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    37.521401                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1540805                       # number of writebacks
-system.cpu.dcache.writebacks::total           1540805                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          287                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9476                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         9476                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         9763                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         9763                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         9763                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         9763                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907024                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       907024                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316667                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       316667                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402763                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402763                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1223691                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1223691                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1626454                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1626454                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      1540773                       # number of writebacks
+system.cpu.dcache.writebacks::total           1540773                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          285                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9475                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         9475                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9760                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9760                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9760                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9760                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907005                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       907005                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316655                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       316655                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402762                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402762                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1223660                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1223660                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1626422                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1626422                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       560266                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12652957000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12652957000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17148864471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17148864471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6516948000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6516948000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29801821471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29801821471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36318769471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36318769471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95132083500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95132083500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2786304500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2786304500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97918388000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  97918388000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070258                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070258                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037691                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037691                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12650383500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12650383500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17142668967                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17142668967                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6518448000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6518448000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29793052467                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29793052467                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36311500467                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36311500467                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95132085000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95132085000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2786349500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2786349500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97918434500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  97918434500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070257                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070257                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037690                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037690                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871991                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871991                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057419                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057419                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074699                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074699                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13949.969350                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13949.969350                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54154.251851                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54154.251851                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.602488                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.602488                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.041560                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.041560                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22330.031757                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22330.031757                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.242696                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.242696                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.247943                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.247943                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057418                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057418                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074698                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074698                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13947.424215                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13947.424215                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54136.738618                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54136.738618                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         7583                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.052194                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        13349                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         7599                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.756679                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5163358790000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052194                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.replacements         7581                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.052199                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        13343                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         7597                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.756351                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052199                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315762                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315762                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
@@ -538,44 +537,44 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        53077                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        53077                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13349                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13349                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13349                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13349                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13349                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13349                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8793                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8793                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8793                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8793                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8793                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8793                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     96493000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     96493000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     96493000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     96493000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     96493000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     96493000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22142                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        22142                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22142                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        22142                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22142                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        22142                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.397119                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.397119                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.397119                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.397119                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.397119                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.397119                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses        53059                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53059                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13343                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13343                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13343                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13343                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13343                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13343                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8791                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8791                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8791                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8791                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8791                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8791                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     96450500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     96450500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     96450500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     96450500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     96450500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     96450500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22134                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22134                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22134                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22134                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22134                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22134                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.397172                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.397172                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.397172                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.397172                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10971.504948                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10971.504948                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -584,40 +583,40 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2984                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2984                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8793                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8793                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8793                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         8793                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8793                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         8793                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     87700000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     87700000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     87700000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     87700000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     87700000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     87700000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.397119                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.397119                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.397119                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.397119                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.397119                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.397119                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9973.842830                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9973.842830                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9973.842830                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9973.842830                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9973.842830                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9973.842830                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         2983                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2983                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8791                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8791                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8791                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8791                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8791                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8791                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     87659500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     87659500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     87659500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     87659500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.397172                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.397172                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.397172                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.397172                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9971.504948                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9971.504948                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9971.504948                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            790533                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.213577                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144635652                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            791045                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.841244                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements            790489                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.213579                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144635934                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791001                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.851771                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle      164551519500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.213577                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.213579                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.996511                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.996511                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -626,44 +625,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          161
 system.cpu.icache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146217756                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146217756                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144635652                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144635652                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144635652                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144635652                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144635652                       # number of overall hits
-system.cpu.icache.overall_hits::total       144635652                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       791052                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        791052                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       791052                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         791052                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       791052                       # number of overall misses
-system.cpu.icache.overall_misses::total        791052                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11851389500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11851389500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11851389500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11851389500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11851389500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11851389500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145426704                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145426704                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145426704                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145426704                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145426704                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145426704                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005440                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005440                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005440                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005440                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005440                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005440                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.808402                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14981.808402                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.808402                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14981.808402                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.808402                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14981.808402                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146217950                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146217950                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144635934                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144635934                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144635934                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144635934                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144635934                       # number of overall hits
+system.cpu.icache.overall_hits::total       144635934                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791008                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791008                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791008                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791008                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791008                       # number of overall misses
+system.cpu.icache.overall_misses::total        791008                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11846341000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11846341000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11846341000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11846341000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11846341000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11846341000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145426942                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145426942                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145426942                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145426942                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145426942                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145426942                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005439                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005439                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005439                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005439                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005439                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005439                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14976.259406                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14976.259406                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14976.259406                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14976.259406                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14976.259406                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -672,42 +671,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       790533                       # number of writebacks
-system.cpu.icache.writebacks::total            790533                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791052                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       791052                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       791052                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       791052                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       791052                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       791052                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11060337500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11060337500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11060337500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11060337500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11060337500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11060337500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005440                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005440                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005440                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.808402                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.808402                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.808402                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       790489                       # number of writebacks
+system.cpu.icache.writebacks::total            790489                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791008                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       791008                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       791008                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       791008                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       791008                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       791008                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11055333000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11055333000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11055333000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11055333000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11055333000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11055333000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005439                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005439                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005439                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005439                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3383                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.069434                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.069456                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7971                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.tags.sampled_refs         3396                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.tags.avg_refs     2.347173                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5168964583500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069434                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191840                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.191840                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069456                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191841                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.191841                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
@@ -730,12 +729,12 @@ system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4247
 system.cpu.itb_walker_cache.demand_misses::total         4247                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4247                       # number of overall misses
 system.cpu.itb_walker_cache.overall_misses::total         4247                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     44886000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     44886000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     44886000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     44886000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     44886000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     44886000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     44856000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     44856000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     44856000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     44856000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     44856000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     44856000                       # number of overall miss cycles
 system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12217                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.ReadReq_accesses::total        12217                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
@@ -750,12 +749,12 @@ system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.347573
 system.cpu.itb_walker_cache.demand_miss_rate::total     0.347573                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.347573                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_miss_rate::total     0.347573                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10568.872145                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10568.872145                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10568.872145                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10568.872145                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10568.872145                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10568.872145                       # average overall miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10561.808335                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10561.808335                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10561.808335                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10561.808335                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -772,36 +771,36 @@ system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4247
 system.cpu.itb_walker_cache.demand_mshr_misses::total         4247                       # number of demand (read+write) MSHR misses
 system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4247                       # number of overall MSHR misses
 system.cpu.itb_walker_cache.overall_mshr_misses::total         4247                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     40639000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     40639000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     40639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     40639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     40639000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     40639000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     40609000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     40609000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     40609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     40609000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     40609000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     40609000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.347630                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.347630                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.347573                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.347573                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.347573                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.347573                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9568.872145                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9568.872145                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9568.872145                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9568.872145                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9568.872145                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9568.872145                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9561.808335                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9561.808335                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9561.808335                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            87285                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64590.437600                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4366421                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151981                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            28.730045                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87287                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64590.438483                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4366272                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           151983                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            28.728687                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50117.146585                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146882                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3409.592137                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.545650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006347                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146883                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3409.599295                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.554060                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.764727                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -811,140 +810,140 @@ system.cpu.l2cache.tags.occ_percent::total     0.985572                       #
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        64696                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2800                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5473                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56265                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2801                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5467                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56270                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987183                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39229727                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39229727                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1544562                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1544562                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       790520                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       790520                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         39228445                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39228445                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1544529                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1544529                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       790476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       790476                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       200932                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       200932                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       778207                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       778207                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6472                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2856                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280545                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1289873                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6472                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2856                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       778207                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1481477                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2269012                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6472                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2856                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       778207                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1481477                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2269012                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       200921                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       200921                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       778162                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       778162                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6471                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2853                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280522                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1289846                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         6471                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         2853                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       778162                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1481443                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2268929                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         6471                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         2853                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       778162                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1481443                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2268929                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         1406                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         1406                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       113512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       113512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        12832                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        12832                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       113511                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       113511                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        12833                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        12833                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker            1                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28494                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        28500                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28496                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        28502                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12832                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       142006                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        154844                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        12833                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       142007                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        154846                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12832                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       142006                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       154844                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     53960000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     53960000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14442540500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14442540500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1692530000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1692530000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker       147000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst        12833                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       142007                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       154846                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     52182500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     52182500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14440315000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14440315000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1688067000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1688067000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker       119000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3749093000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3749877500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       147000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3748293500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3749050000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       119000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       637500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1692530000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  18191633500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  19884948000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       147000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1688067000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  18188608500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  19877432000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       119000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       637500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1692530000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  18191633500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  19884948000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      1544562                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      1544562                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       790520                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       790520                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1688067000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  18188608500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  19877432000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      1544529                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      1544529                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       790476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       790476                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1726                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1726                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314444                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314444                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       791039                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       791039                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6473                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2861                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1309039                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1318373                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6473                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2861                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       791039                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1623483                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2423856                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6473                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2861                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       791039                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1623483                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2423856                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       790995                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::total      1318348                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6472                       # number of overall (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.inst       790995                       # number of overall (read+write) accesses
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+system.cpu.l2cache.overall_accesses::total      2423775                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.814600                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.814600                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360993                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.360993                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016222                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016222                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001748                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.021767                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.021618                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001748                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016222                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087470                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063883                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001748                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016222                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087470                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063883                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127233.600853                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127233.600853                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131899.158354                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131899.158354                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker       147000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361003                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.361003                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016224                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016224                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001749                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.021769                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.021619                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001749                       # miss rate for demand accesses
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+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087472                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.063886                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000155                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001749                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016224                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087472                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063886                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 37114.153627                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 37114.153627                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127215.115716                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127215.115716                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131541.104964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131541.104964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker       119000                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       127500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131574.822770                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131574.649123                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       147000                       # average overall miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131537.531583                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131536.383412                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       119000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131899.158354                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128104.682197                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128419.234843                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       147000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131541.104964                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128082.478329                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128369.037624                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       119000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131899.158354                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128104.682197                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128419.234843                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131541.104964                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -953,167 +952,167 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        80700                       # number of writebacks
-system.cpu.l2cache.writebacks::total            80700                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        80702                       # number of writebacks
+system.cpu.l2cache.writebacks::total            80702                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1406                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total         1406                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113512                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113512                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        12832                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        12832                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113511                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       113511                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        12833                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        12833                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28494                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28500                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28496                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28502                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12832                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       142006                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12832                       # number of overall MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total       154844                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12833                       # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total       154846                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       560266                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    100407500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    100407500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13307420500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13307420500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1564210000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1564210000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker       137000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     96565500                       # number of UpgradeReq MSHR miss cycles
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 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       587500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3464153000                       # number of ReadSharedReq MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       587500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1564210000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::total  18336508000                       # number of demand (read+write) MSHR miss cycles
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 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       587500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1564210000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16771573500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  18336508000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88302753500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88302753500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2626222500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2626222500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90928976000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90928976000                       # number of overall MSHR uncacheable cycles
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+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2626267500                       # number of WriteReq MSHR uncacheable cycles
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90929022500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90929022500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814600                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.814600                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360993                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360993                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016222                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016222                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000154                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.001748                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.021767                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.021618                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000154                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001748                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016222                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087470                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063883                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000154                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001748                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087470                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063883                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117233.600853                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117233.600853                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121899.158354                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361003                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361003                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016224                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.021769                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.021619                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087472                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063886                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000155                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001749                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016224                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087472                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063886                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68681.009957                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68681.009957                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117215.115716                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117215.115716                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121541.104964                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121574.822770                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121574.649123                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average overall mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121537.531583                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121536.383412                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118104.682197                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118419.234843                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118082.478329                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       109000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118104.682197                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118419.234843                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.233544                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.233544                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.080790                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.080790                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4855758                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425140                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11068                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4855602                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425060                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11070                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1020                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1020                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         546346                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2660536                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2660470                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13920                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1671931                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       790520                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        91754                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1671913                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       790489                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        97528                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2230                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       314450                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       314450                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       791052                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1323669                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       314438                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       314438                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       791008                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1323647                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::MessageReq         1654                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2372611                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5995599                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8612                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19573                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8396395                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101219776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204103080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       232576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       605248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          306160680                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      189298                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3174835                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2372492                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5996122                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        10488                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        22844                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8401946                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101214976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204098920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       232384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       605120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          306151400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      189316                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3174772                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.004492                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.077863                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.077876                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3163101     99.63%     99.63% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               9208      0.29%     99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               2526      0.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3163038     99.63%     99.63% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               9206      0.29%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               2528      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3174835                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5050067000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3174772                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5049912000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       571290                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1186578000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1186512000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2990780492                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2990732492                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       6370500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13189500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13186500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq               216035                       # Transaction distribution
 system.iobus.trans_dist::ReadResp              216035                       # Transaction distribution
@@ -1167,13 +1166,13 @@ system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027280
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  3266375                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4013816                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy              4014316                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy             10045000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy             10060500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy              1094500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1191,7 +1190,7 @@ system.iobus.reqLayer10.occupancy              177500                       # La
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            24284500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            24285000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
@@ -1201,7 +1200,7 @@ system.iobus.reqLayer16.occupancy               10500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           240815899                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           241923874                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1216500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
@@ -1212,12 +1211,12 @@ system.iobus.respLayer1.utilization               0.0                       # La
 system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                47507                       # number of replacements
-system.iocache.tags.tagsinuse                0.108263                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.108260                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47523                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5048330960000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.108263                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         5048330957000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.108260                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006766                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.006766                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1233,14 +1232,14 @@ system.iocache.demand_misses::pc.south_bridge.ide          842
 system.iocache.demand_misses::total               842                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          842                       # number of overall misses
 system.iocache.overall_misses::total              842                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141163690                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    141163690                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6072614209                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   6072614209                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    141163690                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    141163690                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    141163690                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    141163690                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    138525690                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    138525690                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5867864184                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5867864184                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    138525690                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    138525690                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    138525690                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    138525690                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          842                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            842                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
@@ -1257,19 +1256,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167652.838480                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167652.838480                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167652.838480                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           694                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 164519.821853                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 164519.821853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 164519.821853                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           428                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   67                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   33                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.358209                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.969697                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1283,14 +1282,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide          842
 system.iocache.demand_mshr_misses::total          842                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          842                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          842                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     99063690                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     99063690                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3736614209                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3736614209                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     99063690                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     99063690                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     99063690                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     99063690                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     96425690                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3530059456                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3530059456                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     96425690                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96425690                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     96425690                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1299,73 +1298,72 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 117652.838480                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 117652.838480                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 114519.821853                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 114519.821853                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq              546346                       # Transaction distribution
-system.membus.trans_dist::ReadResp             588520                       # Transaction distribution
+system.membus.trans_dist::ReadResp             588523                       # Transaction distribution
 system.membus.trans_dist::WriteReq              13920                       # Transaction distribution
 system.membus.trans_dist::WriteResp             13920                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       127367                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6933                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       127369                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7403                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             2156                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1652                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            113266                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           113266                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         42174                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              18                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            113265                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           113265                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         42177                       # Transaction distribution
 system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
 system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
 system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       452398                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       668134                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       399599                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1520131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1665201                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397971                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1518503                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95512                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        95512                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1617323                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       232479                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1336265                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15017472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16586216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15017728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16586472                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19607872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                19608128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                             1571                       # Total snoops (count)
-system.membus.snoop_fanout::samples            901008                       # Request fanout histogram
+system.membus.snoop_fanout::samples            901025                       # Request fanout histogram
 system.membus.snoop_fanout::mean             1.001836                       # Request fanout histogram
 system.membus.snoop_fanout::stdev            0.042806                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  899354     99.82%     99.82% # Request fanout histogram
+system.membus.snoop_fanout::1                  899371     99.82%     99.82% # Request fanout histogram
 system.membus.snoop_fanout::2                    1654      0.18%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total              901008                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           344294500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              901025                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           344310500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           503567500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           503566000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             4013184                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             4013684                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           852595593                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           852733442                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2359184                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            2359684                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1928199616                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1924956500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           85638132                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy            4280140                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index 0ee8e01b1..dc74457ff 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000121                       # Nu
 sim_ticks                                      121460                       # Number of ticks simulated
 final_tick                                     121460                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19821                       # Simulator instruction rate (inst/s)
-host_op_rate                                    19819                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 376677                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390876                       # Number of bytes of host memory used
-host_seconds                                     0.32                       # Real time elapsed on the host
+host_inst_rate                                  58804                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58798                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1117518                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 412400                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 8c7fdbc65..adb01be8a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000109                       # Nu
 sim_ticks                                      108694                       # Number of ticks simulated
 final_tick                                     108694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  18329                       # Simulator instruction rate (inst/s)
-host_op_rate                                    18327                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 311726                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 397240                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
+host_inst_rate                                  71872                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71865                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1222276                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 417856                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index d98266934..fc2b85717 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000087                       # Nu
 sim_ticks                                       86673                       # Number of ticks simulated
 final_tick                                      86673                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  26202                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26199                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 355322                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391844                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  58973                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58962                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 799609                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411856                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index ee921f3ab..cf623ae19 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000107                       # Nu
 sim_ticks                                      107210                       # Number of ticks simulated
 final_tick                                     107210                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29228                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29224                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 490268                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 394320                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                 108799                       # Simulator instruction rate (inst/s)
+host_op_rate                                   108769                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1824399                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 416280                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 55628ad16..a9f8176e1 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000046                       # Nu
 sim_ticks                                       45733                       # Number of ticks simulated
 final_tick                                      45733                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  16358                       # Simulator instruction rate (inst/s)
-host_op_rate                                    16355                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 290200                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389816                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  42490                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42477                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 753627                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411088                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 4855f53c1..be4c58d22 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                       41712                       # Number of ticks simulated
 final_tick                                      41712                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12099                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12098                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 195791                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 393888                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  38081                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38070                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 616024                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414508                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index a8631d9c5..08266d48d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                       32936                       # Number of ticks simulated
 final_tick                                      32936                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  22566                       # Simulator instruction rate (inst/s)
-host_op_rate                                    22561                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 288279                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390660                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  52774                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52753                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 673978                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 411572                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 7f8b12151..c437c6665 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                       41659                       # Number of ticks simulated
 final_tick                                      41659                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23573                       # Simulator instruction rate (inst/s)
-host_op_rate                                    23567                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 380874                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390976                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  41992                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 678429                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 412928                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 5c45eaf46..586c80689 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                    29949500                       # Number of ticks simulated
 final_tick                                   29949500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25443                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29781                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              165422007                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247956                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                 167534                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196036                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1088591965                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269228                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        4605                       # Number of instructions simulated
 sim_ops                                          5391                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -755,17 +755,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp           425                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          103                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          646                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          647                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          292                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               938                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               939                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20800                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30144                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples          468                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.100427                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 3b3a0c7c5..f429492e1 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    17170000                       # Number of ticks simulated
 final_tick                                   17170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24070                       # Simulator instruction rate (inst/s)
-host_op_rate                                    28186                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               89974051                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249040                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  56453                       # Simulator instruction rate (inst/s)
+host_op_rate                                    66106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              211025109                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270504                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1167,16 +1167,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          293                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          105                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          586                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          587                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          294                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               880                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28224                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples          440                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.100000                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 4d42e5502..63280507a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18741000                       # Number of ticks simulated
 final_tick                                   18741000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27191                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31839                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              110934081                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245436                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  84742                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99228                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              345728368                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266024                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4592                       # Number of instructions simulated
 sim_ops                                          5378                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1082,19 +1082,19 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops          409                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          368                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           41                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean           33                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           44                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          383                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFReq           69                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           41                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          297                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          103                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          626                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          287                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               913                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          636                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          288                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               924                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30912                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                         452                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples          893                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.549832                       # Request fanout histogram
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index be08dbe1d..83487a6ff 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28298500                       # Number of ticks simulated
 final_tick                                   28298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76228                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88939                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              471979620                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246976                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                 286813                       # Simulator instruction rate (inst/s)
+host_op_rate                                   333728                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1769783602                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267436                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        4566                       # Number of instructions simulated
 sim_ops                                          5330                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -556,16 +556,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           43                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          241                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq           98                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          482                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          483                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               764                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               765                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        15488                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              24448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              24512                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples          382                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.083770                       # Request fanout histogram
diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
index 338e36e87..f933f7176 100644
--- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000050                       # Nu
 sim_ticks                                    49855000                       # Number of ticks simulated
 final_tick                                   49855000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93266                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107828                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              931188295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 634440                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 411650                       # Simulator instruction rate (inst/s)
+host_op_rate                                   475781                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4107877451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 655016                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4988                       # Number of instructions simulated
 sim_ops                                          5770                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -629,13 +629,13 @@ system.l2bus.snoop_filter.tot_snoops                0                       # To
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.trans_dist::ReadResp                 348                       # Transaction distribution
-system.l2bus.trans_dist::CleanEvict                60                       # Transaction distribution
+system.l2bus.trans_dist::CleanEvict                70                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 43                       # Transaction distribution
 system.l2bus.trans_dist::ReadExResp                43                       # Transaction distribution
 system.l2bus.trans_dist::ReadSharedReq            348                       # Transaction distribution
-system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          558                       # Packet count per connected master and slave (bytes)
+system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          568                       # Packet count per connected master and slave (bytes)
 system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side          284                       # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count::total                     842                       # Packet count per connected master and slave (bytes)
+system.l2bus.pkt_count::total                     852                       # Packet count per connected master and slave (bytes)
 system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side        15936                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         9088                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    25024                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
index bf796f4ef..010db5b17 100644
--- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
+++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                    53334000                       # Number of ticks simulated
 final_tick                                   53334000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45290                       # Simulator instruction rate (inst/s)
-host_op_rate                                    45279                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              435170568                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 616512                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                 486070                       # Simulator instruction rate (inst/s)
+host_op_rate                                   485474                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4661655450                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 680524                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5548                       # Number of instructions simulated
 sim_ops                                          5548                       # Number of ops (including micro ops) simulated
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
@@ -508,13 +508,13 @@ system.l2bus.snoop_filter.tot_snoops                0                       # To
 system.l2bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.l2bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.l2bus.trans_dist::ReadResp                 315                       # Transaction distribution
-system.l2bus.trans_dist::CleanEvict                70                       # Transaction distribution
+system.l2bus.trans_dist::CleanEvict                71                       # Transaction distribution
 system.l2bus.trans_dist::ReadExReq                 82                       # Transaction distribution
 system.l2bus.trans_dist::ReadExResp                82                       # Transaction distribution
 system.l2bus.trans_dist::ReadSharedReq            315                       # Transaction distribution
-system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          588                       # Packet count per connected master and slave (bytes)
+system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side          589                       # Packet count per connected master and slave (bytes)
 system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side          276                       # Packet count per connected master and slave (bytes)
-system.l2bus.pkt_count::total                     864                       # Packet count per connected master and slave (bytes)
+system.l2bus.pkt_count::total                     865                       # Packet count per connected master and slave (bytes)
 system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side        16576                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side         8832                       # Cumulative packet size per connected master and slave (bytes)
 system.l2bus.pkt_size::total                    25408                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 7302f4619..7b63e03f4 100644
--- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.147149                       # Nu
 sim_ticks                                147148719500                       # Number of ticks simulated
 final_tick                               147148719500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 392484                       # Simulator instruction rate (inst/s)
-host_op_rate                                   394434                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              637618235                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 382304                       # Number of bytes of host memory used
-host_seconds                                   230.78                       # Real time elapsed on the host
+host_inst_rate                                1174056                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1179890                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1907338487                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 402756                       # Number of bytes of host memory used
+host_seconds                                    77.15                       # Real time elapsed on the host
 sim_insts                                    90576862                       # Number of instructions simulated
 sim_ops                                      91026991                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -600,18 +600,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       942334                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          255                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          368                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46609                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46609                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          599                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       900189                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1199                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2836185                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2837384                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        38400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1200                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2836298                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2837498                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        38464                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120904448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          120942848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          120942912                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples       947397                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000132                       # Request fanout histogram
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 459938f5d..31446f740 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,64 +1,64 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000108                       # Number of seconds simulated
-sim_ticks                                   107836000                       # Number of ticks simulated
-final_tick                                  107836000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   107700000                       # Number of ticks simulated
+final_tick                                  107700000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68965                       # Simulator instruction rate (inst/s)
-host_op_rate                                    68965                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                7480497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247424                       # Number of bytes of host memory used
-host_seconds                                    14.42                       # Real time elapsed on the host
-sim_insts                                      994171                       # Number of instructions simulated
-sim_ops                                        994171                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 155633                       # Simulator instruction rate (inst/s)
+host_op_rate                                   155632                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               16853882                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312924                       # Number of bytes of host memory used
+host_seconds                                     6.39                       # Real time elapsed on the host
+sim_insts                                      994522                       # Number of instructions simulated
+sim_ops                                        994522                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            23040                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             5120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst             5248                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst              384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                42560                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        23040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         5120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst         5248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst          384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          128                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           28800                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               360                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                80                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                82                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                 6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   665                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           213657777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           100300456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            47479506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            11869876                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             1780481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7715420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             4154457                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7715420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               394673393                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      213657777                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       47479506                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        1780481                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        4154457                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          267072221                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          213657777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          100300456                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           47479506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           11869876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            1780481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7715420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            4154457                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7715420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              394673393                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           213927577                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           100427112                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            48727948                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11884865                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             3565460                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7725162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             1188487                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7725162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               395171773                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      213927577                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       48727948                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        3565460                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        1188487                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          267409471                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          213927577                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          100427112                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           48727948                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11884865                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            3565460                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7725162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            1188487                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7725162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              395171773                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           666                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         666                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -70,7 +70,7 @@ system.physmem.bytesReadSys                     42624                       # To
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             89                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 114                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  42                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  30                       # Per bank write bursts
@@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       107808000                       # Total gap between requests
+system.physmem.totGap                       107672000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895            2      1.38%     94.48% # By
 system.physmem.bytesPerActivate::896-1023            3      2.07%     96.55% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            5      3.45%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            145                       # Bytes accessed per row activation
-system.physmem.totQLat                        6565250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  19052750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        6586250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  19073750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      3330000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9857.73                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        9889.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28607.73                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         395.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28639.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         395.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      395.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      395.77                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.09                       # Data bus utilization in percentage
@@ -250,169 +250,169 @@ system.physmem.readRowHits                        510                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   76.58                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161873.87                       # Average gap between requests
+system.physmem.avgGap                       161669.67                       # Average gap between requests
 system.physmem.pageHitRate                      76.58                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                     710640                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                     387750                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                   2769000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy               38088540                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy               27477750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy                 76044960                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              749.349855                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE       47969250                       # Time in different power states
+system.physmem_0.actBackEnergy               38199690                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy               27380250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 76058610                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              749.484363                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE       47670750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT        52649750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        52812250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                     355320                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                     193875                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                   2028000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy                6611280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy               32065065                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy               32761500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy                 74015040                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              729.346948                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE       57811250                       # Time in different power states
+system.physmem_1.actBackEnergy               32151420                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy               32685750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 74025645                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              729.451450                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE       57549250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF         3380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT        43803750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        43929750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups                  81652                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            79008                       # Number of conditional branches predicted
+system.cpu0.branchPred.lookups                  81595                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            78953                       # Number of conditional branches predicted
 system.cpu0.branchPred.condIncorrect             1100                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               78985                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  76270                       # Number of BTB hits
+system.cpu0.branchPred.BTBLookups               78929                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  76214                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            96.562638                       # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct            96.560200                       # BTB Hit Percentage
 system.cpu0.branchPred.usedRAS                    645                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               128                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          215673                       # number of cpu cycles simulated
+system.cpu0.numCycles                          215401                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             19729                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        482689                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      81652                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             76915                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       165939                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.icacheStallCycles             19727                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        482343                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      81595                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             76859                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       165670                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu0.fetch.SquashCycles                   2501                       # Number of cycles fetch has spent squashing
 system.cpu0.fetch.TlbCycles                        96                       # Number of cycles fetch has spent waiting for tlb
 system.cpu0.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         1994                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     6734                       # Number of cache lines fetched
+system.cpu0.fetch.PendingTrapStallCycles         1993                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     6732                       # Number of cache lines fetched
 system.cpu0.fetch.IcacheSquashes                  621                       # Number of outstanding Icache misses that were squashed
 system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples            189011                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.553761                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.213837                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples            188739                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.555609                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.213598                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   30617     16.20%     16.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   78326     41.44%     57.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     798      0.42%     58.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1203      0.64%     58.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     614      0.32%     59.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   73725     39.01%     98.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     672      0.36%     98.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     403      0.21%     98.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2653      1.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   30459     16.14%     16.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   78270     41.47%     57.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     797      0.42%     58.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1203      0.64%     58.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     613      0.32%     58.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   73671     39.03%     98.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     671      0.36%     98.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     403      0.21%     98.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2652      1.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              189011                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.378592                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.238059                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   15475                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                18570                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   153063                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  653                       # Number of cycles decode is unblocking
+system.cpu0.fetch.rateDist::total              188739                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.378805                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.239279                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   15463                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                18382                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   152999                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  645                       # Number of cycles decode is unblocking
 system.cpu0.decode.SquashCycles                  1250                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                472193                       # Number of instructions handled by decode
+system.cpu0.decode.DecodedInsts                471851                       # Number of instructions handled by decode
 system.cpu0.rename.SquashCycles                  1250                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   16079                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   2117                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         15116                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   153063                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                 1386                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                469016                       # Number of instructions processed by rename
+system.cpu0.rename.IdleCycles                   16060                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2005                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         15072                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   152998                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                 1354                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                468673                       # Number of instructions processed by rename
 system.cpu0.rename.IQFullEvents                    11                       # Number of times rename has blocked due to IQ full
 system.cpu0.rename.LQFullEvents                    11                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents                   883                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands             320676                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               935403                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          706479                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               307583                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   13093                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               822                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           832                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     4383                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              150037                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              75873                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            73364                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           72959                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    392343                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.SQFullEvents                   851                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands             320440                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               934717                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          705961                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               307367                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   13073                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               821                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           831                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     4337                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              149926                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              75817                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            73307                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           72919                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    392051                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqNonSpecInstsAdded                889                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   388906                       # Number of instructions issued
+system.cpu0.iq.iqInstsIssued                   388622                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued               31                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          12322                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        11733                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedInstsExamined          12300                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11714                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved           330                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       189011                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.057584                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.125737                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples       188739                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.059045                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.124370                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              33687     17.82%     17.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4243      2.24%     20.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              74165     39.24%     59.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              73776     39.03%     98.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1622      0.86%     99.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                890      0.47%     99.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                405      0.21%     99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              33524     17.76%     17.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4207      2.23%     19.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              74141     39.28%     59.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              73776     39.09%     98.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1579      0.84%     99.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                884      0.47%     99.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                404      0.21%     99.88% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                147      0.08%     99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 76      0.04%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 77      0.04%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         189011                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         188739                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     62     21.45%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     21.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                   124     42.91%     64.36% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  103     35.64%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     61     21.18%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     21.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                   124     43.06%     64.24% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  103     35.76%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               164396     42.27%     42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               164274     42.27%     42.27% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.27% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.27% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.27% # Type of FU issued
@@ -441,40 +441,40 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.27% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.27% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.27% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.27% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              149390     38.41%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              75120     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              149282     38.41%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              75066     19.32%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                388906                       # Type of FU issued
-system.cpu0.iq.rate                          1.803221                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        289                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000743                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads            967143                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           405616                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       387054                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                388622                       # Type of FU issued
+system.cpu0.iq.rate                          1.804179                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        288                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000741                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            966302                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           405302                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       386770                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                389195                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                388910                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           72474                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           72419                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2656                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2653                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread0.memOrderViolation           63                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1676                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores         1674                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu0.iew.lsq.thread0.cacheBlocked           22                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu0.iew.iewSquashCycles                  1250                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   2081                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewBlockCycles                   1969                       # Number of cycles IEW is blocking
 system.cpu0.iew.iewUnblockCycles                   38                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             466895                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispatchedInsts             466549                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts              243                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               150037                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               75873                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispLoadInsts               149926                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               75817                       # Number of dispatched store instructions
 system.cpu0.iew.iewDispNonSpecInsts               770                       # Number of dispatched non-speculative instructions
 system.cpu0.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
@@ -482,53 +482,53 @@ system.cpu0.iew.memOrderViolationEvents            63                       # Nu
 system.cpu0.iew.predictedTakenIncorrect           318                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect          991                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.branchMispredicts                1309                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               387894                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               149051                       # Number of load instructions executed
+system.cpu0.iew.iewExecutedInsts               387610                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               148943                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts             1012                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        73663                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      224021                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   76988                       # Number of branches executed
-system.cpu0.iew.exec_stores                     74970                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.798528                       # Inst execution rate
-system.cpu0.iew.wb_sent                        387462                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       387054                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   229603                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   232649                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      1.794634                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.986907                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts          13111                       # The number of squashed insts skipped by commit
+system.cpu0.iew.exec_nop                        73609                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      223859                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   76931                       # Number of branches executed
+system.cpu0.iew.exec_stores                     74916                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.799481                       # Inst execution rate
+system.cpu0.iew.wb_sent                        387178                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       386770                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   229443                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   232488                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      1.795581                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.986903                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts          13089                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts             1100                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       186547                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.432234                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.149146                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples       186278                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.434007                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.148610                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        33930     18.19%     18.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        76047     40.77%     58.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         1940      1.04%     59.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          670      0.36%     60.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          524      0.28%     60.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        72154     38.68%     99.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          534      0.29%     99.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          265      0.14%     99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        33753     18.12%     18.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        76007     40.80%     58.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         1940      1.04%     59.96% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          664      0.36%     60.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          518      0.28%     60.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        72154     38.73%     99.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          496      0.27%     99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          263      0.14%     99.74% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::8          483      0.26%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       186547                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              453726                       # Number of instructions committed
-system.cpu0.commit.committedOps                453726                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       186278                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              453402                       # Number of instructions committed
+system.cpu0.commit.committedOps                453402                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        221578                       # Number of memory references committed
-system.cpu0.commit.loads                       147381                       # Number of loads committed
+system.cpu0.commit.refs                        221416                       # Number of memory references committed
+system.cpu0.commit.loads                       147273                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     76084                       # Number of branches committed
+system.cpu0.commit.branches                     76030                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   305914                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   305698                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass        72816     16.05%     16.05% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu          159248     35.10%     51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass        72762     16.05%     16.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu          159140     35.10%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntMult              0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntDiv               0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     51.15% # Class of committed instruction
@@ -557,103 +557,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     51.15%
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.15% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead         147465     32.50%     83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite         74197     16.35%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead         147357     32.50%     83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite         74143     16.35%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total           453726                       # Class of committed instruction
+system.cpu0.commit.op_class_0::total           453402                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events                  483                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                      651740                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     936154                       # The number of ROB writes
+system.cpu0.rob.rob_reads                      651125                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     935459                       # The number of ROB writes
 system.cpu0.timesIdled                            313                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.idleCycles                          26662                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     380826                       # Number of Instructions Simulated
-system.cpu0.committedOps                       380826                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              0.566330                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.566330                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.765756                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.765756                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  693989                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 312909                       # number of integer regfile writes
+system.cpu0.committedInsts                     380556                       # Number of Instructions Simulated
+system.cpu0.committedOps                       380556                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              0.566017                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.566017                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.766733                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.766733                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  693485                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 312678                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 225890                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 225727                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          141.137199                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             149509                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          141.118700                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             149407                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              171                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           874.321637                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           873.725146                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.137199                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275659                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.275659                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   141.118700                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.275622                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.275622                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1           67                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.330078                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           603167                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          603167                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        75961                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          75961                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        73598                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         73598                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           602739                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          602739                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        75912                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          75912                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        73546                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         73546                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       149559                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          149559                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       149559                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         149559                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          557                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          557                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          557                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          557                       # number of WriteReq misses
+system.cpu0.dcache.demand_hits::cpu0.data       149458                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          149458                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       149458                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         149458                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          553                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          553                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          555                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          555                       # number of WriteReq misses
 system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
 system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1114                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1114                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1114                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1114                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     17293500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     17293500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     34774980                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     34774980                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data         1108                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1108                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1108                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1108                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16789000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     16789000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     34744480                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     34744480                       # number of WriteReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       472500                       # number of SwapReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::total       472500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     52068480                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     52068480                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     52068480                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     52068480                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        76518                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        76518                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        74155                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        74155                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data     51533480                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     51533480                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     51533480                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     51533480                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        76465                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        76465                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        74101                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        74101                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       150673                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       150673                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       150673                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       150673                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007279                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.007279                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007511                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007511                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data       150566                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       150566                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       150566                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       150566                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.007232                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.007232                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007490                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007490                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007393                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.007393                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007393                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.007393                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138                       # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.007359                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.007359                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.007359                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.007359                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667                       # average WriteReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923                       # average SwapReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs          891                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               27                       # number of cycles access was blocked
@@ -664,107 +664,107 @@ system.cpu0.dcache.fast_writes                      0                       # nu
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          375                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          375                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          379                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          379                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          754                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          754                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          754                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          754                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          182                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          182                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          178                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          178                       # number of WriteReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          370                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          370                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          378                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          378                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          748                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          748                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          748                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          748                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          177                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          177                       # number of WriteReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
 system.cpu0.dcache.demand_mshr_misses::cpu0.data          360                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.demand_mshr_misses::total          360                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          360                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          360                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6892000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6892000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8487000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8487000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6853000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6853000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      8423500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      8423500                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       446500                       # number of SwapReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::total       446500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15379000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     15379000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15379000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     15379000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002379                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002379                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002400                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002400                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     15276500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     15276500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     15276500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     15276500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002393                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002393                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002389                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002389                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002389                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002389                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002389                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002389                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002391                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002391                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002391                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002391                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923                       # average SwapReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              315                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          241.200073                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               5951                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          241.159002                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               5949                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              607                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.803954                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             9.800659                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.200073                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471094                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.471094                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.159002                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471014                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.471014                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          292                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          173                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.570312                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             7341                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            7341                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5951                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5951                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5951                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5951                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5951                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5951                       # number of overall hits
+system.cpu0.icache.tags.tag_accesses             7339                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            7339                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst         5949                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           5949                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         5949                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            5949                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         5949                       # number of overall hits
+system.cpu0.icache.overall_hits::total           5949                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          783                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          783                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          783                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           783                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          783                       # number of overall misses
 system.cpu0.icache.overall_misses::total          783                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40367500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     40367500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     40367500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     40367500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     40367500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     40367500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         6734                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         6734                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         6734                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         6734                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         6734                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         6734                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116276                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.116276                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116276                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.116276                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116276                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.116276                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 51554.916986                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 51554.916986                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     40394500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     40394500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     40394500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     40394500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     40394500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     40394500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         6732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         6732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         6732                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         6732                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         6732                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         6732                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116310                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.116310                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116310                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.116310                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116310                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.116310                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 51589.399745                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 51589.399745                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            4                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -787,396 +787,397 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          608
 system.cpu0.icache.demand_mshr_misses::total          608                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          608                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          608                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31309500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     31309500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31309500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     31309500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31309500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     31309500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090288                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.090288                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090288                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.090288                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     31312500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     31312500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     31312500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     31312500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     31312500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     31312500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090315                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090315                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090315                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.090315                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090315                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.090315                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  53782                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            50347                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1277                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               46315                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  45397                       # Number of BTB hits
+system.cpu1.branchPred.lookups                  52270                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            48857                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             1261                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               45038                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  43957                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            98.017921                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    899                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct            97.599805                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                    912                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          162898                       # number of cpu cycles simulated
+system.cpu1.numCycles                          162626                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             29679                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        299544                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      53782                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             46296                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       124703                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   2711                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.icacheStallCycles             30636                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        289541                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      52270                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             44869                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       123502                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   2677                       # Number of cycles fetch has spent squashing
 system.cpu1.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu1.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
 system.cpu1.fetch.PendingTrapStallCycles         1084                       # Number of stall cycles due to pending traps
 system.cpu1.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                    20165                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  457                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            156846                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.909797                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.217375                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines                    21117                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  458                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            156585                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.849098                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.199028                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   53057     33.83%     33.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   52143     33.24%     67.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    5878      3.75%     70.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3526      2.25%     73.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     939      0.60%     73.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   35272     22.49%     96.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1247      0.80%     96.95% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     803      0.51%     97.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3981      2.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   55186     35.24%     35.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   51235     32.72%     67.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    6397      4.09%     72.05% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3507      2.24%     74.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     942      0.60%     74.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   33361     21.31%     96.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1213      0.77%     96.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     812      0.52%     97.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3932      2.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              156846                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.330158                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.838844                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   17882                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                51023                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    83554                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 3022                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  1355                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                284108                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  1355                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   18601                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  22664                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         13899                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    84840                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                15477                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                280728                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                 13732                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total              156585                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.321412                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.780410                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   17913                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                54188                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    79912                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 3224                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1338                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                274398                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1338                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   18610                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  24678                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13550                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    81416                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                16983                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                271226                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                 15241                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                    15                       # Number of times rename has blocked due to LQ full
 system.cpu1.rename.FullRegisterEvents               6                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands             198394                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               541219                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          420944                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               184552                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   13842                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1192                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1257                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    20109                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               79403                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              38032                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            37516                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           32939                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    234221                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               5649                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   235400                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued                7                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          12841                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        10393                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           661                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       156846                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.500835                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.378978                       # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands             191192                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               520363                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          405271                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               177667                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   13525                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1180                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1251                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    21370                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               76128                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              36144                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            36135                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           31079                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    225686                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6135                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   227404                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued                8                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          12625                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        10115                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           706                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       156585                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.452272                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.380275                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              56627     36.10%     36.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              19405     12.37%     48.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              37510     23.92%     72.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              37026     23.61%     96.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3380      2.15%     98.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1607      1.02%     99.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                891      0.57%     99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                204      0.13%     99.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8                196      0.12%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              58755     37.52%     37.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              20747     13.25%     50.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              35642     22.76%     73.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              35172     22.46%     96.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3374      2.15%     98.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1612      1.03%     99.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                878      0.56%     99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                207      0.13%     99.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8                198      0.13%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         156846                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         156585                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     79     24.38%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     24.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    36     11.11%     35.49% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  209     64.51%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     79     24.01%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     24.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    41     12.46%     36.47% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  209     63.53%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               114995     48.85%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               82971     35.25%     84.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              37434     15.90%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               111654     49.10%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               80158     35.25%     84.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              35592     15.65%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                235400                       # Type of FU issued
-system.cpu1.iq.rate                          1.445076                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        324                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001376                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            627977                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           252747                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       233879                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                227404                       # Type of FU issued
+system.cpu1.iq.rate                          1.398325                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        329                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001447                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            611730                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           244482                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       225916                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                235724                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                227733                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           32768                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           30932                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2551                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2495                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu1.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1483                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedStores         1427                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  1355                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   6889                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   69                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             278263                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              133                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                79403                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               38032                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1130                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  1338                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   7175                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   65                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             268817                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              146                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                76128                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               36144                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1126                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
 system.cpu1.iew.memOrderViolationEvents            36                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           442                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         1069                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1511                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               234388                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                78381                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1012                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.predictedTakenIncorrect           440                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1052                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1492                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               226425                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                75137                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts              979                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        38393                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      115730                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   47858                       # Number of branches executed
-system.cpu1.iew.exec_stores                     37349                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.438864                       # Inst execution rate
-system.cpu1.iew.wb_sent                        234148                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       233879                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   133368                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   139978                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      1.435739                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.952778                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts          13605                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           4988                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1277                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       154309                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.714761                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.081585                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                        36996                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      110644                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   46426                       # Number of branches executed
+system.cpu1.iew.exec_stores                     35507                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.392305                       # Inst execution rate
+system.cpu1.iew.wb_sent                        226182                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       225916                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   128242                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   134834                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      1.389175                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.951110                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts          13383                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5429                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1261                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       154086                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.657380                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.063453                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        61394     39.79%     39.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        44430     28.79%     68.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5247      3.40%     71.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         5803      3.76%     75.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1533      0.99%     76.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        32828     21.27%     98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          824      0.53%     98.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          946      0.61%     99.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8         1304      0.85%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        63982     41.52%     41.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        43006     27.91%     69.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5237      3.40%     72.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6258      4.06%     76.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1532      0.99%     77.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        30979     20.11%     97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          844      0.55%     98.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          946      0.61%     99.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8         1302      0.84%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       154309                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              264603                       # Number of instructions committed
-system.cpu1.commit.committedOps                264603                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       154086                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              255379                       # Number of instructions committed
+system.cpu1.commit.committedOps                255379                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        113401                       # Number of memory references committed
-system.cpu1.commit.loads                        76852                       # Number of loads committed
-system.cpu1.commit.membars                       4272                       # Number of memory barriers committed
-system.cpu1.commit.branches                     46786                       # Number of branches committed
+system.cpu1.commit.refs                        108350                       # Number of memory references committed
+system.cpu1.commit.loads                        73633                       # Number of loads committed
+system.cpu1.commit.membars                       4715                       # Number of memory barriers committed
+system.cpu1.commit.branches                     45393                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   182306                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   175866                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass        37574     14.20%     14.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu          109356     41.33%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead          81124     30.66%     86.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite         36549     13.81%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass        36183     14.17%     14.17% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu          106131     41.56%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult              0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.73% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead          78348     30.68%     86.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite         34717     13.59%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total           264603                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events                 1304                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                      430627                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     558953                       # The number of ROB writes
-system.cpu1.timesIdled                            228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           6052                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.commit.op_class_0::total           255379                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events                 1302                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                      420960                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     540023                       # The number of ROB writes
+system.cpu1.timesIdled                            227                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           6041                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu1.quiesceCycles                       45271                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     222757                       # Number of Instructions Simulated
-system.cpu1.committedOps                       222757                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              0.731281                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.731281                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.367463                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.367463                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  407061                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 190501                       # number of integer regfile writes
+system.cpu1.committedInsts                     214481                       # Number of Instructions Simulated
+system.cpu1.committedOps                       214481                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              0.758230                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.758230                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.318860                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.318860                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  391734                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 183502                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 117378                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 112279                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           25.769381                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              42560                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 1520                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           25.736588                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              40830                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1407.931034                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.769381                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050331                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.050331                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    25.736588                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.050267                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.050267                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           328816                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          328816                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        45076                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          45076                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        36319                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         36319                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        81395                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           81395                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        81395                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          81395                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          515                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          515                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          160                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          160                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          675                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           675                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          675                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          675                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     10357000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     10357000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3384000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3384000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       705000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       705000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     13741000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     13741000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     13741000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     13741000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        45591                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        45591                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        36479                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        36479                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        82070                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        82070                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        82070                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        82070                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011296                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.011296                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004386                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004386                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.008225                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.008225                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.008225                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.008225                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data        21150                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total        21150                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037                       # average overall miss latency
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           315852                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          315852                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        43688                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          43688                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        34492                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         34492                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           17                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        78180                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           78180                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        78180                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          78180                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          495                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          495                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          157                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          157                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           51                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          652                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           652                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          652                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          652                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      8967000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      8967000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3364000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      3364000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       599000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       599000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     12331000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     12331000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     12331000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     12331000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        44183                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        44183                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        34649                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        34649                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        78832                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        78832                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        78832                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        78832                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011203                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.011203                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004531                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.004531                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.750000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.750000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.008271                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.008271                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.008271                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.008271                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1185,106 +1186,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          349                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          349                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           53                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          402                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          402                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          402                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          402                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          273                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          273                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          273                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          273                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2153500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2153500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1760500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1760500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       649000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       649000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3914000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      3914000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3914000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      3914000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003641                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003641                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002933                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002933                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003326                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003326                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003326                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003326                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          331                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          331                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           51                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           51                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          382                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          382                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          382                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          382                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          164                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          164                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           51                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1988000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1988000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1748500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1748500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       548000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       548000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3736500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3736500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3736500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3736500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003712                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003712                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003059                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003059                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.750000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.750000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003425                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003425                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003425                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003425                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              383                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           84.449474                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              19585                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           84.417280                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              20534                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              496                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.485887                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            41.399194                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    84.449474                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.164940                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.164940                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    84.417280                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.164877                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.164877                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          113                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.220703                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            20661                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           20661                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        19585                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          19585                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        19585                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           19585                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        19585                       # number of overall hits
-system.cpu1.icache.overall_hits::total          19585                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          580                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          580                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          580                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           580                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          580                       # number of overall misses
-system.cpu1.icache.overall_misses::total          580                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14033000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     14033000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     14033000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     14033000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     14033000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     14033000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        20165                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        20165                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        20165                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        20165                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        20165                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        20165                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028763                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028763                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028763                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028763                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028763                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028763                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 24194.827586                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 24194.827586                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses            21613                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           21613                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        20534                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          20534                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        20534                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           20534                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        20534                       # number of overall hits
+system.cpu1.icache.overall_hits::total          20534                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          583                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          583                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          583                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           583                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          583                       # number of overall misses
+system.cpu1.icache.overall_misses::total          583                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     14299500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     14299500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     14299500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     14299500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     14299500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     14299500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        21117                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        21117                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        21117                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        21117                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        21117                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        21117                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.027608                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.027608                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.027608                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.027608                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.027608                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.027608                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24527.444254                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24527.444254                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs          128                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
@@ -1295,408 +1296,407 @@ system.cpu1.icache.fast_writes                      0                       # nu
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.writebacks::writebacks          383                       # number of writebacks
 system.cpu1.icache.writebacks::total              383                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           84                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           84                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           84                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           84                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           84                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           84                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           87                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           87                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           87                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           87                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           87                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           87                       # number of overall MSHR hits
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          496                       # number of ReadReq MSHR misses
 system.cpu1.icache.ReadReq_mshr_misses::total          496                       # number of ReadReq MSHR misses
 system.cpu1.icache.demand_mshr_misses::cpu1.inst          496                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.demand_mshr_misses::total          496                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          496                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          496                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11668000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total     11668000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11668000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total     11668000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11668000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total     11668000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024597                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024597                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024597                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024597                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst     11785500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total     11785500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst     11785500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total     11785500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst     11785500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total     11785500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023488                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.023488                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023488                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.023488                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023488                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.023488                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  46151                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            42669                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1261                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               38744                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  37721                       # Number of BTB hits
+system.cpu2.branchPred.lookups                  51016                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            47608                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             1273                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               43707                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  42688                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.359591                       # BTB Hit Percentage
+system.cpu2.branchPred.BTBHitPct            97.668566                       # BTB Hit Percentage
 system.cpu2.branchPred.usedRAS                    903                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          162526                       # number of cpu cycles simulated
+system.cpu2.numCycles                          162253                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             35053                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        247865                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      46151                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             38624                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       123337                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   2679                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles             31836                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        280333                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      51016                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             43591                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       126252                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   2703                       # Number of cycles fetch has spent squashing
 system.cpu2.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu2.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1154                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    26088                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  455                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            160896                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.540529                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.092892                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles         1153                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    22874                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  441                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            160605                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.745481                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.165535                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   69454     43.17%     43.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   47444     29.49%     72.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    8853      5.50%     78.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3439      2.14%     80.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     969      0.60%     80.90% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   24720     15.36%     96.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1203      0.75%     97.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     808      0.50%     97.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    4006      2.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   60810     37.86%     37.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   50841     31.66%     69.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    7311      4.55%     74.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3498      2.18%     76.25% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     961      0.60%     76.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   31234     19.45%     96.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1226      0.76%     97.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     786      0.49%     97.55% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3938      2.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              160896                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.283961                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.525079                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   17877                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                74268                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    63015                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 4387                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  1339                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                232406                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  1339                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   18566                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  36272                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         13923                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    64728                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                26058                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                229231                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                 23352                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                    13                       # Number of times rename has blocked due to LQ full
+system.cpu2.fetch.rateDist::total              160605                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.314423                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.727752                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   17488                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                62772                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    75260                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 3724                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  1351                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                265175                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  1351                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   18185                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  29493                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         13900                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    76790                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                20876                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                262017                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                 18650                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
 system.cpu2.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands             159189                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               426806                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          335096                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               145681                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   13508                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1198                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1266                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    30557                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               61312                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              27565                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            29913                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           22477                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    187400                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               8554                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   191519                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               13                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          12551                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        10065                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           731                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       160896                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.190328                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.355636                       # Number of insts issued each cycle
+system.cpu2.rename.RenamedOperands             183428                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               498093                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          388599                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               169446                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   13982                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1189                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1258                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    25354                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               72684                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              33991                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            34917                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           28890                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    216663                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               7106                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   219007                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued               19                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          13119                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        11098                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           687                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       160605                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.363637                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.376138                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              73129     45.45%     45.45% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              27885     17.33%     62.78% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              27023     16.80%     79.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              26608     16.54%     96.11% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3367      2.09%     98.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1611      1.00%     99.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                866      0.54%     99.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                211      0.13%     99.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                196      0.12%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              64456     40.13%     40.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              23625     14.71%     54.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              33318     20.75%     75.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              32915     20.49%     96.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3374      2.10%     98.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1611      1.00%     99.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                893      0.56%     99.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                212      0.13%     99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                201      0.13%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         160896                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         160605                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     80     24.02%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     24.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    44     13.21%     37.24% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  209     62.76%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     80     23.32%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    54     15.74%     39.07% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  209     60.93%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu                96792     50.54%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.54% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               67722     35.36%     85.90% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              27005     14.10%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               108075     49.35%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.35% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               77606     35.44%     84.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              33326     15.22%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                191519                       # Type of FU issued
-system.cpu2.iq.rate                          1.178390                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        333                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001739                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            544280                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           208542                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       190032                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                219007                       # Type of FU issued
+system.cpu2.iq.rate                          1.349787                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        343                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001566                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            598981                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           236927                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       217448                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                191852                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                219350                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           22329                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           28643                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2475                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2671                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1441                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1575                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  1339                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   9482                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewSquashCycles                  1351                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   8096                       # Number of cycles IEW is blocking
 system.cpu2.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             226726                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              191                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                61312                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               27565                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1142                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewDispatchedInsts             259522                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              168                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                72684                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               33991                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1139                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           430                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         1052                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1482                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               190532                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                60316                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts              987                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            39                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           443                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         1062                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1505                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               217972                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                71586                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1035                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        30772                       # number of nop insts executed
-system.cpu2.iew.exec_refs                       87235                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   40210                       # Number of branches executed
-system.cpu2.iew.exec_stores                     26919                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.172317                       # Inst execution rate
-system.cpu2.iew.wb_sent                        190296                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       190032                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   104798                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   111375                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.169241                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.940947                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts          13298                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           7823                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1261                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       158397                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.347140                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.933730                       # Number of insts commited each cycle
+system.cpu2.iew.exec_nop                        35753                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      104818                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   45124                       # Number of branches executed
+system.cpu2.iew.exec_stores                     33232                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.343408                       # Inst execution rate
+system.cpu2.iew.wb_sent                        217734                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       217448                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   122408                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   129014                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.340179                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.948796                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts          13957                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           6419                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1273                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       158015                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.553777                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.025126                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        80708     50.95%     50.95% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        36780     23.22%     74.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5258      3.32%     77.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         8633      5.45%     82.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1531      0.97%     83.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        22393     14.14%     98.05% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          849      0.54%     98.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7          955      0.60%     99.19% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8         1290      0.81%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        70555     44.65%     44.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        41677     26.38%     71.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         5250      3.32%     74.35% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         7214      4.57%     78.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1535      0.97%     79.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        28695     18.16%     98.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          838      0.53%     98.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          950      0.60%     99.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8         1301      0.82%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       158397                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              213383                       # Number of instructions committed
-system.cpu2.commit.committedOps                213383                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       158015                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              245520                       # Number of instructions committed
+system.cpu2.commit.committedOps                245520                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                         84961                       # Number of memory references committed
-system.cpu2.commit.loads                        58837                       # Number of loads committed
-system.cpu2.commit.membars                       7109                       # Number of memory barriers committed
-system.cpu2.commit.branches                     39190                       # Number of branches committed
+system.cpu2.commit.refs                        102429                       # Number of memory references committed
+system.cpu2.commit.loads                        70013                       # Number of loads committed
+system.cpu2.commit.membars                       5702                       # Number of memory barriers committed
+system.cpu2.commit.branches                     44083                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   146276                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   168630                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        29980     14.05%     14.05% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu           91333     42.80%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult              0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead          65946     30.90%     87.76% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite         26124     12.24%    100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass        34870     14.20%     14.20% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu          102519     41.76%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult              0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead          75715     30.84%     86.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite         32416     13.20%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total           213383                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events                 1290                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                      383202                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     455861                       # The number of ROB writes
-system.cpu2.timesIdled                            213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           1630                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.commit.op_class_0::total           245520                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events                 1301                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                      415605                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     521544                       # The number of ROB writes
+system.cpu2.timesIdled                            214                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           1648                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu2.quiesceCycles                       45643                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     176294                       # Number of Instructions Simulated
-system.cpu2.committedOps                       176294                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.921903                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.921903                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.084713                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.084713                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  321409                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 151400                       # number of integer regfile writes
+system.cpu2.committedInsts                     204948                       # Number of Instructions Simulated
+system.cpu2.committedOps                       204948                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              0.791679                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.791679                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.263138                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.263138                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  374158                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 175347                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                  88848                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 106430                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           23.120660                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              32242                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1111.793103                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           23.147052                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              38440                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1372.857143                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.120660                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045158                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.045158                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    23.147052                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.045209                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.045209                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           256599                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          256599                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        37491                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          37491                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        25903                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         25903                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           19                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             19                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        63394                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           63394                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        63394                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          63394                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          473                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          473                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          153                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          153                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           49                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           49                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          626                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           626                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          626                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          626                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      7957500                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      7957500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3701500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3701500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       605000                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       605000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     11659000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     11659000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     11659000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     11659000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        37964                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        37964                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        26056                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        26056                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        64020                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        64020                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        64020                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        64020                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.012459                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.012459                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.005872                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.005872                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.720588                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.720588                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.009778                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.009778                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.009778                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.009778                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639                       # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           301603                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          301603                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        42391                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          42391                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        32186                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         32186                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        74577                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           74577                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        74577                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          74577                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          529                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          529                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          159                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          159                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          688                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           688                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          688                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          688                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      8601000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      8601000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3593000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3593000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       655000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       655000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     12194000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     12194000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     12194000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     12194000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        42920                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        42920                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        32345                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        32345                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        75265                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        75265                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        75265                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        75265                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.012325                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.012325                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004916                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.004916                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.009141                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.009141                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.009141                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.009141                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1705,106 +1705,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          311                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          311                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           50                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           50                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          361                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          361                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          361                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          361                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          103                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           49                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           49                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          265                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          265                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1647500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1647500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1967500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1967500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       556000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       556000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3615000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3615000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3615000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3615000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004267                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004267                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003953                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003953                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.720588                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.720588                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004139                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004139                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004139                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004139                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          359                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          359                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           53                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           53                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          412                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          412                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          412                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          412                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          170                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          276                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          276                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          276                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          276                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1653000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1653000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1845000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1845000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       597000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       597000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3498000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3498000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3498000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3498000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003961                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003961                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003277                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003277                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003667                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.003667                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003667                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.003667                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9723.529412                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9723.529412                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              386                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           77.580266                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              25515                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse           77.661611                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              22304                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              500                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            51.030000                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            44.608000                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    77.580266                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.151524                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.151524                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    77.661611                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.151683                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.151683                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu2.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            26588                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           26588                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        25515                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          25515                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        25515                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           25515                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        25515                       # number of overall hits
-system.cpu2.icache.overall_hits::total          25515                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          573                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          573                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          573                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           573                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          573                       # number of overall misses
-system.cpu2.icache.overall_misses::total          573                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7955500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      7955500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      7955500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      7955500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      7955500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      7955500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        26088                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        26088                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        26088                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        26088                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        26088                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        26088                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.021964                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.021964                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.021964                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.021964                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.021964                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.021964                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 13883.944154                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 13883.944154                       # average overall miss latency
+system.cpu2.icache.tags.tag_accesses            23374                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           23374                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst        22304                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          22304                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        22304                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           22304                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        22304                       # number of overall hits
+system.cpu2.icache.overall_hits::total          22304                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          570                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          570                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          570                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           570                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          570                       # number of overall misses
+system.cpu2.icache.overall_misses::total          570                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8095000                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      8095000                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      8095000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      8095000                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      8095000                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      8095000                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        22874                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        22874                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        22874                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        22874                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        22874                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        22874                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024919                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.024919                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024919                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.024919                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024919                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.024919                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 14201.754386                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 14201.754386                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            5                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -1815,407 +1815,407 @@ system.cpu2.icache.fast_writes                      0                       # nu
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.writebacks::writebacks          386                       # number of writebacks
 system.cpu2.icache.writebacks::total              386                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           73                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           73                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           73                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           73                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           73                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           70                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           70                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           70                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          500                       # number of ReadReq MSHR misses
 system.cpu2.icache.ReadReq_mshr_misses::total          500                       # number of ReadReq MSHR misses
 system.cpu2.icache.demand_mshr_misses::cpu2.inst          500                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.demand_mshr_misses::total          500                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          500                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          500                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      6895000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      6895000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      6895000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      6895000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      6895000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      6895000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.019166                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.019166                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.019166                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.019166                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst        13790                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total        13790                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst        13790                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total        13790                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst        13790                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total        13790                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7049500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      7049500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7049500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      7049500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7049500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      7049500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021859                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021859                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021859                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.021859                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021859                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.021859                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst        14099                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total        14099                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst        14099                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total        14099                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst        14099                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total        14099                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  52678                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            49211                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1284                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               45275                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  44303                       # Number of BTB hits
+system.cpu3.branchPred.lookups                  49230                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            45728                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             1271                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               41796                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  40803                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            97.853120                       # BTB Hit Percentage
+system.cpu3.branchPred.BTBHitPct            97.624175                       # BTB Hit Percentage
 system.cpu3.branchPred.usedRAS                    906                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               231                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          162161                       # number of cpu cycles simulated
+system.cpu3.numCycles                          161890                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             30846                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        291154                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      52678                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             45209                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       126827                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   2723                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles             32992                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        268412                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      49230                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             41709                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       124419                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   2697                       # Number of cycles fetch has spent squashing
 system.cpu3.fetch.MiscStallCycles                   3                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu3.fetch.NoActiveThreadStallCycles           10                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1166                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    21882                       # Number of cache lines fetched
+system.cpu3.fetch.PendingTrapStallCycles         1165                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    24017                       # Number of cache lines fetched
 system.cpu3.fetch.IcacheSquashes                  451                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            160213                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.817293                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.188011                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::samples            159937                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.678236                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.146445                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   57700     36.01%     36.01% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   51927     32.41%     68.43% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    6814      4.25%     72.68% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3535      2.21%     74.89% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     932      0.58%     75.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   33301     20.79%     96.25% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1242      0.78%     97.03% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     787      0.49%     97.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3975      2.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   63357     39.61%     39.61% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   49486     30.94%     70.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    7847      4.91%     75.46% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3455      2.16%     77.62% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     942      0.59%     78.21% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   28830     18.03%     96.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1207      0.75%     96.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     797      0.50%     97.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    4016      2.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              160213                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.324850                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.795463                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   17433                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                58368                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    79576                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 3465                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  1361                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                275763                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  1361                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   18155                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  26788                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         14101                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    81078                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                18720                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                272367                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                 16743                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                    17                       # Number of times rename has blocked due to LQ full
+system.cpu3.fetch.rateDist::total              159937                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.304095                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.657990                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   17620                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                66098                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    70935                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 3926                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1348                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                252986                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1348                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   18323                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  31370                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         13970                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    72885                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                22031                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                249675                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                 20026                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                    15                       # Number of times rename has blocked due to LQ full
 system.cpu3.rename.FullRegisterEvents               3                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands             191251                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               520897                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          405695                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               177247                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   14004                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1196                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1267                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    23402                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               76309                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              36069                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            36463                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           30962                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    226032                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               6585                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   227862                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued               13                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          13164                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        10986                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           709                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       160213                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.422244                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.377526                       # Number of insts issued each cycle
+system.cpu3.rename.RenamedOperands             174506                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               471658                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          368736                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               160859                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   13647                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1202                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1275                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    26657                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               68456                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              31644                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            33001                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           26549                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    205848                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               7559                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   208921                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued                4                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          12739                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        10220                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           712                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       159937                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.306271                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.372225                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              61467     38.37%     38.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              22016     13.74%     52.11% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              35438     22.12%     74.23% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              35000     21.85%     96.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3395      2.12%     98.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1603      1.00%     99.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                883      0.55%     99.74% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                211      0.13%     99.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                200      0.12%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              67005     41.89%     41.89% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              24940     15.59%     57.49% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              31075     19.43%     76.92% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              30637     19.16%     96.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3376      2.11%     98.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1620      1.01%     99.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                871      0.54%     99.74% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                214      0.13%     99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                199      0.12%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         160213                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         159937                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     82     24.12%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     24.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    49     14.41%     38.53% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  209     61.47%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     82     24.70%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     24.70% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    41     12.35%     37.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  209     62.95%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               111773     49.05%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               80677     35.41%     84.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              35412     15.54%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               103999     49.78%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.78% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               73864     35.35%     85.13% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              31058     14.87%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                227862                       # Type of FU issued
-system.cpu3.iq.rate                          1.405159                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        340                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001492                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            616290                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           245818                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       226322                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                208921                       # Type of FU issued
+system.cpu3.iq.rate                          1.290512                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        332                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001589                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            578115                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           226182                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       207437                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                228202                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                209253                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           30727                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           26373                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2667                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2521                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1566                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           36                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1480                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  1361                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   7576                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   66                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             269910                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              166                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                76309                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               36069                       # Number of dispatched store instructions
+system.cpu3.iew.iewSquashCycles                  1348                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   8395                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   63                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             247262                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              160                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                68456                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               31644                       # Number of dispatched store instructions
 system.cpu3.iew.iewDispNonSpecInsts              1148                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    41                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewIQFullEvents                    36                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            37                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           452                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         1067                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1519                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               226838                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                75201                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1024                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            36                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           438                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         1065                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1503                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               207928                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                67431                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts              993                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        37293                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      110524                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   46686                       # Number of branches executed
-system.cpu3.iew.exec_stores                     35323                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.398844                       # Inst execution rate
-system.cpu3.iew.wb_sent                        226605                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       226322                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   128132                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   134738                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      1.395662                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.950972                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts          13998                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           5876                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1284                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       157615                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.623367                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.050526                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        33855                       # number of nop insts executed
+system.cpu3.iew.exec_refs                       98404                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   43312                       # Number of branches executed
+system.cpu3.iew.exec_stores                     30973                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.284378                       # Inst execution rate
+system.cpu3.iew.wb_sent                        207701                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       207437                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   116002                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   122598                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      1.281345                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.946198                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts          13505                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           6847                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1271                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       157409                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.484744                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.997930                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        67043     42.54%     42.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        43238     27.43%     69.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         5262      3.34%     73.31% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         6673      4.23%     77.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1534      0.97%     78.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        30788     19.53%     98.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          827      0.52%     98.57% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          952      0.60%     99.18% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8         1298      0.82%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        73609     46.76%     46.76% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        39844     25.31%     72.08% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         5242      3.33%     75.41% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         7652      4.86%     80.27% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1542      0.98%     81.25% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        26417     16.78%     98.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          849      0.54%     98.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          951      0.60%     99.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8         1303      0.83%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       157615                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              255867                       # Number of instructions committed
-system.cpu3.commit.committedOps                255867                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       157409                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              233712                       # Number of instructions committed
+system.cpu3.commit.committedOps                233712                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        108145                       # Number of memory references committed
-system.cpu3.commit.loads                        73642                       # Number of loads committed
-system.cpu3.commit.membars                       5159                       # Number of memory barriers committed
-system.cpu3.commit.branches                     45627                       # Number of branches committed
+system.cpu3.commit.refs                         96099                       # Number of memory references committed
+system.cpu3.commit.loads                        65935                       # Number of loads committed
+system.cpu3.commit.membars                       6131                       # Number of memory barriers committed
+system.cpu3.commit.branches                     42256                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   175889                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   160475                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass        36414     14.23%     14.23% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu          106149     41.49%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult              0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     55.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead          78801     30.80%     86.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite         34503     13.48%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass        33044     14.14%     14.14% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu           98438     42.12%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult              0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.26% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead          72066     30.84%     87.09% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite         30164     12.91%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total           255867                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events                 1298                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                      425596                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     542328                       # The number of ROB writes
-system.cpu3.timesIdled                            209                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1948                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.commit.op_class_0::total           233712                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events                 1303                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                      402737                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     496962                       # The number of ROB writes
+system.cpu3.timesIdled                            208                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           1953                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu3.quiesceCycles                       46007                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     214294                       # Number of Instructions Simulated
-system.cpu3.committedOps                       214294                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              0.756722                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.756722                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.321489                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.321489                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  391365                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 183208                       # number of integer regfile writes
+system.cpu3.committedInsts                     194537                       # Number of Instructions Simulated
+system.cpu3.committedOps                       194537                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              0.832181                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.832181                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.201662                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.201662                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  355006                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 166699                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 112150                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 100037                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           24.277315                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              40522                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           24.251319                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              36167                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1447.214286                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1291.678571                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.277315                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047417                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.047417                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.251319                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.047366                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.047366                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           316074                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          316074                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        43937                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          43937                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        34273                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         34273                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        78210                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           78210                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        78210                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          78210                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          514                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          514                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          159                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          159                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          673                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           673                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          673                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          673                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9349000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      9349000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3790500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3790500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       680500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       680500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     13139500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     13139500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     13139500                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     13139500                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        44451                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        44451                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        34432                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        34432                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        78883                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        78883                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        78883                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        78883                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011563                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.011563                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004618                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.004618                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.802817                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008532                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.008532                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008532                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.008532                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146                       # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses           285043                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          285043                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        40546                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          40546                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        29945                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         29945                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           17                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        70491                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           70491                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        70491                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          70491                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          489                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          489                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          149                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          149                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           53                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           53                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          638                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           638                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          638                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          638                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8138500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      8138500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3781500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3781500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       606500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       606500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     11920000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     11920000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     11920000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     11920000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41035                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41035                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        30094                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        30094                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        71129                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        71129                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        71129                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        71129                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011917                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.011917                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004951                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.004951                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.757143                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.757143                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008970                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.008970                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008970                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.008970                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2224,106 +2224,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          347                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          347                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           52                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          399                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          399                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          399                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          399                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          167                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          274                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          274                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          274                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1719000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1719000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2129500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2129500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       623500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       623500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3848500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3848500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3848500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3848500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003757                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003757                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003108                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003108                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003473                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003473                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003473                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003473                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          328                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          328                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           46                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           46                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          374                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          374                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          103                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          103                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           53                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           53                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          264                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          264                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1609000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1609000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2139500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2139500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       553500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       553500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3748500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3748500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3748500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3748500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003923                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003923                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003423                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003423                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.757143                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.757143                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003712                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.003712                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003712                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.003712                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9993.788820                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9993.788820                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              384                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           81.046367                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              21310                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           80.879647                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              23443                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              498                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            42.791165                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            47.074297                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    81.046367                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.158294                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.158294                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    80.879647                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.157968                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.157968                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024          114                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.222656                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            22380                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           22380                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        21310                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          21310                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        21310                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           21310                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        21310                       # number of overall hits
-system.cpu3.icache.overall_hits::total          21310                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          572                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          572                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          572                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           572                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          572                       # number of overall misses
-system.cpu3.icache.overall_misses::total          572                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      8104500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      8104500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      8104500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      8104500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      8104500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      8104500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        21882                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        21882                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        21882                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        21882                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        21882                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        21882                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.026140                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.026140                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.026140                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.026140                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.026140                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.026140                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14168.706294                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14168.706294                       # average overall miss latency
+system.cpu3.icache.tags.tag_accesses            24515                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           24515                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        23443                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          23443                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        23443                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           23443                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        23443                       # number of overall hits
+system.cpu3.icache.overall_hits::total          23443                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          574                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          574                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          574                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           574                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          574                       # number of overall misses
+system.cpu3.icache.overall_misses::total          574                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7717500                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7717500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7717500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7717500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7717500                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7717500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        24017                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        24017                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        24017                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        24017                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        24017                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        24017                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.023900                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.023900                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.023900                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.023900                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.023900                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.023900                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13445.121951                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13445.121951                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2334,66 +2334,66 @@ system.cpu3.icache.fast_writes                      0                       # nu
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.writebacks::writebacks          384                       # number of writebacks
 system.cpu3.icache.writebacks::total              384                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           74                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           74                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           74                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           74                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           76                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           76                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           76                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           76                       # number of overall MSHR hits
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
 system.cpu3.icache.demand_mshr_misses::cpu3.inst          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.demand_mshr_misses::total          498                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          498                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          498                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6912000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      6912000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6912000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      6912000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6912000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      6912000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.022758                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.022758                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.022758                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.022758                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      6640500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      6640500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      6640500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      6640500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      6640500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      6640500                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.020735                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.020735                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.020735                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.020735                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.020735                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.020735                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13334.337349                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13334.337349                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13334.337349                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 13334.337349                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13334.337349                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 13334.337349                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  419.218954                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                  419.138543                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       2347                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                      532                       # Sample count of references to valid blocks.
 system.l2c.tags.avg_refs                     4.411654                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.788461                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      288.048945                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       58.083381                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst       60.484959                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        5.324168                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst        2.350458                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        0.677584                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        2.742702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.718294                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.788194                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      288.006073                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       58.075910                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       61.760427                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        5.322052                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst        2.559109                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        0.677187                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        1.231634                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.717957                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.004395                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000886                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000923                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000942                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000081                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000036                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000039                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000010                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000042                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000019                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.006397                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.006396                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024          532                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          141                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          343                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          138                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.008118                       # Percentage of cache occupancy per task id
 system.l2c.tags.tag_accesses                    25618                       # Number of tag accesses
 system.l2c.tags.data_accesses                   25618                       # Number of data accesses
@@ -2404,9 +2404,9 @@ system.l2c.WritebackClean_hits::total             676                       # nu
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
 system.l2c.ReadCleanReq_hits::cpu0.inst           246                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst           412                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst           491                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst           489                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst           410                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst           489                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst           493                       # number of ReadCleanReq hits
 system.l2c.ReadCleanReq_hits::total              1638                       # number of ReadCleanReq hits
 system.l2c.ReadSharedReq_hits::cpu0.data            5                       # number of ReadSharedReq hits
 system.l2c.ReadSharedReq_hits::cpu1.data            5                       # number of ReadSharedReq hits
@@ -2415,26 +2415,26 @@ system.l2c.ReadSharedReq_hits::cpu3.data           11                       # nu
 system.l2c.ReadSharedReq_hits::total               32                       # number of ReadSharedReq hits
 system.l2c.demand_hits::cpu0.inst                 246                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 410                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 491                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 489                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 489                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 493                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                    1670                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.inst                246                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                410                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                491                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                489                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                489                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                493                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
 system.l2c.overall_hits::total                   1670                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data            27                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            21                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            22                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                89                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
@@ -2442,9 +2442,9 @@ system.l2c.ReadExReq_misses::cpu2.data             12                       # nu
 system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
 system.l2c.ReadCleanReq_misses::cpu0.inst          362                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst           84                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst            9                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst            9                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst           86                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst           11                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst            5                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::total             464                       # number of ReadCleanReq misses
 system.l2c.ReadSharedReq_misses::cpu0.data           75                       # number of ReadSharedReq misses
 system.l2c.ReadSharedReq_misses::cpu1.data            7                       # number of ReadSharedReq misses
@@ -2453,63 +2453,63 @@ system.l2c.ReadSharedReq_misses::cpu3.data            1                       #
 system.l2c.ReadSharedReq_misses::total             84                       # number of ReadSharedReq misses
 system.l2c.demand_misses::cpu0.inst               362                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                84                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                86                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                11                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 5                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   679                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.inst              362                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               84                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               86                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                9                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst               11                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                5                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
 system.l2c.overall_misses::total                  679                       # number of overall misses
-system.l2c.ReadExReq_miss_latency::cpu0.data      7611000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      7622500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data      1059000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data      1210500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data      1399000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total     11279500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     27676500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6293000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst       614000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst       660000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     35243500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data      1210000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data      1404500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total     11296000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     27679500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst      6438500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst       788500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst       341500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     35248000                       # number of ReadCleanReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu0.data      5981500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu1.data       540000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu2.data        82500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu3.data        96500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::total      6700500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     27676500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     13592500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      6293000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     27679500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     13604000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      6438500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data      1599000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       614000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1293000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       660000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1495500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        53223500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     27676500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     13592500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      6293000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       788500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1292500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       341500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data      1501000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        53244500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     27679500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     13604000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      6438500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data      1599000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       614000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1293000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       660000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1495500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       53223500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       788500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1292500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       341500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data      1501000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       53244500                       # number of overall miss cycles
 system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackClean_accesses::writebacks          676                       # number of WritebackClean accesses(hits+misses)
 system.l2c.WritebackClean_accesses::total          676                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           21                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           22                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              92                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
@@ -2555,9 +2555,9 @@ system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # m
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.595395                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.169355                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.018000                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.018072                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.173387                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.022000                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.010040                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_miss_rate::total     0.220742                       # miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.937500                       # miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.583333                       # miss rate for ReadSharedReq accesses
@@ -2566,55 +2566,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.083333
 system.l2c.ReadSharedReq_miss_rate::total     0.724138                       # miss rate for ReadSharedReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.595395                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.169355                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.173387                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.018000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.022000                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.018072                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.010040                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           0.289059                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.595395                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.169355                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.173387                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.018000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.022000                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.018072                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.010040                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.289059                       # miss rate for overall accesses
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80968.085106                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81090.425532                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data       100875                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 116583.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 86103.053435                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76454.419890                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74916.666667                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 68222.222222                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73333.333333                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 75955.818966                       # average ReadCleanReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100833.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 117041.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 86229.007634                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76462.707182                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74866.279070                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 71681.818182                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        68300                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 75965.517241                       # average ReadCleanReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79753.333333                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77142.857143                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        82500                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        96500                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::total 79767.857143                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76454.419890                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 80428.994083                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74916.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 76462.707182                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 80497.041420                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74866.279070                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data        79950                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 68222.222222                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 99461.538462                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 73333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 115038.461538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78385.125184                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76454.419890                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 80428.994083                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74916.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 71681.818182                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 99423.076923                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        68300                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 115461.538462                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 78416.053019                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 76462.707182                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 80497.041420                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74866.279070                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data        79950                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 68222.222222                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 99461.538462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 73333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 115038.461538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78385.125184                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 71681.818182                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 99423.076923                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        68300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 115461.538462                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 78416.053019                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2625,23 +2625,23 @@ system.l2c.fast_writes                              0                       # nu
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            6                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            2                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            5                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            3                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
 system.l2c.UpgradeReq_mshr_misses::cpu0.data           27                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           19                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           21                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           22                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total           89                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
@@ -2649,9 +2649,9 @@ system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       #
 system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          361                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           80                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst            3                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            7                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           82                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst            6                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            2                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::total          451                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.data           75                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.data            7                       # number of ReadSharedReq MSHR misses
@@ -2660,60 +2660,60 @@ system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1
 system.l2c.ReadSharedReq_mshr_misses::total           84                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           80                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           82                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst            3                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst            6                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            7                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            2                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::total              666                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           80                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           82                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst            3                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst            6                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            7                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            2                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             666                       # number of overall MSHR misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       587000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       437000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       459996                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       457500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      1941496                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6671000                       # number of ReadExReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       512500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       359500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       401500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       416000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1689500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      6682500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       929000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1090500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1279000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      9969500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data      1090000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data      1284500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      9986000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     23889000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5285500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst       219000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       495500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     29889000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst      5419500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst       436500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       145500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     29890500                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      5231500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data       470000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data        72500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        86500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::total      5860500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.inst     23889000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     11902500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      5285500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     11914000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      5419500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data      1399000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst       219000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1163000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       495500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data      1365500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     45719000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst       436500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data      1162500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       145500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data      1371000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     45737000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.inst     23889000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     11902500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      5285500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     11914000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      5419500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data      1399000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst       219000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1163000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       495500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data      1365500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     45719000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst       436500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data      1162500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       145500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data      1371000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     45737000                       # number of overall MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.900000                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -2725,9 +2725,9 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.012000                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.004016                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::total     0.214558                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadSharedReq accesses
@@ -2736,129 +2736,128 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.083333
 system.l2c.ReadSharedReq_mshr_miss_rate::total     0.724138                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.004016                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total      0.283525                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.593750                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161290                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.165323                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.014056                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.004016                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.283525                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        21850                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18981.481481                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18921.052632                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19119.047619                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18909.090909                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18983.146067                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71090.425532                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        90875                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634                       # average ReadExReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst        73000                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst        72750                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        72750                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        72500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        86500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143                       # average ReadSharedReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data        69950                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        73000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 68647.147147                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        72750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        72750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 68674.174174                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data        69950                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        73000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 68647.147147                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        72750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        72750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 68674.174174                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                534                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              290                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              89                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               162                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              291                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               159                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq           535                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1741                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1741                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1650                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1650                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        42560                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   42560                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              232                       # Total snoops (count)
-system.membus.snoop_fanout::samples               987                       # Request fanout histogram
+system.membus.snoops                              230                       # Total snoops (count)
+system.membus.snoop_fanout::samples               985                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     987    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     985    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 987                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              936504                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                 985                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              928501                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3712661                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              3.4                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         4933                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1339                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         2364                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.respLayer1.occupancy            3534750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests         4931                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests         1335                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         2366                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadResp              2778                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp              2779                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean          676                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean         1468                       # Transaction distribution
 system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             293                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            293                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              391                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             391                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             294                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            294                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              387                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             387                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadCleanReq          2102                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq          677                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1448                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          592                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1140                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          374                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1151                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          360                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1140                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          376                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  6581                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        53760                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadSharedReq          678                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1530                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          593                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1375                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1386                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          379                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1380                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          363                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  7371                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        59008                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        41216                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        56256                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        41664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        56704                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        41088                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        56448                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 193600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1022                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             3463                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.289633                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.182691                       # Request fanout histogram
+system.toL2Bus.pkt_size::total                 244288                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1020                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             3461                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.293268                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.185819                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1230     35.52%     35.52% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    835     24.11%     59.63% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    563     16.26%     75.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    835     24.11%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   1230     35.54%     35.54% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                    830     23.98%     59.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    557     16.09%     75.61% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    844     24.39%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
@@ -2867,24 +2866,24 @@ system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Re
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               3463                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            3953462                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               3461                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            3950967                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              3.7                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy            911498                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.8                       # Layer utilization (%)
 system.toL2Bus.respLayer1.occupancy            505495                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            746495                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy            746494                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            439455                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            429965                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            752991                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy            752493                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            419474                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy            440466                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            747998                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy            748497                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            434475                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy            422962                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 903a3bff1..1d3cbd064 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140858                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140857                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               18239325                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243264                       # Number of bytes of host memory used
-host_seconds                                     4.81                       # Real time elapsed on the host
+host_inst_rate                                1830828                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1830758                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              237054275                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306784                       # Number of bytes of host memory used
+host_seconds                                     0.37                       # Real time elapsed on the host
 sim_insts                                      677333                       # Number of instructions simulated
 sim_ops                                        677333                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -750,14 +750,14 @@ system.cpu3.icache.writebacks::writebacks          279                       # n
 system.cpu3.icache.writebacks::total              279                       # number of writebacks
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  366.582953                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                  367.545675                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1716                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                      421                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.076010                       # Average number of references to valid blocks.
+system.l2c.tags.sampled_refs                      422                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.066351                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
 system.l2c.tags.occ_blocks::writebacks       0.966439                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.inst      239.426226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       55.207589                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       56.170311                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.inst       59.512205                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.data        6.721185                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu2.inst        1.942787                       # Average occupied blocks per requestor
@@ -766,18 +766,18 @@ system.l2c.tags.occ_blocks::cpu3.inst        0.965459                       # Av
 system.l2c.tags.occ_blocks::cpu3.data        0.905646                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.003653                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.000842                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.000857                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.inst       0.000908                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000103                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.inst       0.000030                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000014                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005594                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::total           0.005608                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          422                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          373                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.006424                       # Percentage of cache occupancy per task id
+system.l2c.tags.age_task_id_blocks_1024::1          374                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.006439                       # Percentage of cache occupancy per task id
 system.l2c.tags.tag_accesses                    19424                       # Number of tag accesses
 system.l2c.tags.data_accesses                   19424                       # Number of data accesses
 system.l2c.WritebackDirty_hits::writebacks            1                       # number of WritebackDirty hits
@@ -944,24 +944,24 @@ system.l2c.no_allocate_misses                       0                       # Nu
 system.membus.trans_dist::ReadResp                423                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              273                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp              80                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               412                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               183                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              136                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq           423                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1747                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1747                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1518                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1518                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        35776                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   35776                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              1108                       # Request fanout histogram
+system.membus.snoop_fanout::samples               879                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    1108    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     879    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                1108                       # Request fanout histogram
+system.membus.snoop_fanout::total                 879                       # Request fanout histogram
 system.toL2Bus.snoop_filter.tot_requests         3918                       # Total number of requests made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_requests         1221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests         1709                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -970,7 +970,7 @@ system.toL2Bus.snoop_filter.hit_single_snoops            0
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadResp              2179                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean          495                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean         1050                       # Transaction distribution
 system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq             275                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp            275                       # Transaction distribution
@@ -978,24 +978,24 @@ system.toL2Bus.trans_dist::ReadExReq              412                       # Tr
 system.toL2Bus.trans_dist::ReadExResp             412                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadCleanReq          1542                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadSharedReq          637                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1077                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          712                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          838                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          696                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          830                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          994                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          618                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          834                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          997                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          624                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  6229                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39040                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  6784                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        43648                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        18752                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        30720                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        30208                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        40704                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        30400                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side        15424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 197568                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total                 233088                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.snoops                               0                       # Total snoops (count)
 system.toL2Bus.snoop_fanout::samples             3918                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            1.246554                       # Request fanout histogram
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 813d17b05..eb0bc0573 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,91 +1,91 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000265                       # Number of seconds simulated
-sim_ticks                                   264840500                       # Number of ticks simulated
-final_tick                                  264840500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000264                       # Number of seconds simulated
+sim_ticks                                   263565500                       # Number of ticks simulated
+final_tick                                  263565500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 127010                       # Simulator instruction rate (inst/s)
-host_op_rate                                   127009                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50783237                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243272                       # Number of bytes of host memory used
-host_seconds                                     5.22                       # Real time elapsed on the host
-sim_insts                                      662366                       # Number of instructions simulated
-sim_ops                                        662366                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 798172                       # Simulator instruction rate (inst/s)
+host_op_rate                                   798158                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              317271660                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306776                       # Number of bytes of host memory used
+host_seconds                                     0.83                       # Real time elapsed on the host
+sim_insts                                      663039                       # Number of instructions simulated
+sim_ops                                        663039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst              448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data              960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             3712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst             3456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data             1408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         3712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst         3456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                 7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                58                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                23                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                54                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data                22                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            68871642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            39873056                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             1691584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             3624823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            14015983                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             5558062                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              966620                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3624823                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               138226593                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       68871642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        1691584                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       14015983                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         966620                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           85545829                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           68871642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           39873056                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            1691584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3624823                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           14015983                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            5558062                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             966620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3624823                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              138226593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst            69204809                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            40065942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             2428239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3642358                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            13112490                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             5342126                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             1214119                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             3885182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               138895265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       69204809                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        2428239                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       13112490                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        1214119                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           85959657                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           69204809                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           40065942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            2428239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3642358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           13112490                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            5342126                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            1214119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            3885182                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              138895265                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          529681                       # number of cpu cycles simulated
+system.cpu0.numCycles                          527131                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     158238                       # Number of instructions committed
-system.cpu0.committedOps                       158238                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               108984                       # Number of integer alu accesses
+system.cpu0.committedInsts                     158196                       # Number of instructions committed
+system.cpu0.committedOps                       158196                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               108956                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        25976                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      108984                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        25969                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      108956                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             315110                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110590                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             315026                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            110562                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        73853                       # number of memory refs
-system.cpu0.num_load_insts                      48895                       # Number of load instructions
-system.cpu0.num_store_insts                     24958                       # Number of store instructions
+system.cpu0.num_mem_refs                        73832                       # number of memory refs
+system.cpu0.num_load_insts                      48881                       # Number of load instructions
+system.cpu0.num_store_insts                     24951                       # Number of store instructions
 system.cpu0.num_idle_cycles                  0.002000                       # Number of idle cycles
-system.cpu0.num_busy_cycles              529680.998000                       # Number of busy cycles
+system.cpu0.num_busy_cycles              527130.998000                       # Number of busy cycles
 system.cpu0.not_idle_fraction                1.000000                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                    0.000000                       # Percentage of idle cycles
-system.cpu0.Branches                            26841                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                23568     14.89%     14.89% # Class of executed instruction
-system.cpu0.op_class::IntAlu                    60795     38.40%     53.29% # Class of executed instruction
+system.cpu0.Branches                            26834                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                23561     14.89%     14.89% # Class of executed instruction
+system.cpu0.op_class::IntAlu                    60781     38.41%     53.29% # Class of executed instruction
 system.cpu0.op_class::IntMult                       0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::IntDiv                        0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     53.29% # Class of executed instruction
@@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc                 0      0.00%     53.29% # Cl
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     53.29% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     53.29% # Class of executed instruction
-system.cpu0.op_class::MemRead                   48979     30.94%     84.23% # Class of executed instruction
-system.cpu0.op_class::MemWrite                  24958     15.77%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                   48965     30.94%     84.23% # Class of executed instruction
+system.cpu0.op_class::MemWrite                  24951     15.77%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                    158300                       # Class of executed instruction
+system.cpu0.op_class::total                    158258                       # Class of executed instruction
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          145.090849                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs              73323                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          145.050771                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs              73302                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           439.059880                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           438.934132                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.090849                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.283381                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.283381                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.050771                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.283302                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.283302                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           295643                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          295643                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48717                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48717                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24724                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24724                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           295559                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          295559                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        48703                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          48703                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        24717                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         24717                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73441                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73441                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73441                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73441                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        73420                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           73420                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        73420                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          73420                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          168                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          168                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
@@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data          351                       #
 system.cpu0.dcache.demand_misses::total           351                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          351                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          351                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      5149000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      5149000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7867000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      7867000                       # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4817500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total      4817500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      6985500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      6985500                       # number of WriteReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       395000                       # number of SwapReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::total       395000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     13016000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     13016000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     13016000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     13016000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48885                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48885                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24907                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24907                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data     11803000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     11803000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     11803000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     11803000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        48871                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        48871                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        24900                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        24900                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73792                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73792                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73792                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73792                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003437                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003437                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007347                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007347                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        73771                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        73771                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        73771                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        73771                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003438                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.003438                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007349                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007349                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004757                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004757                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004757                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004757                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038                       # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004758                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.004758                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004758                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.004758                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148                       # average WriteReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692                       # average SwapReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          351
 system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4981000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4981000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7684000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7684000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4649500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4649500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6802500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6802500                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       369000                       # number of SwapReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::total       369000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12665000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     12665000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12665000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     12665000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003437                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003437                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007347                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007347                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     11452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11452000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     11452000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003438                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003438                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007349                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007349                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004757                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004757                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004757                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004757                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004758                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.004758                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004758                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.004758                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692                       # average SwapReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements              215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          211.456411                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs             157834                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          211.380247                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             157792                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           337.974304                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           337.884368                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   211.456411                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.413001                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.413001                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   211.380247                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.412852                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.412852                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses           158768                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses          158768                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst       157834                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         157834                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       157834                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          157834                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       157834                       # number of overall hits
-system.cpu0.icache.overall_hits::total         157834                       # number of overall hits
+system.cpu0.icache.tags.tag_accesses           158726                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          158726                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst       157792                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         157792                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       157792                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          157792                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       157792                       # number of overall hits
+system.cpu0.icache.overall_hits::total         157792                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
 system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     20139500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     20139500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     20139500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     20139500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     20139500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     20139500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       158301                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       158301                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       158301                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       158301                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       158301                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       158301                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002950                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002950                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002950                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002950                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002950                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002950                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 43125.267666                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 43125.267666                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     20140500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     20140500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     20140500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     20140500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     20140500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     20140500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       158259                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       158259                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       158259                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       158259                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       158259                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       158259                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002951                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002951                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002951                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002951                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002951                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002951                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 43127.408994                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 43127.408994                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -312,158 +312,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          467
 system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     19672500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     19672500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     19672500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     19672500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     19672500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     19672500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002950                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002950                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002950                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002950                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     19673500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     19673500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     19673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     19673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     19673500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     19673500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002951                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.002951                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002951                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.002951                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          529680                       # number of cpu cycles simulated
+system.cpu1.numCycles                          527130                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     168829                       # Number of instructions committed
-system.cpu1.committedOps                       168829                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               111193                       # Number of integer alu accesses
+system.cpu1.committedInsts                     170790                       # Number of instructions committed
+system.cpu1.committedOps                       170790                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               110708                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        32827                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      111193                       # number of integer instructions
+system.cpu1.num_conditional_control_insts        34050                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      110708                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             275699                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            104505                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads             268858                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            101318                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        54535                       # number of memory refs
-system.cpu1.num_load_insts                      41264                       # Number of load instructions
-system.cpu1.num_store_insts                     13271                       # Number of store instructions
-system.cpu1.num_idle_cycles              73879.862241                       # Number of idle cycles
-system.cpu1.num_busy_cycles              455800.137759                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.860520                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.139480                       # Percentage of idle cycles
-system.cpu1.Branches                            34479                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                25261     14.96%     14.96% # Class of executed instruction
-system.cpu1.op_class::IntAlu                    74858     44.33%     59.29% # Class of executed instruction
-system.cpu1.op_class::IntMult                       0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.29% # Class of executed instruction
-system.cpu1.op_class::MemRead                   55471     32.85%     92.14% # Class of executed instruction
-system.cpu1.op_class::MemWrite                  13271      7.86%    100.00% # Class of executed instruction
+system.cpu1.num_mem_refs                        52827                       # number of memory refs
+system.cpu1.num_load_insts                      41019                       # Number of load instructions
+system.cpu1.num_store_insts                     11808                       # Number of store instructions
+system.cpu1.num_idle_cycles              73818.861681                       # Number of idle cycles
+system.cpu1.num_busy_cycles              453311.138319                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.859961                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.140039                       # Percentage of idle cycles
+system.cpu1.Branches                            35703                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                26483     15.50%     15.50% # Class of executed instruction
+system.cpu1.op_class::IntAlu                    74610     43.68%     59.18% # Class of executed instruction
+system.cpu1.op_class::IntMult                       0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     59.18% # Class of executed instruction
+system.cpu1.op_class::MemRead                   57921     33.91%     93.09% # Class of executed instruction
+system.cpu1.op_class::MemWrite                  11808      6.91%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                    168861                       # Class of executed instruction
+system.cpu1.op_class::total                    170822                       # Class of executed instruction
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           26.495164                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              28944                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs           964.800000                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           26.474097                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              25884                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           892.551724                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.495164                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051748                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.051748                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    26.474097                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.051707                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.051707                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           218364                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          218364                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        41094                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          41094                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        13094                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         13094                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        54188                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           54188                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        54188                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          54188                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          163                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          163                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          107                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          107                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          270                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           270                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          270                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          270                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      2920000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      2920000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2149500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      2149500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       245500                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       245500                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      5069500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      5069500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      5069500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      5069500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        41257                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        41257                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        13201                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        13201                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        54458                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        54458                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        54458                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        54458                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003951                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.003951                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008105                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.008105                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.808824                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.808824                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004958                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.004958                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004958                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.004958                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4463.636364                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  4463.636364                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926                       # average overall miss latency
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           211529                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          211529                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        40844                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          40844                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        11631                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         11631                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        52475                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           52475                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        52475                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          52475                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          167                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          167                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          105                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           56                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          272                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           272                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          272                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          272                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      1891500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      1891500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1642500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      1642500                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       250000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       250000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      3534000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      3534000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      3534000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      3534000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        41011                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        41011                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        11736                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        11736                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        52747                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        52747                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        52747                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        52747                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004072                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.004072                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008947                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.008947                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.800000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005157                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.005157                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005157                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.005157                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  4464.285714                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  4464.285714                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -472,99 +472,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          163                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          270                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          270                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          270                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2757000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2757000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      2042500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      2042500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       190500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       190500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4799500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      4799500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4799500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      4799500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003951                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003951                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008105                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008105                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.808824                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.808824                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004958                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.004958                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004958                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.004958                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3463.636364                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3463.636364                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          167                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          167                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          272                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          272                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1724500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1724500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1537500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1537500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       194000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       194000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3262000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3262000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004072                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004072                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.008947                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.008947                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005157                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.005157                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005157                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.005157                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3464.285714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3464.285714                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements              280                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           67.000483                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs             168496                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           66.953040                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             170457                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs           460.371585                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           465.729508                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    67.000483                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.130860                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.130860                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    66.953040                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.130768                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.130768                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses           169228                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses          169228                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst       168496                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         168496                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       168496                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          168496                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       168496                       # number of overall hits
-system.cpu1.icache.overall_hits::total         168496                       # number of overall hits
+system.cpu1.icache.tags.tag_accesses           171189                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          171189                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst       170457                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         170457                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       170457                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          170457                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       170457                       # number of overall hits
+system.cpu1.icache.overall_hits::total         170457                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
 system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5681500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      5681500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      5681500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      5681500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      5681500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      5681500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       168862                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       168862                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       168862                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       168862                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       168862                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       168862                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002167                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002167                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002167                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002167                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002167                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002167                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15523.224044                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15523.224044                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      5688500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      5688500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      5688500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      5688500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      5688500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      5688500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       170823                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       170823                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       170823                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       170823                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       170823                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       170823                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002143                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.002143                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002143                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.002143                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002143                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.002143                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15542.349727                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15542.349727                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -581,158 +581,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          366
 system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5315500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5315500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5315500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5315500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5315500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5315500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002167                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002167                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002167                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002167                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5322500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      5322500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5322500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      5322500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5322500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      5322500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002143                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.002143                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002143                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.002143                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          529681                       # number of cpu cycles simulated
+system.cpu2.numCycles                          527130                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     165415                       # Number of instructions committed
-system.cpu2.committedOps                       165415                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               110386                       # Number of integer alu accesses
+system.cpu2.committedInsts                     168244                       # Number of instructions committed
+system.cpu2.committedOps                       168244                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               109603                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        31522                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      110386                       # number of integer instructions
+system.cpu2.num_conditional_control_insts        33329                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      109603                       # number of integer instructions
 system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             277687                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            105904                       # number of times the integer registers were written
+system.cpu2.num_int_register_reads             267321                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes            101101                       # number of times the integer registers were written
 system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        55033                       # number of memory refs
-system.cpu2.num_load_insts                      40858                       # Number of load instructions
-system.cpu2.num_store_insts                     14175                       # Number of store instructions
-system.cpu2.num_idle_cycles              74150.001720                       # Number of idle cycles
-system.cpu2.num_busy_cycles              455530.998280                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.860010                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.139990                       # Percentage of idle cycles
-system.cpu2.Branches                            33177                       # Number of branches fetched
-system.cpu2.op_class::No_OpClass                23956     14.48%     14.48% # Class of executed instruction
-system.cpu2.op_class::IntAlu                    74457     45.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::IntMult                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::IntDiv                        0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatAdd                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatCmp                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatCvt                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatMult                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatDiv                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAdd                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdAlu                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdCmp                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdCvt                       0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMisc                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMult                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdShift                     0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt                      0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.48% # Class of executed instruction
-system.cpu2.op_class::MemRead                   52859     31.95%     91.43% # Class of executed instruction
-system.cpu2.op_class::MemWrite                  14175      8.57%    100.00% # Class of executed instruction
+system.cpu2.num_mem_refs                        52443                       # number of memory refs
+system.cpu2.num_load_insts                      40463                       # Number of load instructions
+system.cpu2.num_store_insts                     11980                       # Number of store instructions
+system.cpu2.num_idle_cycles              74087.861169                       # Number of idle cycles
+system.cpu2.num_busy_cycles              453042.138831                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.859450                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.140550                       # Percentage of idle cycles
+system.cpu2.Branches                            34984                       # Number of branches fetched
+system.cpu2.op_class::No_OpClass                25761     15.31%     15.31% # Class of executed instruction
+system.cpu2.op_class::IntAlu                    74059     44.01%     59.32% # Class of executed instruction
+system.cpu2.op_class::IntMult                       0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::IntDiv                        0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatAdd                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatCmp                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatCvt                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatMult                     0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatDiv                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::FloatSqrt                     0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdAdd                       0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdAddAcc                    0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdAlu                       0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdCmp                       0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdCvt                       0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdMisc                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdMult                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdMultAcc                   0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdShift                     0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdShiftAcc                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdSqrt                      0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAdd                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatAlu                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCmp                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatCvt                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatDiv                  0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMisc                 0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMult                 0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatMultAcc              0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt                 0      0.00%     59.32% # Class of executed instruction
+system.cpu2.op_class::MemRead                   56476     33.56%     92.88% # Class of executed instruction
+system.cpu2.op_class::MemWrite                  11980      7.12%    100.00% # Class of executed instruction
 system.cpu2.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu2.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu2.op_class::total                    165447                       # Class of executed instruction
+system.cpu2.op_class::total                    168276                       # Class of executed instruction
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           27.486829                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              30625                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1056.034483                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           27.444081                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              26343                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               30                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           878.100000                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.486829                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.053685                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.053685                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    27.444081                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.053602                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.053602                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           220352                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          220352                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        40687                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          40687                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        13994                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         13994                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        54681                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           54681                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        54681                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          54681                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          163                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          163                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          108                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           209996                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          209996                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        40285                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          40285                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        11801                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         11801                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           15                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        52086                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           52086                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        52086                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          52086                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          170                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          170                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          104                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          104                       # number of WriteReq misses
 system.cpu2.dcache.SwapReq_misses::cpu2.data           58                       # number of SwapReq misses
 system.cpu2.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          271                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           271                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          271                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          271                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3093500                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      3093500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2328000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2328000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       260500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       260500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      5421500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      5421500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      5421500                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      5421500                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        40850                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        40850                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        14102                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        14102                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        54952                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        54952                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        54952                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        54952                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003990                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003990                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.007658                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.007658                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.816901                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004932                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004932                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004932                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004932                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4491.379310                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  4491.379310                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055                       # average overall miss latency
+system.cpu2.dcache.demand_misses::cpu2.data          274                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           274                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          274                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          274                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2220000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      2220000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      1703000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      1703000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       260000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       260000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      3923000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      3923000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      3923000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      3923000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        40455                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        40455                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        11905                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        11905                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           73                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        52360                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        52360                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        52360                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        52360                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.004202                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.004202                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.008736                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.008736                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.794521                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.794521                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005233                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.005233                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005233                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.005233                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        16375                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total        16375                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  4482.758621                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  4482.758621                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -741,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          163                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          108                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          170                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          170                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           58                       # number of SwapReq MSHR misses
 system.cpu2.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2930500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2930500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      2220000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      2220000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       202500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       202500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      5150500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      5150500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      5150500                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      5150500                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003990                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003990                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.007658                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.007658                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.816901                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004932                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004932                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004932                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004932                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3491.379310                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3491.379310                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055                       # average overall mshr miss latency
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          274                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          274                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          274                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2050000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2050000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1599000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1599000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       202000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       202000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3649000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3649000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3649000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3649000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004202                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004202                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.008736                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.008736                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.794521                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.794521                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005233                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.005233                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005233                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.005233                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        15375                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        15375                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  3482.758621                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  3482.758621                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.icache.tags.replacements              280                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           69.407713                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs             165082                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse           69.363893                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             167911                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              366                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs           451.043716                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs           458.773224                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    69.407713                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.135562                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.135562                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    69.363893                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.135476                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.135476                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses           165814                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses          165814                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst       165082                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         165082                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       165082                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          165082                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       165082                       # number of overall hits
-system.cpu2.icache.overall_hits::total         165082                       # number of overall hits
+system.cpu2.icache.tags.tag_accesses           168643                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          168643                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst       167911                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         167911                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       167911                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          167911                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       167911                       # number of overall hits
+system.cpu2.icache.overall_hits::total         167911                       # number of overall hits
 system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
 system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
 system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
 system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8101000                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      8101000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      8101000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      8101000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      8101000                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      8101000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       165448                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       165448                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       165448                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       165448                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       165448                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       165448                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002212                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002212                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002212                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002212                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002212                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002212                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 22133.879781                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 22133.879781                       # average overall miss latency
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      8088500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      8088500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      8088500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      8088500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      8088500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      8088500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       168277                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       168277                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       168277                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       168277                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       168277                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       168277                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002175                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.002175                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002175                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.002175                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002175                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.002175                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 22099.726776                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 22099.726776                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -850,158 +850,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst          366
 system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7735000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      7735000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      7735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7735000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      7735000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002212                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002212                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002212                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002212                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      7722500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      7722500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      7722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      7722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      7722500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      7722500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002175                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.002175                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002175                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.002175                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          529680                       # number of cpu cycles simulated
+system.cpu3.numCycles                          527131                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     169884                       # Number of instructions committed
-system.cpu3.committedOps                       169884                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               110793                       # Number of integer alu accesses
+system.cpu3.committedInsts                     165809                       # Number of instructions committed
+system.cpu3.committedOps                       165809                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               112442                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        33553                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      110793                       # number of integer instructions
+system.cpu3.num_conditional_control_insts        30690                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      112442                       # number of integer instructions
 system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             271193                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            102450                       # number of times the integer registers were written
+system.cpu3.num_int_register_reads             289238                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            110642                       # number of times the integer registers were written
 system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        53409                       # number of memory refs
-system.cpu3.num_load_insts                      41060                       # Number of load instructions
-system.cpu3.num_store_insts                     12349                       # Number of store instructions
-system.cpu3.num_idle_cycles              74420.861217                       # Number of idle cycles
-system.cpu3.num_busy_cycles              455259.138783                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.859498                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.140502                       # Percentage of idle cycles
-system.cpu3.Branches                            35208                       # Number of branches fetched
-system.cpu3.op_class::No_OpClass                25987     15.29%     15.29% # Class of executed instruction
-system.cpu3.op_class::IntAlu                    74660     43.94%     59.23% # Class of executed instruction
-system.cpu3.op_class::IntMult                       0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::IntDiv                        0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatAdd                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatCmp                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatCvt                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatMult                     0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatDiv                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt                     0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdAdd                       0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdAlu                       0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdCmp                       0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdCvt                       0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdMisc                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdMult                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdShift                     0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt                      0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.23% # Class of executed instruction
-system.cpu3.op_class::MemRead                   56920     33.50%     92.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite                  12349      7.27%    100.00% # Class of executed instruction
+system.cpu3.num_mem_refs                        57921                       # number of memory refs
+system.cpu3.num_load_insts                      41890                       # Number of load instructions
+system.cpu3.num_store_insts                     16031                       # Number of store instructions
+system.cpu3.num_idle_cycles              74358.001718                       # Number of idle cycles
+system.cpu3.num_busy_cycles              452772.998282                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.858938                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.141062                       # Percentage of idle cycles
+system.cpu3.Branches                            32344                       # Number of branches fetched
+system.cpu3.op_class::No_OpClass                23127     13.95%     13.95% # Class of executed instruction
+system.cpu3.op_class::IntAlu                    75479     45.51%     59.46% # Class of executed instruction
+system.cpu3.op_class::IntMult                       0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::IntDiv                        0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatAdd                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatCmp                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatCvt                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatMult                     0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatDiv                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::FloatSqrt                     0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdAdd                       0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdAddAcc                    0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdAlu                       0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdCmp                       0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdCvt                       0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdMisc                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdMult                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdMultAcc                   0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdShift                     0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdShiftAcc                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdSqrt                      0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAdd                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatAlu                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCmp                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatCvt                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatDiv                  0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMisc                 0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMult                 0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatMultAcc              0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::SimdFloatSqrt                 0      0.00%     59.46% # Class of executed instruction
+system.cpu3.op_class::MemRead                   51204     30.88%     90.33% # Class of executed instruction
+system.cpu3.op_class::MemWrite                  16031      9.67%    100.00% # Class of executed instruction
 system.cpu3.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu3.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu3.op_class::total                    169916                       # Class of executed instruction
+system.cpu3.op_class::total                    165841                       # Class of executed instruction
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           25.679518                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              26969                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           25.704074                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              34341                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs           929.965517                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1184.172414                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.679518                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050155                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.050155                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.704074                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050203                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.050203                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           213856                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          213856                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        40892                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          40892                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        12169                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         12169                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        53061                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           53061                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        53061                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          53061                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          161                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          161                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          107                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          107                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           57                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          268                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           268                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          268                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          268                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2856500                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      2856500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2210000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2210000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       258500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       258500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      5066500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      5066500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      5066500                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      5066500                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41053                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41053                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        12276                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        12276                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        53329                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        53329                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        53329                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        53329                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003922                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003922                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.008716                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.008716                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.802817                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005025                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.005025                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005025                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.005025                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4535.087719                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  4535.087719                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746                       # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses           231895                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          231895                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        41733                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          41733                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        15853                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         15853                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        57586                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           57586                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        57586                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          57586                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          150                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          150                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          109                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          259                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           259                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          259                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          259                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      1542500                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      1542500                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1810500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      1810500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       250500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       250500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      3353000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      3353000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      3353000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      3353000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41883                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41883                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        15962                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        15962                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           67                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           67                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        57845                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        57845                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        57845                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        57845                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003581                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.003581                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006829                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.006829                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.835821                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.835821                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004477                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.004477                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004477                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.004477                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  4473.214286                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  4473.214286                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1010,69 +1010,69 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           57                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          268                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          268                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2695500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2695500                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      2103000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      2103000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       201500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       201500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4798500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      4798500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4798500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      4798500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003922                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003922                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.008716                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.008716                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.005025                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.005025                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.005025                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.005025                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3535.087719                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3535.087719                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          150                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          150                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          109                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          259                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          259                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1392500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1392500                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1701500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1701500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       194500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       194500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3094000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3094000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3094000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3094000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003581                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003581                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.006829                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.006829                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.835821                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.835821                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004477                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.004477                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004477                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.004477                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  9283.333333                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  9283.333333                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3473.214286                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3473.214286                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.icache.tags.replacements              281                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           64.991831                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs             169550                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           64.942208                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             165475                       # Total number of references to valid blocks.
 system.cpu3.icache.tags.sampled_refs              367                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs           461.989101                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs           450.885559                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    64.991831                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.126937                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.126937                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    64.942208                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.126840                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.126840                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses           170284                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses          170284                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst       169550                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         169550                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       169550                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          169550                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       169550                       # number of overall hits
-system.cpu3.icache.overall_hits::total         169550                       # number of overall hits
+system.cpu3.icache.tags.tag_accesses           166209                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          166209                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst       165475                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         165475                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       165475                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          165475                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       165475                       # number of overall hits
+system.cpu3.icache.overall_hits::total         165475                       # number of overall hits
 system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
 system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
 system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
@@ -1085,18 +1085,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst      5473500
 system.cpu3.icache.demand_miss_latency::total      5473500                       # number of demand (read+write) miss cycles
 system.cpu3.icache.overall_miss_latency::cpu3.inst      5473500                       # number of overall miss cycles
 system.cpu3.icache.overall_miss_latency::total      5473500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       169917                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       169917                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       169917                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       169917                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       169917                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       169917                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002160                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002160                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002160                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002160                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002160                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002160                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       165842                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       165842                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       165842                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       165842                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       165842                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       165842                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002213                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.002213                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002213                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.002213                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002213                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.002213                       # miss rate for overall accesses
 system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937                       # average ReadReq miss latency
 system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937                       # average ReadReq miss latency
 system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937                       # average overall miss latency
@@ -1125,12 +1125,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5106500
 system.cpu3.icache.demand_mshr_miss_latency::total      5106500                       # number of demand (read+write) MSHR miss cycles
 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5106500                       # number of overall MSHR miss cycles
 system.cpu3.icache.overall_mshr_miss_latency::total      5106500                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002160                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002160                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002160                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002213                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.002213                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002213                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.002213                       # mshr miss rate for overall accesses
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average ReadReq mshr miss latency
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937                       # average ReadReq mshr miss latency
 system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937                       # average overall mshr miss latency
@@ -1139,30 +1139,30 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937
 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  347.318197                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                  347.185045                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1714                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                      429                       # Sample count of references to valid blocks.
 system.l2c.tags.avg_refs                     3.995338                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.882018                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      230.794628                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       54.021394                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst        6.166785                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        0.835671                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       46.779239                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        6.090035                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        0.944334                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.804093                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.881447                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      230.714883                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       54.006864                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst        6.227742                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        0.835119                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst       46.668024                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        6.066881                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        0.961095                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.822991                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.003522                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.003520                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000824                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000094                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000095                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000013                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000714                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000712                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000093                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.000012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.005300                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.005298                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
@@ -1204,9 +1204,9 @@ system.l2c.overall_hits::cpu3.inst                357                       # nu
 system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
 system.l2c.overall_hits::total                   1218                       # number of overall hits
 system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             14                       # number of ReadExReq misses
@@ -1242,46 +1242,46 @@ system.l2c.overall_misses::cpu3.inst               10                       # nu
 system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
 system.l2c.overall_misses::total                  594                       # number of overall misses
 system.l2c.ReadExReq_miss_latency::cpu0.data      5892000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       842000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       896000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       840000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      8470000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst     16964000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst       821500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3820000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst       553500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total     22159000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       837500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       905000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       836000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      8470500                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst     16965000                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst       831500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst      3806500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst       555500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total     22158500                       # number of ReadCleanReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu0.data      3927500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data       118500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data       476000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data       118000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data       118000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data       475500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data       119000                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::total      4640000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     16964000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     16965000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.data      9819500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst       821500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data       960500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      3820000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data      1372000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       553500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       958000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst       831500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data       955500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      3806500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1380500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       555500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       955000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::total        35269000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     16964000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     16965000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.data      9819500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst       821500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data       960500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      3820000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data      1372000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       553500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       958000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst       831500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data       955500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      3806500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1380500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       555500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       955000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::total       35269000                       # number of overall miss cycles
 system.l2c.WritebackDirty_accesses::writebacks            1                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackDirty_accesses::total            1                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackClean_accesses::writebacks          495                       # number of WritebackClean accesses(hits+misses)
 system.l2c.WritebackClean_accesses::total          495                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           14                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           14                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           14                       # number of ReadExReq accesses(hits+misses)
@@ -1355,37 +1355,37 @@ system.l2c.overall_miss_rate::cpu3.inst      0.027248                       # mi
 system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          0.327815                       # miss rate for overall accesses
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60142.857143                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59733.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data        60000                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 59647.887324                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59522.807018                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 58678.571429                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58769.230769                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        55350                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 59248.663102                       # average ReadCleanReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59821.428571                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60333.333333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59714.285714                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 59651.408451                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59526.315789                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59392.857143                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58561.538462                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst        55550                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 59247.326203                       # average ReadCleanReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        59250                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data        59500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        59000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data        59000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59437.500000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data        59500                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 59522.807018                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 59526.315789                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 58678.571429                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 60031.250000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 58769.230769                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 59652.173913                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst        55350                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data        59875                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 59392.857143                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 59718.750000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 58561.538462                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 60021.739130                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        55550                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 59687.500000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total 59375.420875                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 59522.807018                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 59526.315789                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 58678.571429                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 60031.250000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 58769.230769                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 59652.173913                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst        55350                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data        59875                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 59392.857143                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 59718.750000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 58561.538462                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 60021.739130                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        55550                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total 59375.420875                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
@@ -1395,29 +1395,29 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            7                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            6                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            4                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst           11                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           20                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu1.data            1                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            1                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst             11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 22                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst            11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             5                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                22                       # number of overall MSHR hits
 system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           16                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           14                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           14                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           14                       # number of ReadExReq MSHR misses
@@ -1425,71 +1425,71 @@ system.l2c.ReadExReq_mshr_misses::cpu2.data           15                       #
 system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::cpu0.inst          285                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst            7                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           58                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            4                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst           10                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst           54                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst            5                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::total          354                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu0.data           66                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::cpu1.data            1                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data            8                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data            1                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data            7                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data            2                       # number of ReadSharedReq MSHR misses
 system.l2c.ReadSharedReq_mshr_misses::total           76                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst            7                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           10                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst           58                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           23                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst           54                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data           22                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            5                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst            7                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           10                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst           58                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data           23                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst           54                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data           22                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            5                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data           16                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1418500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       762498                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       864497                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       813997                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      3859492                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       533000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       271000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       269000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       381000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1454000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4902000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       702000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       746000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       700000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      7050000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     14114000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       351500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      2872000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       199000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total     17536500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       697500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       755000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       696000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      7050500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst     14115000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst       500500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst      2674000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst       247500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total     17537000                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data      3267500                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data        49500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       396000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        49500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data       346500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data        99000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::total      3762500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     14114000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     14115000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.data      8169500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst       351500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       751500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      2872000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data      1142000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       199000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       749500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     28349000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     14114000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst       500500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data       747000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      2674000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data      1101500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       247500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       795000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     28350000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     14115000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.data      8169500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst       351500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       751500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      2872000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data      1142000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       199000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       749500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     28349000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst       500500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data       747000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      2674000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data      1101500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       247500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       795000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     28350000                       # number of overall MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1501,80 +1501,79 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadCleanReq_mshr_miss_rate::total     0.226054                       # mshr miss rate for ReadCleanReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.727273                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.636364                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.ReadSharedReq_mshr_miss_rate::total     0.730769                       # mshr miss rate for ReadSharedReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.019126                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.027322                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.600000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.158470                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.884615                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.010899                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.147541                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.846154                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013624                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19357.142857                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19214.285714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        19050                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19131.578947                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        50000                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        49750                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49821.428571                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50333.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49714.285714                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 49651.408451                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst        50050                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst        49500                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data        49500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data        49500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data        49500                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        50100                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        49750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 49561.188811                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        50050                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        49800                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        49500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 49562.937063                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        50100                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        49750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 49561.188811                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        50050                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        49800                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        49500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 49562.937063                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadResp                430                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              271                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               208                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              142                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq           430                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1557                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1557                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1481                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1481                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.physmem.port        36608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total                   36608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              261                       # Total snoops (count)
@@ -1588,53 +1587,53 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                 915                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              677632                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              685132                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2936000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2860000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests         3980                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests         1113                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests         3976                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests         1120                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1854                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadResp              2221                       # Transaction distribution
 system.toL2Bus.trans_dist::WritebackDirty            1                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean          495                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean         1056                       # Transaction distribution
 system.toL2Bus.trans_dist::CleanEvict               1                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq             273                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp            273                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              428                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             428                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              424                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             424                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadCleanReq          1566                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadSharedReq          655                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1077                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1149                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          579                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          849                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          365                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          849                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side         1012                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          372                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          852                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5309                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        39040                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side         1015                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          360                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  5866                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        43648                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        10944                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        30912                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        30912                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        41344                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1664                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        31040                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        41472                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total                 147712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                            1032                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples             2922                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.269678                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           1.154527                       # Request fanout histogram
+system.toL2Bus.pkt_size::total                 183616                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                            1028                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples             2918                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.265250                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           1.153418                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                   1002     34.29%     34.29% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                    787     26.93%     61.23% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    476     16.29%     77.52% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                    657     22.48%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                   1002     34.34%     34.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                    794     27.21%     61.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    468     16.04%     77.59% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                    654     22.41%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::5                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::6                      0      0.00%    100.00% # Request fanout histogram
@@ -1643,24 +1642,24 @@ system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Re
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total               2922                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy            3050992                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total               2918                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy            3048992                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              1.2                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy            700999                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy            495500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy            500989                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy            552489                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy            550995                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy            432972                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy            435970                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy            552491                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy            554485                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy            434474                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy            441968                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy            553492                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy            552992                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy            427974                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy            411482                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 1566487a2..7c2d41959 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.010022                       # Nu
 sim_ticks                                    10021833                       # Number of ticks simulated
 final_tick                                   10021833                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  66575                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 401248                       # Number of bytes of host memory used
-host_seconds                                   150.54                       # Real time elapsed on the host
+host_tick_rate                                 141404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 425972                       # Number of bytes of host memory used
+host_seconds                                    70.87                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39622272                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 760ab889a..02b6c9c1b 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.004723                       # Nu
 sim_ticks                                     4722948                       # Number of ticks simulated
 final_tick                                    4722948                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  22839                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 403984                       # Number of bytes of host memory used
-host_seconds                                   206.79                       # Real time elapsed on the host
+host_tick_rate                                  43612                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 429416                       # Number of bytes of host memory used
+host_seconds                                   108.30                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     38973248                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index edf017693..ac17b1f35 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.007679                       # Nu
 sim_ticks                                     7678882                       # Number of ticks simulated
 final_tick                                    7678882                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  60394                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 401808                       # Number of bytes of host memory used
-host_seconds                                   127.15                       # Real time elapsed on the host
+host_tick_rate                                 131227                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 425824                       # Number of bytes of host memory used
+host_seconds                                    58.52                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0     39687936                       # Number of bytes read from this memory
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 6281c21fd..64e77dffe 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1819 +1,1816 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000541                       # Number of seconds simulated
-sim_ticks                                   540820000                       # Number of ticks simulated
-final_tick                                  540820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000535                       # Number of seconds simulated
+sim_ticks                                   535115500                       # Number of ticks simulated
+final_tick                                  535115500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                               46544616                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216108                       # Number of bytes of host memory used
-host_seconds                                    11.62                       # Real time elapsed on the host
+host_tick_rate                              114251239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237088                       # Number of bytes of host memory used
+host_seconds                                     4.68                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 88157                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 82701                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 84142                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 82645                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 83993                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 79749                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 78765                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 84222                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               664374                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       426368                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5567                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5462                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5416                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5447                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5329                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5472                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5531                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5421                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            470013                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11108                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10881                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10936                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10951                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11102                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10890                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10914                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  11079                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87861                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6662                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5567                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5462                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5416                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5447                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5329                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5472                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5531                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5421                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                50307                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                163006176                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                152917792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                155582264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                152814245                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                155306756                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                147459413                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                145639954                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                155730187                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1228456788                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         788373211                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                10293628                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                10099479                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                10014423                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                10071743                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                 9853556                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                10117969                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                10227063                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                10023668                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              869074738                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         788373211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               173299804                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               163017270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               165596687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               162885988                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               165160312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               157577382                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               155867017                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               165753855                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2097531526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 81574                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 80110                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 79121                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 81238                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 80899                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 79820                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 79202                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 79066                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               641030                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       406208                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5473                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5509                       # Number of bytes written to this memory
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+system.physmem.bytes_written::cpu3               5388                       # Number of bytes written to this memory
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+system.physmem.bytes_written::cpu5               5375                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5435                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5475                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            449807                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  11077                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10999                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10829                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  10993                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  11032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10961                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10910                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  11026                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87827                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6347                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5473                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5509                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5540                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5388                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5404                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5375                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5435                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5475                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49946                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                152441856                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                149705998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                147857799                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                151813954                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                151180446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                149164059                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                148009168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                147755017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1197928298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         759103409                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                10227699                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                10294974                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                10352905                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                10068854                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                10098754                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                10044560                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                10156686                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                10231436                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              840579277                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         759103409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               162669555                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               160000972                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               158210704                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               161882808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               161279200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               159208619                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               158165854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               157986453                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2038507575                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                           99596                       # number of read accesses completed
-system.cpu0.num_writes                          55268                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22066                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             391.486377                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13717                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22459                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.610757                       # Average number of references to valid blocks.
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          55271                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22387                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             391.751313                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13331                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22793                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.584873                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      391.486377                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.764622                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.764622                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              338295                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             338295                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8878                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8878                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1162                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1162                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0               10040                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total              10040                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0              10040                       # number of overall hits
-system.cpu0.l1c.overall_hits::total             10040                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36478                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36478                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23899                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23899                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60377                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60377                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60377                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60377                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    603408975                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    603408975                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    722750184                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    722750184                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1326159159                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1326159159                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1326159159                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1326159159                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          45356                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         45356                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         25061                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        25061                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           70417                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          70417                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          70417                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         70417                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.804260                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.804260                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953633                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.953633                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.857421                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.857421                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.857421                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.857421                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       828428                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      391.751313                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.765139                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.765139                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              338274                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             338274                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8660                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8660                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1174                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1174                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9834                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9834                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9834                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9834                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36517                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36517                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23979                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23979                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60496                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60496                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60496                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60496                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    647463503                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    647463503                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    554640697                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    554640697                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1202104200                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1202104200                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1202104200                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1202104200                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45177                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45177                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25153                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25153                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70330                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70330                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70330                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70330                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.808310                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.808310                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953326                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.953326                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.860173                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.860173                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.860173                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.860173                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       749854                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               62795                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               59820                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    13.192579                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.535172                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9669                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9669                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36478                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36478                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23899                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23899                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60377                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60377                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60377                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60377                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9885                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9885                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5567                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5567                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15452                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15452                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    566933975                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    566933975                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    698852184                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    698852184                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1265786159                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1265786159                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1265786159                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1265786159                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    722511018                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    722511018                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    853790554                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    853790554                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1576301572                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1576301572                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.804260                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.804260                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953633                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953633                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.857421                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.857421                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.857421                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.857421                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177                       # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks           9840                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9840                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36517                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36517                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23979                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23979                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60496                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60496                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60496                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60496                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9959                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9959                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5475                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5475                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15434                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15434                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    610946503                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    610946503                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    530662697                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    530662697                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1141609200                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1141609200                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1141609200                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1141609200                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    751203683                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    751203683                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    933372844                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    933372844                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1684576527                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1684576527                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.808310                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.808310                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953326                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953326                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860173                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.860173                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860173                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.860173                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           98929                       # number of read accesses completed
-system.cpu1.num_writes                          55238                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22532                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             392.132482                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13440                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22931                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.586106                       # Average number of references to valid blocks.
+system.cpu1.num_reads                           99085                       # number of read accesses completed
+system.cpu1.num_writes                          54836                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22258                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             391.296117                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13378                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22654                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.590536                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      392.132482                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.765884                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.765884                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0          387                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              338385                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             338385                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8754                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8754                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1152                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1152                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9906                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9906                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9906                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9906                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36277                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36277                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           24198                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          24198                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60475                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60475                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60475                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60475                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    602891984                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    602891984                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    733995398                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    733995398                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1336887382                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1336887382                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1336887382                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1336887382                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          45031                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         45031                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         25350                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        25350                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           70381                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          70381                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          70381                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         70381                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805601                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.805601                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954556                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.954556                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.859252                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.859252                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.859252                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.859252                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       828861                       # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1      391.296117                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.764250                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.764250                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              336817                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             336817                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8647                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8647                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1131                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1131                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9778                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9778                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9778                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9778                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36589                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36589                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23685                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23685                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60274                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60274                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60274                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60274                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    652011208                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    652011208                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    548619495                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    548619495                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1200630703                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1200630703                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1200630703                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1200630703                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45236                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45236                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24816                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24816                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70052                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70052                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70052                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70052                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.808847                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.808847                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954425                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954425                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.860418                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.860418                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.860418                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.860418                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       748495                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               62856                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               59422                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    13.186665                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.596261                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9918                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9918                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36277                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36277                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        24198                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        24198                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60475                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60475                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60475                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60475                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9741                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9741                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5463                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5463                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15204                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15204                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    566614984                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    566614984                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    709800398                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    709800398                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1276415382                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1276415382                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1276415382                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1276415382                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    713705140                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    713705140                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    858653101                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    858653101                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1572358241                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1572358241                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805601                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805601                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954556                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954556                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.859252                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.859252                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.859252                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.859252                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012                       # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks           9809                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9809                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36589                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36589                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23685                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23685                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60274                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60274                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60274                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60274                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9902                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9902                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5511                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5511                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15413                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15413                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    615423208                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    615423208                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    524934495                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    524934495                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1140357703                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1140357703                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1140357703                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1140357703                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    747152224                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    747152224                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    944376752                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    944376752                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1691528976                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1691528976                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.808847                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.808847                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954425                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954425                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860418                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.860418                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860418                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.860418                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99726                       # number of read accesses completed
-system.cpu2.num_writes                          55227                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22340                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             393.100704                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13463                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22750                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.591780                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99705                       # number of read accesses completed
+system.cpu2.num_writes                          55132                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22489                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             393.363987                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13472                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22889                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.588580                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      393.100704                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.767775                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.767775                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          410                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          400                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.800781                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              338035                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             338035                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8657                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8657                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1109                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1109                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9766                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9766                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9766                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9766                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36622                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36622                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23922                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23922                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60544                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60544                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60544                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60544                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    606579368                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    606579368                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    739451035                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    739451035                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1346030403                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1346030403                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1346030403                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1346030403                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45279                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45279                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25031                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25031                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70310                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70310                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70310                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70310                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.808808                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.808808                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955695                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.955695                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.861101                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.861101                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.861101                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.861101                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       834628                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      393.363987                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.768289                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.768289                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          387                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              339330                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             339330                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8744                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8744                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1142                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1142                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9886                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9886                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9886                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9886                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36705                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36705                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23982                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23982                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60687                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60687                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60687                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60687                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    655863609                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    655863609                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    555301116                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    555301116                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1211164725                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1211164725                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1211164725                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1211164725                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45449                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45449                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25124                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25124                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70573                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70573                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70573                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70573                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807609                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.807609                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954545                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.954545                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.859918                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.859918                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.859918                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.859918                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       744784                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               63193                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               59741                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    13.207602                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.466882                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9768                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9768                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36622                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36622                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23922                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23922                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60544                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60544                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60544                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60544                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9774                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9774                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5417                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5417                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15191                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15191                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    569957368                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    569957368                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    715531035                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    715531035                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1285488403                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1285488403                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1285488403                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1285488403                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    714145091                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    714145091                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    834952155                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    834952155                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1549097246                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1549097246                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.808808                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.808808                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955695                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955695                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.861101                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.861101                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.861101                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.861101                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240                       # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks           9941                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9941                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36705                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36705                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23982                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23982                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60687                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60687                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60687                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60687                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9745                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9745                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5541                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5541                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15286                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15286                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    619160609                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    619160609                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    531319116                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    531319116                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1150479725                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1150479725                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1150479725                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1150479725                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    736103391                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    736103391                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    958643718                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    958643718                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1694747109                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1694747109                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807609                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807609                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954545                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954545                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859918                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.859918                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859918                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.859918                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99494                       # number of read accesses completed
-system.cpu3.num_writes                          54686                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22431                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             392.658378                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13393                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22832                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.586589                       # Average number of references to valid blocks.
+system.cpu3.num_reads                           99493                       # number of read accesses completed
+system.cpu3.num_writes                          55186                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22493                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             393.330553                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13483                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22894                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.588932                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      392.658378                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.766911                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.766911                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_blocks::cpu3      393.330553                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.768224                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.768224                       # Average percentage of cache occupancy
 system.cpu3.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          389                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          390                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
 system.cpu3.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              337999                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             337999                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8615                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8615                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1106                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1106                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9721                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9721                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9721                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9721                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36594                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36594                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23974                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23974                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60568                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60568                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60568                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60568                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    607642440                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    607642440                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    730577546                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    730577546                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1338219986                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1338219986                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1338219986                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1338219986                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45209                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45209                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         25080                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        25080                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70289                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70289                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70289                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70289                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.809441                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.809441                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955901                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.955901                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.861700                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.861700                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.861700                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.861700                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       833585                       # number of cycles access was blocked
+system.cpu3.l1c.tags.tag_accesses              338296                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             338296                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8738                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8738                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1110                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1110                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9848                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9848                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9848                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9848                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36582                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36582                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23939                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23939                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60521                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60521                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60521                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60521                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    654319900                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    654319900                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    552232159                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    552232159                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1206552059                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1206552059                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1206552059                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1206552059                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45320                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45320                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         25049                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        25049                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70369                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70369                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70369                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70369                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807193                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.807193                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955687                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.955687                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.860052                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.860052                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.860052                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.860052                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       748969                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               63208                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               59958                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    13.187967                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.491561                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9871                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9871                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36594                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36594                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23974                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23974                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60568                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60568                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60568                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60568                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9814                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9814                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5449                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5449                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15263                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15263                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    571049440                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    571049440                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    706605546                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    706605546                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1277654986                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1277654986                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1277654986                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1277654986                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    718813002                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    718813002                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    842609106                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    842609106                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1561422108                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1561422108                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.809441                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.809441                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955901                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955901                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.861700                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.861700                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.861700                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.861700                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432                       # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks           9953                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9953                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36582                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36582                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23939                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23939                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60521                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60521                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60521                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60521                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9878                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9878                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5388                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5388                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15266                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15266                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    617737900                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    617737900                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    528295159                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    528295159                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1146033059                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1146033059                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1146033059                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1146033059                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    746486832                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    746486832                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    927844496                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    927844496                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1674331328                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1674331328                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807193                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807193                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955687                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955687                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860052                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.860052                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860052                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.860052                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           99490                       # number of read accesses completed
-system.cpu4.num_writes                          54928                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               22277                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             391.439470                       # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs                 13388                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22671                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.590534                       # Average number of references to valid blocks.
+system.cpu4.num_reads                           99921                       # number of read accesses completed
+system.cpu4.num_writes                          55196                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22380                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             392.777413                       # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs                 13581                       # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22786                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.596024                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      391.439470                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.764530                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.764530                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          372                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              337649                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             337649                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8692                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8692                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1145                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1145                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9837                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9837                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9837                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9837                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36462                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36462                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23928                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23928                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             60390                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            60390                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            60390                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           60390                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    604688688                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    604688688                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    724847511                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    724847511                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1329536199                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1329536199                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1329536199                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1329536199                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          45154                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         45154                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         25073                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        25073                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           70227                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          70227                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          70227                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         70227                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.807503                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.807503                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954333                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.954333                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.859926                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.859926                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.859926                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.859926                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       834109                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      392.777413                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.767143                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.767143                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          394                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              339211                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             339211                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8862                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8862                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1132                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                9994                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               9994                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               9994                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              9994                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36800                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36800                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23778                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23778                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60578                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60578                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60578                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60578                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    655197570                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    655197570                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    548908934                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    548908934                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1204106504                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1204106504                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1204106504                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1204106504                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          45662                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         45662                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         24910                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        24910                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           70572                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          70572                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          70572                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         70572                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.805922                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.805922                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954556                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.954556                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.858386                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.858386                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.858386                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.858386                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       750268                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               63123                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               59848                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    13.214027                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.536225                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9949                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9949                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36462                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36462                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23928                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23928                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        60390                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        60390                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        60390                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        60390                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9946                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9946                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5329                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5329                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15275                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15275                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    568228688                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    568228688                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    700919511                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    700919511                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1269148199                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1269148199                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1269148199                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1269148199                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    727166434                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    727166434                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    837934166                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    837934166                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1565100600                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1565100600                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.807503                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.807503                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954333                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954333                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.859926                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.859926                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.859926                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.859926                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741                       # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks           9770                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9770                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36800                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36800                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23778                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23778                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60578                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60578                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60578                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60578                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9925                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9925                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5406                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5406                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15331                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15331                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    618398570                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    618398570                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    525131934                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    525131934                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1143530504                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1143530504                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1143530504                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1143530504                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    750294225                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    750294225                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    944567825                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    944567825                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1694862050                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1694862050                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.805922                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.805922                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954556                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954556                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858386                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.858386                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858386                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.858386                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99495                       # number of read accesses completed
-system.cpu5.num_writes                          55318                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22409                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             392.682039                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13393                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22790                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.587670                       # Average number of references to valid blocks.
+system.cpu5.num_reads                           99482                       # number of read accesses completed
+system.cpu5.num_writes                          55607                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22456                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             392.242325                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13457                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22866                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.588516                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      392.682039                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.766957                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.766957                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          381                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.744141                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              337688                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             337688                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8637                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8637                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1146                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1146                       # number of WriteReq hits
+system.cpu5.l1c.tags.occ_blocks::cpu5      392.242325                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.766098                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.766098                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          410                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.800781                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              338143                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             338143                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8578                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8578                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1205                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1205                       # number of WriteReq hits
 system.cpu5.l1c.demand_hits::cpu5                9783                       # number of demand (read+write) hits
 system.cpu5.l1c.demand_hits::total               9783                       # number of demand (read+write) hits
 system.cpu5.l1c.overall_hits::cpu5               9783                       # number of overall hits
 system.cpu5.l1c.overall_hits::total              9783                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36329                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36329                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           24118                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          24118                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60447                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60447                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60447                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60447                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    601479868                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    601479868                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    729882091                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    729882091                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1331361959                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1331361959                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1331361959                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1331361959                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          44966                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         44966                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         25264                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        25264                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70230                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70230                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70230                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70230                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.807922                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.807922                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954639                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.954639                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.860701                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.860701                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.860701                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.860701                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       826632                       # number of cycles access was blocked
+system.cpu5.l1c.ReadReq_misses::cpu5            36239                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36239                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           24308                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          24308                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60547                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60547                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60547                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60547                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    647043171                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    647043171                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    559180438                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    559180438                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1206223609                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1206223609                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1206223609                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1206223609                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          44817                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         44817                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25513                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25513                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           70330                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          70330                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          70330                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         70330                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808599                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.808599                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952769                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.952769                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.860899                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.860899                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.860899                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.860899                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       749399                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               62727                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               59952                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    13.178249                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.499983                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9995                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9995                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36329                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36329                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24118                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        24118                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60447                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60447                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60447                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60447                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9798                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9798                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5473                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5473                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15271                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15271                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    565152868                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    565152868                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    705764091                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    705764091                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1270916959                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1270916959                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1270916959                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1270916959                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    717311081                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    717311081                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    861132955                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    861132955                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1578444036                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1578444036                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.807922                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.807922                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954639                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954639                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860701                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.860701                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860701                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.860701                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129                       # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks          10051                       # number of writebacks
+system.cpu5.l1c.writebacks::total               10051                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36239                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36239                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        24308                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        24308                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60547                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60547                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60547                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60547                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9869                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9869                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5375                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5375                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15244                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15244                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    610804171                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    610804171                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    534872438                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    534872438                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1145676609                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1145676609                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1145676609                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1145676609                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    745114179                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    745114179                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    938602875                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    938602875                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1683717054                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1683717054                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808599                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808599                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952769                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952769                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.860899                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.860899                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.860899                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.860899                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                          100000                       # number of read accesses completed
-system.cpu6.num_writes                          55059                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22318                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             390.741535                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13451                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22720                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.592033                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99231                       # number of read accesses completed
+system.cpu6.num_writes                          55266                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22476                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             393.210816                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13488                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22863                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.589949                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      390.741535                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.763167                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.763167                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              338536                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             338536                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8731                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8731                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1150                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1150                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9881                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9881                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9881                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9881                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36733                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36733                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23795                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23795                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60528                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60528                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60528                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60528                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    609896687                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    609896687                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    716784676                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    716784676                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1326681363                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1326681363                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1326681363                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1326681363                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45464                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45464                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         24945                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        24945                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70409                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70409                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70409                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70409                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807958                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.807958                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953899                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.953899                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.859663                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.859663                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.859663                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.859663                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       822803                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      393.210816                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.767990                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.767990                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          387                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              339081                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             339081                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8703                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8703                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1207                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1207                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9910                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9910                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9910                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9910                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36605                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36605                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           24011                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          24011                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60616                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60616                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60616                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60616                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    653690176                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    653690176                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    554778070                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    554778070                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1208468246                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1208468246                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1208468246                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1208468246                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45308                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45308                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25218                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25218                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70526                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70526                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70526                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70526                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807915                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.807915                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.952137                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.952137                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859484                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859484                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859484                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859484                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       748048                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               62827                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               59929                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    13.096328                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.482237                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9777                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9777                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36733                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36733                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23795                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23795                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60528                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60528                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60528                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60528                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9837                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9837                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5532                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5532                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15369                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15369                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    573164687                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    573164687                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    692991676                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    692991676                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1266156363                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1266156363                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1266156363                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1266156363                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    718909036                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    718909036                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    867837123                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    867837123                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1586746159                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1586746159                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807958                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807958                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953899                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953899                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859663                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.859663                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859663                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.859663                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277                       # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks           9811                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9811                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36605                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36605                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24011                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        24011                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60616                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60616                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60616                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60616                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9828                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9828                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5436                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5436                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15264                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15264                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    617085176                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    617085176                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    530767070                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    530767070                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1147852246                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1147852246                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1147852246                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1147852246                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    743889866                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    743889866                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    938428736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    938428736                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1682318602                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1682318602                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807915                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807915                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.952137                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.952137                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859484                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859484                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859484                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859484                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99734                       # number of read accesses completed
-system.cpu7.num_writes                          54921                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22329                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             392.290074                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13499                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22713                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.594329                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99956                       # number of read accesses completed
+system.cpu7.num_writes                          55531                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22312                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             393.161929                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13691                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22714                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.602756                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      392.290074                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.766192                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.766192                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          384                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0          371                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              338596                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             338596                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8795                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8795                       # number of ReadReq hits
+system.cpu7.l1c.tags.occ_blocks::cpu7      393.161929                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.767894                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.767894                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              338939                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             338939                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8916                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8916                       # number of ReadReq hits
 system.cpu7.l1c.WriteReq_hits::cpu7              1165                       # number of WriteReq hits
 system.cpu7.l1c.WriteReq_hits::total             1165                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9960                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9960                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9960                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9960                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36684                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36684                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23790                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23790                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60474                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60474                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60474                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60474                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    611011013                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    611011013                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    715403706                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    715403706                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1326414719                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1326414719                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1326414719                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1326414719                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45479                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45479                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         24955                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        24955                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70434                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70434                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70434                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70434                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.806614                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.806614                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953316                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.953316                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.858591                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.858591                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.858591                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.858591                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       829723                       # number of cycles access was blocked
+system.cpu7.l1c.demand_hits::cpu7               10081                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total              10081                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7              10081                       # number of overall hits
+system.cpu7.l1c.overall_hits::total             10081                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36493                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36493                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23963                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23963                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60456                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60456                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60456                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60456                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    649044669                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    649044669                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    555516702                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    555516702                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1204561371                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1204561371                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1204561371                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1204561371                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45409                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45409                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25128                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25128                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70537                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70537                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70537                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70537                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803651                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.803651                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953637                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.953637                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.857082                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.857082                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.857082                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.857082                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       753584                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               63058                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               60106                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    13.158093                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.537584                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9746                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9746                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36684                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36684                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23790                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23790                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60474                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60474                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60474                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60474                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9918                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9918                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5421                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5421                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15339                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15339                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    574327013                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    574327013                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    691615706                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    691615706                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1265942719                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1265942719                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1265942719                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1265942719                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    726668427                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    726668427                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    847371643                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    847371643                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1574040070                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1574040070                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.806614                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.806614                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953316                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953316                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858591                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.858591                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858591                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.858591                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550                       # average overall mshr uncacheable latency
+system.cpu7.l1c.writebacks::writebacks           9825                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9825                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36493                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36493                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23963                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23963                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60456                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60456                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60456                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60456                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9946                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9946                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5477                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5477                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15423                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15423                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    612553669                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    612553669                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    531553702                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    531553702                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1144107371                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1144107371                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1144107371                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1144107371                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    750008205                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    750008205                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    931574803                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    931574803                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1681583008                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1681583008                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803651                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803651                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953637                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953637                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.857082                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.857082                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.857082                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.857082                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    14328                       # number of replacements
-system.l2c.tags.tagsinuse                  791.177993                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     163940                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    15120                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.842593                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13679                       # number of replacements
+system.l2c.tags.tagsinuse                  785.030982                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     164295                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14481                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.345556                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     732.189847                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.660754                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.418431                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.928491                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.181835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             7.391664                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             6.508374                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             7.134486                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             7.764111                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.715029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.007481                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.007245                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.007743                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.007218                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.006356                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.006967                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.007582                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.772635                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          792                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          650                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  2105170                       # Number of tag accesses
-system.l2c.tags.data_accesses                 2105170                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks        77576                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total           77576                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0                  276                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  259                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  279                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  261                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  303                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  269                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  291                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  289                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2227                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1751                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1771                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1804                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1773                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1863                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1769                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1750                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1757                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                14238                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0             10760                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1             10778                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2             10893                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3             11049                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4             10672                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5             10913                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6             11141                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7             10949                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total            87155                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0                    12511                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12549                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12697                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12822                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12535                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12682                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12891                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12706                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  101393                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12511                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12549                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12697                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12822                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12535                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12682                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12891                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12706                       # number of overall hits
-system.l2c.overall_hits::total                 101393                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0               2046                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2029                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2111                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2056                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2033                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               2090                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               2030                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               1987                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16382                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4599                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4725                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4817                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4668                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4596                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4594                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4511                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4557                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              37067                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0             771                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1             761                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2             769                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3             709                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu4             779                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu5             699                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu6             722                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7             759                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total           5969                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0                   5370                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5486                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5586                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5377                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5375                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5293                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5233                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5316                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 43036                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5370                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5486                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5586                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5377                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5375                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5293                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5233                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5316                       # number of overall misses
-system.l2c.overall_misses::total                43036                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0     72840477                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     70862981                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     74683475                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     72897976                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     72564980                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     68905302                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     71238981                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     72107979                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    576102151                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     293596847                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     301266861                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     306960376                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     297631356                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     293263365                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     292806382                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     287321715                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     290617373                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2363464275                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0     53018410                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1     52427412                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2     53340392                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3     48936413                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu4     53163418                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu5     48227901                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu6     50021405                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu7     52163904                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total    411299255                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0        346615257                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        353694273                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        360300768                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        346567769                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        346426783                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        341034283                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        337343120                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        342781277                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2774763530                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       346615257                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       353694273                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       360300768                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       346567769                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       346426783                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       341034283                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       337343120                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       342781277                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2774763530                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks        77576                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total        77576                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2322                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2288                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2390                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2317                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2336                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2359                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2321                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2276                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18609                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6350                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1              6496                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6621                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6441                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6459                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6363                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6261                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6314                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            51305                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0         11531                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1         11539                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2         11662                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3         11758                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu4         11451                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu5         11612                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu6         11863                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu7         11708                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total        93124                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17881                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                18035                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                18283                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                18199                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                17910                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17975                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                18124                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                18022                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              144429                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17881                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               18035                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               18283                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               18199                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               17910                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17975                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               18124                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               18022                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             144429                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.881137                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.886801                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.883264                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.887354                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.870291                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.885969                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.874623                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.873023                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.880327                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.724252                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.727371                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.727534                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.724732                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.711565                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.721986                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.720492                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.721729                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.722483                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0     0.066863                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1     0.065950                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2     0.065941                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3     0.060299                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4     0.068029                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu5     0.060196                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu6     0.060862                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7     0.064827                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.064097                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0            0.300319                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.304186                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.305530                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.295456                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.300112                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.294465                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.288733                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.294973                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.297973                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.300319                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.304186                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.305530                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.295456                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.300112                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.294465                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.288733                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.294973                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.297973                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 63761.952006                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 64546.602793                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 64472.160591                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 64500.674544                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 64453.741678                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 64451.494512                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 64431.188929                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 64464.574814                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 64481.052859                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 64475.405010                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 64546.602793                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 64472.160591                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 64500.674544                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 64453.741678                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 64451.494512                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 64431.188929                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 64464.574814                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 64481.052859                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 64475.405010                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             37689                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks     728.912576                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             7.109869                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             7.264593                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             7.067016                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             7.280147                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.468572                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             6.873708                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             6.969066                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             7.085434                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.711829                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006943                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.007094                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2            0.006901                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3            0.007110                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4            0.006317                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5            0.006713                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6            0.006806                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7            0.006919                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.766632                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          802                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          674                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  2100989                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2100989                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks        77660                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total           77660                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0                  265                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  275                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  255                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  290                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  283                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  292                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  297                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  302                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2259                       # number of UpgradeReq hits
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+system.l2c.overall_hits::cpu0                   12568                       # number of overall hits
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+system.l2c.overall_hits::total                 101011                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0               1935                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               2063                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::cpu3               2061                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               2025                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::cpu6               1973                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total             16225                       # number of UpgradeReq misses
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+system.l2c.ReadSharedReq_misses::cpu0             701                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu3             750                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu4             700                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu5             714                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu6             696                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu7             703                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total           5712                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0                   5418                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total                 42910                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0                  5418                       # number of overall misses
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+system.l2c.overall_misses::total                42910                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0     33570299                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     36327486                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     35657979                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     35008978                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     34589470                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     34691475                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     32410475                       # number of UpgradeReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::total    277722139                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     161829189                       # number of ReadExReq miss cycles
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+system.l2c.WritebackDirty_accesses::total        77660                       # number of WritebackDirty accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu6              6431                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6478                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            51480                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0         11485                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1         11578                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2         11589                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3         11564                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu4         11669                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu5         11496                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu6         11521                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu7         11539                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total        92441                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                17986                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                17915                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                18063                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                17917                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                18030                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                18041                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                17952                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                18017                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              143921                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               17986                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1               17915                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2               18063                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3               17917                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               18030                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               18041                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               17952                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               18017                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             143921                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.879545                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.882378                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.889944                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.876648                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.877383                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.875639                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.869163                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.871599                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.877786                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.725581                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.721635                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.717176                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.726901                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.723786                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.715202                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.725237                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.725224                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.722572                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0     0.061036                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1     0.064001                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2     0.061006                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3     0.064856                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu4     0.059988                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu5     0.062109                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu6     0.060411                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu7     0.060924                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.061791                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0            0.301234                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.296623                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.296186                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.299604                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.294176                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.299041                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.298574                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.299772                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.298150                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.301234                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.296623                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.296186                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.299604                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.294176                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.299041                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.298574                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.299772                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.298150                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 17348.991731                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 17609.057683                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 17292.909311                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 16986.403688                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 17081.219753                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 16873.285506                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 16427.002027                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 17300.476585                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17116.926903                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 34307.650837                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 33968.045703                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 33980.191686                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 33915.807709                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 34430.144440                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 33922.212989                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 34104.495497                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 34078.887709                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 69987.383578                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 38955.445921                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 38975.307678                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 38828.056262                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 38956.988636                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 39013.158183                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 38695.511585                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 38772.250746                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 38678.106462                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 38858.876719                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 38955.445921                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 38975.307678                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 38828.056262                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 38956.988636                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 39013.158183                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 38695.511585                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 38772.250746                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 38678.106462                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 38858.876719                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             15775                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     7229                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     2328                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      5.213584                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      6.776203                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6662                       # number of writebacks
-system.l2c.writebacks::total                     6662                       # number of writebacks
+system.l2c.writebacks::writebacks                6347                       # number of writebacks
+system.l2c.writebacks::total                     6347                       # number of writebacks
 system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu1               5                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              8                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                5                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                6                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                6                       # number of ReadExReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                3                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1                7                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                8                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5                8                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                9                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::total              45                       # number of ReadExReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2           12                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3            7                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu4           14                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu5            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu6            8                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu7            8                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           72                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  14                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  19                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  14                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                  14                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                  14                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                117                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                 16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 14                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 19                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                 14                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                 14                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                 14                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               117                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         1261                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         1261                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          2045                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2024                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2111                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2055                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          2032                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          2090                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          2030                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          1987                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        16374                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4592                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4720                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4810                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4661                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4593                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4590                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4505                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4551                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         37022                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0          762                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1          752                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2          757                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3          702                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu4          765                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu5          694                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu6          714                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu7          751                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total         5897                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5354                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5472                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5567                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5363                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5358                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5284                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              5219                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5302                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            42919                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5354                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5472                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5567                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5363                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5358                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5284                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             5219                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5302                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           42919                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0         9885                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1         9741                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2         9774                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3         9813                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu4         9945                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu5         9798                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu6         9837                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu7         9918                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        78711                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0         5567                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1         5462                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2         5416                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3         5447                       # number of WriteReq MSHR uncacheable
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+system.l2c.demand_mshr_miss_latency::cpu1    153118465                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    153714512                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    154904663                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    153299293                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    154148371                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    153787468                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    154302292                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1233700860                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    156425796                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    153118465                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    153714512                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    154904663                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    153299293                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    154148371                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    153787468                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    154302292                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1233700860                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    532537334                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    530034961                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    522091524                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    528677272                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    531067932                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    528334987                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    526505398                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    532738235                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   4231987643                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    302507401                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    304491446                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    306673088                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    296941482                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    299721877                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    297975047                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    302462757                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    303375300                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2414148398                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    835044735                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    834526407                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    828764612                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    825618754                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    830789809                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    826310034                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    828968155                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    836113535                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6646136041                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.880706                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.884615                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.883264                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.886923                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.869863                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.885969                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.874623                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.873023                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.879897                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.723150                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.726601                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.726476                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.723645                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.711101                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.721358                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.719534                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.720779                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.721606                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.066083                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.065170                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.064912                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.059704                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.066806                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.059766                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.060187                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.064144                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.063324                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.299424                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.303410                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.304491                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.294687                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.299162                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.293964                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.287961                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.294196                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.297163                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.299424                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.303410                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.304491                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.294687                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.299162                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.293964                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.287961                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.294196                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.297163                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 54556.724062                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 54556.724062                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.879091                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.882378                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.889944                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.876223                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.877383                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.875213                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.869163                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.871599                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.877624                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.725119                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.720530                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.715941                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.726428                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.723000                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.713980                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.724926                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.723835                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.721698                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060427                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.062878                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.060402                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.063992                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.058874                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.061413                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.059630                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.060577                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.061023                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.300678                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.295507                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.295355                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.298878                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.293178                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.298154                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.297961                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.299051                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.297344                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.300678                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.295507                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.295355                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.298878                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.293178                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.298154                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.297961                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.299051                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.297344                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 28828.827873                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 28828.827873                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests        127545                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       121489                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests        125196                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests       119242                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
 system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq               78710                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84594                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43645                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43644                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty         6662                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             1288                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            60944                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           50160                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             49324                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3261                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          5890                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       428122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 428122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1134381                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1134381                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            56843                       # Total snoops (count)
-system.membus.snoop_fanout::samples            246442                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               79046                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84668                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43599                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43596                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty         6347                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1243                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            60999                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             49250                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3150                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5631                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       377529                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 377529                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1090828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1090828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            56847                       # Total snoops (count)
+system.membus.snoop_fanout::samples            245688                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  246442    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  245688    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              246442                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           292771939                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              54.1                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          296967000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             54.9                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       667370                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       284034                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       336982                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          12889                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         5997                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         6892                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              78711                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            370868                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            5                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43646                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43643                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty        84238                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           20479                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29389                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29387                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           162232                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          162225                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       292173                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       122572                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122578                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122851                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122953                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122545                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       122770                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122967                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122678                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                981914                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1769628                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1794530                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1801428                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1802844                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1789097                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1796324                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1791880                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1784489                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14330220                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          335082                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           628739                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.148986                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.990092                       # Request fanout histogram
+system.membus.snoop_fanout::total              245688                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           290283631                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              54.2                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          245575000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             45.9                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       665524                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       283935                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       335837                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          12315                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         5744                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         6571                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              79051                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            371557                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43601                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43596                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty        84007                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105887                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29231                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29230                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           162413                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          162411                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       292528                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133547                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133251                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133734                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133419                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       133559                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133487                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133484                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       133586                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1068067                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1785416                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1780080                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1798067                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1787232                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1784031                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1801672                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1781660                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1785403                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14303561                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          335445                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           626448                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.148675                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.987271                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 176143     28.02%     28.02% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 257926     41.02%     69.04% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 134453     21.38%     90.42% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  47224      7.51%     97.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  11211      1.78%     99.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                   1632      0.26%     99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                    146      0.02%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 174709     27.89%     27.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 258191     41.22%     69.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 133874     21.37%     90.47% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  46929      7.49%     97.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  11007      1.76%     99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                   1601      0.26%     99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                    133      0.02%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::7                      4      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             628739                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          500695190                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             92.6                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         101141048                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         101214213                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         101195728                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         101296930                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         101179412                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         101203668                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         101388789                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            18.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         101354632                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            18.7                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total             626448                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          498178453                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             93.1                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         102533331                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         102040683                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            19.1                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         102532818                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         102294677                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            19.1                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         102527849                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         102329742                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            19.1                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         102510939                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         102349372                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            19.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index ffbbc56b2..36475e393 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1811 +1,1811 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000534                       # Number of seconds simulated
-sim_ticks                                   534039500                       # Number of ticks simulated
-final_tick                                  534039500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000530                       # Number of seconds simulated
+sim_ticks                                   530176500                       # Number of ticks simulated
+final_tick                                  530176500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                               46952087                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215976                       # Number of bytes of host memory used
-host_seconds                                    11.37                       # Real time elapsed on the host
+host_tick_rate                              118834220                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236308                       # Number of bytes of host memory used
+host_seconds                                     4.46                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0                 80135                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 83816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 79566                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 82290                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 82935                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 84320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 79631                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 84304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               656997                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       418368                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5512                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5388                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5320                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5503                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5449                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5363                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5499                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5488                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            461890                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  10898                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  10988                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  10833                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  10911                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  10989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  10862                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  10835                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  10972                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 87288                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            6537                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5512                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5388                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5320                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5503                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5449                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5363                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5499                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5488                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                50059                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                150054444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                156947192                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                148988979                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                154089726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                155297501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                157890943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                149110693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                157860982                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1230240460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         783402726                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                10321334                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                10089141                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                 9961810                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                10304481                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                10203365                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                10042328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                10296991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                10276393                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              864898570                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         783402726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               160375777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               167036333                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               158950789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               164394207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               165500867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               167933271                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               159407684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               168137376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2095139030                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0                 78184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 80178                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 79911                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 80308                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 82157                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 80611                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 79164                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 81441                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               641954                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       404160                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5485                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5400                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5418                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5526                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5422                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5458                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5386                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5538                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            447793                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  10774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  10815                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  10863                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  11071                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  10904                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  10870                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  10935                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  10881                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 87113                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6315                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5485                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5400                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5418                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5526                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5422                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5458                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5386                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5538                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49948                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                147467872                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                151228883                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                150725277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                151474085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                154961602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                152045592                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                149316313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                153611109                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1210830733                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         762312173                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                10345611                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                10185287                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                10219238                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                10422944                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                10226783                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                10294685                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                10158881                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                10445578                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              844611181                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         762312173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               157813483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               161414171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               160944516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               161897029                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               165188385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               162340277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               159475194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               164056687                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2055441914                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.num_reads                           98970                       # number of read accesses completed
-system.cpu0.num_writes                          54697                       # number of write accesses completed
-system.cpu0.l1c.tags.replacements               22262                       # number of replacements
-system.cpu0.l1c.tags.tagsinuse             392.444163                       # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs                 13142                       # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs               22657                       # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs                0.580041                       # Average number of references to valid blocks.
+system.cpu0.num_reads                           99175                       # number of read accesses completed
+system.cpu0.num_writes                          54789                       # number of write accesses completed
+system.cpu0.l1c.tags.replacements               22440                       # number of replacements
+system.cpu0.l1c.tags.tagsinuse             392.189512                       # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs                 13440                       # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs               22832                       # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs                0.588648                       # Average number of references to valid blocks.
 system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0      392.444163                       # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0       0.766493                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total      0.766493                       # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses              335259                       # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses             335259                       # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0               8424                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8424                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1108                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1108                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9532                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9532                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9532                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9532                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            36392                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           36392                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23768                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23768                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             60160                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            60160                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            60160                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           60160                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    598420373                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    598420373                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    705577272                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    705577272                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1303997645                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1303997645                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1303997645                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1303997645                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          44816                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         44816                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         24876                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        24876                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           69692                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          69692                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          69692                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         69692                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.812031                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.812031                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.955459                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.955459                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.863227                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.863227                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.863227                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.863227                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs       798798                       # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0      392.189512                       # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0       0.765995                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total      0.765995                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          392                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          373                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              338141                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             338141                       # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0               8693                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8693                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1204                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1204                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9897                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9897                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9897                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            36509                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           36509                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23927                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23927                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60436                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60436                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60436                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60436                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    645236912                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    645236912                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    543361201                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    543361201                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1188598113                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1188598113                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1188598113                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1188598113                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          45202                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         45202                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         25131                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        25131                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           70333                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          70333                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          70333                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         70333                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807686                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.807686                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952091                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.952091                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.859284                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.859284                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.859284                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.859284                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs       716464                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               61887                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               58624                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.907363                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.221343                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9766                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9766                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36392                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        36392                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23768                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23768                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        60160                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        60160                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        60160                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        60160                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9799                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9799                       # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5512                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5512                       # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15311                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15311                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    562029373                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    562029373                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    681810272                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    681810272                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1243839645                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1243839645                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1243839645                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1243839645                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    706647630                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    706647630                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    855364129                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    855364129                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1562011759                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1562011759                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.812031                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.812031                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.955459                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.955459                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.863227                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.863227                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.863227                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.863227                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891                       # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks           9950                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9950                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36509                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        36509                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23927                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23927                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60436                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60436                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60436                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60436                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9705                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9705                       # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5489                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5489                       # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15194                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15194                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    608727912                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    608727912                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    519435201                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    519435201                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1128163113                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1128163113                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1128163113                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1128163113                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    718425919                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    718425919                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    939004763                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    939004763                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1657430682                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1657430682                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807686                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807686                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952091                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952091                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.859284                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.859284                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928                       # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           98379                       # number of read accesses completed
-system.cpu1.num_writes                          54883                       # number of write accesses completed
-system.cpu1.l1c.tags.replacements               22236                       # number of replacements
-system.cpu1.l1c.tags.tagsinuse             391.015365                       # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs                 13378                       # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs               22622                       # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs                0.591371                       # Average number of references to valid blocks.
+system.cpu1.num_reads                           99705                       # number of read accesses completed
+system.cpu1.num_writes                          54823                       # number of write accesses completed
+system.cpu1.l1c.tags.replacements               22335                       # number of replacements
+system.cpu1.l1c.tags.tagsinuse             390.697643                       # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs                 13624                       # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs               22725                       # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs                0.599516                       # Average number of references to valid blocks.
 system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1      391.015365                       # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1       0.763702                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total      0.763702                       # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_blocks::cpu1      390.697643                       # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1       0.763081                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total      0.763081                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
 system.cpu1.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses              335372                       # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses             335372                       # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1               8546                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8546                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1143                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1143                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9689                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9689                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9689                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9689                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36240                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36240                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           23835                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          23835                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             60075                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            60075                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            60075                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           60075                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    593535449                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    593535449                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    712426271                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    712426271                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1305961720                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1305961720                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1305961720                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1305961720                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          44786                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         44786                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         24978                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        24978                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           69764                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          69764                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          69764                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         69764                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809181                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.809181                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954240                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.954240                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.861117                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.861117                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.861117                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.861117                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs       803378                       # number of cycles access was blocked
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              339221                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             339221                       # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1               8840                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8840                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1148                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9988                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9988                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9988                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9988                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36605                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36605                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23987                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23987                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60592                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60592                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60592                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60592                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    646842299                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    646842299                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    543658224                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    543658224                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1190500523                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1190500523                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1190500523                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1190500523                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          45445                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         45445                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         25135                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        25135                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           70580                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          70580                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          70580                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         70580                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805479                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.805479                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954327                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954327                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.858487                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.858487                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.858487                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.858487                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs       718948                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               62137                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               59028                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.929140                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.179779                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9779                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9779                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36240                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36240                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23835                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        23835                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        60075                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        60075                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        60075                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        60075                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9833                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9833                       # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5388                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5388                       # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15221                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15221                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    557295449                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    557295449                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    688592271                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    688592271                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1245887720                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1245887720                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1245887720                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1245887720                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    707451122                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    707451122                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    858171680                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    858171680                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1565622802                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1565622802                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809181                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809181                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954240                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954240                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.861117                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.861117                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.861117                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.861117                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761                       # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks           9932                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9932                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36605                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36605                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23987                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23987                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60592                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60592                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60592                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60592                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9715                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9715                       # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5400                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5400                       # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15115                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15115                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    610238299                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    610238299                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    519672224                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    519672224                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1129910523                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1129910523                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1129910523                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1129910523                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    721621903                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    721621903                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    954237303                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    954237303                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1675859206                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1675859206                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805479                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805479                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954327                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954327                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.858487                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.858487                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728                       # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99126                       # number of read accesses completed
-system.cpu2.num_writes                          55057                       # number of write accesses completed
-system.cpu2.l1c.tags.replacements               22416                       # number of replacements
-system.cpu2.l1c.tags.tagsinuse             392.045662                       # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs                 13448                       # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs               22823                       # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs                0.589230                       # Average number of references to valid blocks.
+system.cpu2.num_reads                           99117                       # number of read accesses completed
+system.cpu2.num_writes                          54908                       # number of write accesses completed
+system.cpu2.l1c.tags.replacements               22381                       # number of replacements
+system.cpu2.l1c.tags.tagsinuse             392.253516                       # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs                 13534                       # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs               22797                       # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs                0.593675                       # Average number of references to valid blocks.
 system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2      392.045662                       # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2       0.765714                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total      0.765714                       # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0          394                       # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses              337969                       # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses             337969                       # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2               8656                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8656                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1187                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1187                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9843                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9843                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9843                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9843                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            36613                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           36613                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23839                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23839                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             60452                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            60452                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            60452                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           60452                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    594021809                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    594021809                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    716005587                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    716005587                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1310027396                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1310027396                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1310027396                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1310027396                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          45269                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         45269                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         25026                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        25026                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           70295                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          70295                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          70295                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         70295                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.808787                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.808787                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.952569                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.952569                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.859976                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.859976                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.859976                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.859976                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs       801429                       # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2      392.253516                       # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2       0.766120                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total      0.766120                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          416                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          405                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              338010                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             338010                       # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2               8679                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8679                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1137                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9816                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9816                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9816                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9816                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36478                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36478                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           24024                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          24024                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60502                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60502                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60502                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60502                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    647459345                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    647459345                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    543523925                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    543523925                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1190983270                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1190983270                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1190983270                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1190983270                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          45157                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         45157                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         25161                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        25161                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           70318                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          70318                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          70318                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         70318                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807804                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.807804                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954811                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.954811                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.860406                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.860406                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.860406                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.860406                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs       722959                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               62324                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               59032                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.859075                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.246900                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9798                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9798                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36613                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        36613                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23839                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23839                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        60452                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        60452                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        60452                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        60452                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9743                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9743                       # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5322                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5322                       # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15065                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15065                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    557410809                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    557410809                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    692167587                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    692167587                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1249578396                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1249578396                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1249578396                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1249578396                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    702012144                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    702012144                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    835893746                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    835893746                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1537905890                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1537905890                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.808787                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.808787                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.952569                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.952569                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.859976                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.859976                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.859976                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.859976                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333                       # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks           9774                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9774                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36478                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36478                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24024                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        24024                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60502                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60502                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60502                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60502                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9767                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9767                       # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5419                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5419                       # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15186                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15186                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    610981345                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    610981345                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    519499925                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    519499925                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1130481270                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1130481270                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1130481270                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1130481270                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    722748371                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    722748371                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    934057840                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    934057840                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1656806211                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1656806211                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807804                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807804                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954811                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954811                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.860406                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.860406                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286                       # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           99267                       # number of read accesses completed
-system.cpu3.num_writes                          54937                       # number of write accesses completed
-system.cpu3.l1c.tags.replacements               22308                       # number of replacements
-system.cpu3.l1c.tags.tagsinuse             393.396608                       # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs                 13642                       # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs               22699                       # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs                0.600996                       # Average number of references to valid blocks.
+system.cpu3.num_reads                          100000                       # number of read accesses completed
+system.cpu3.num_writes                          55255                       # number of write accesses completed
+system.cpu3.l1c.tags.replacements               22194                       # number of replacements
+system.cpu3.l1c.tags.tagsinuse             391.395366                       # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs                 13678                       # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs               22603                       # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs                0.605141                       # Average number of references to valid blocks.
 system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3      393.396608                       # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3       0.768353                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total      0.768353                       # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0          377                       # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses              336965                       # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses             336965                       # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3               8834                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8834                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1126                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1126                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9960                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9960                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9960                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9960                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            36404                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           36404                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23769                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23769                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             60173                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            60173                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            60173                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           60173                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    595557078                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    595557078                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    707954928                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    707954928                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1303512006                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1303512006                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1303512006                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1303512006                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          45238                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         45238                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         24895                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        24895                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           70133                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          70133                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          70133                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         70133                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.804722                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.804722                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954770                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.954770                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.857984                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.857984                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.857984                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.857984                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs       796210                       # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3      391.395366                       # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3       0.764444                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total      0.764444                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          403                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              337339                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             337339                       # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3               8923                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8923                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1132                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3               10055                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total              10055                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3              10055                       # number of overall hits
+system.cpu3.l1c.overall_hits::total             10055                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            36521                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           36521                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23639                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23639                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60160                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60160                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60160                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60160                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    641069966                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    641069966                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    531956623                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    531956623                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1173026589                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1173026589                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1173026589                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1173026589                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          45444                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         45444                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         24771                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        24771                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           70215                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          70215                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          70215                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         70215                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.803648                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.803648                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954301                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.954301                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.856797                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.856797                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.856797                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.856797                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs       718925                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               61792                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.885325                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.224121                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9835                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9835                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36404                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        36404                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23769                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23769                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        60173                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        60173                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        60173                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        60173                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9778                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9778                       # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5503                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5503                       # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15281                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15281                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    559153078                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    559153078                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    684188928                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    684188928                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1243342006                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1243342006                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1243342006                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1243342006                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    702217176                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    702217176                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    867552200                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    867552200                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1569769376                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1569769376                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.804722                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.804722                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954770                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954770                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.857984                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.857984                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.857984                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.857984                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943                       # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks           9851                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9851                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36521                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        36521                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23639                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23639                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60160                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60160                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60160                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60160                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9973                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9973                       # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5527                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5527                       # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15500                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15500                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    604549966                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    604549966                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    508318623                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    508318623                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1112868589                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1112868589                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1112868589                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1112868589                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    738348758                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    738348758                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    962176807                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    962176807                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1700525565                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1700525565                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.803648                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.803648                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954301                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954301                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.856797                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.856797                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774                       # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                           98613                       # number of read accesses completed
-system.cpu4.num_writes                          54610                       # number of write accesses completed
-system.cpu4.l1c.tags.replacements               21998                       # number of replacements
-system.cpu4.l1c.tags.tagsinuse             392.447255                       # Cycle average of tags in use
+system.cpu4.num_reads                           98958                       # number of read accesses completed
+system.cpu4.num_writes                          54718                       # number of write accesses completed
+system.cpu4.l1c.tags.replacements               22445                       # number of replacements
+system.cpu4.l1c.tags.tagsinuse             392.205168                       # Cycle average of tags in use
 system.cpu4.l1c.tags.total_refs                 13326                       # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs               22393                       # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs                0.595097                       # Average number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs               22839                       # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs                0.583476                       # Average number of references to valid blocks.
 system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4      392.447255                       # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4       0.766499                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total      0.766499                       # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0          385                       # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses              335144                       # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses             335144                       # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4               8557                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8557                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1170                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1170                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9727                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9727                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9727                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9727                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36223                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36223                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23758                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23758                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             59981                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            59981                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            59981                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           59981                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    587952444                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    587952444                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    716203349                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    716203349                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1304155793                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1304155793                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1304155793                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1304155793                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          44780                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         44780                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24928                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24928                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           69708                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          69708                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          69708                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         69708                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.808910                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.808910                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953065                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.953065                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.860461                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.860461                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.860461                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.860461                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs       805297                       # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4      392.205168                       # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4       0.766026                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total      0.766026                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              336585                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             336585                       # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4               8551                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8551                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1195                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1195                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                9746                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               9746                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               9746                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              9746                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            36430                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           36430                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23820                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23820                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60250                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60250                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60250                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60250                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    646410865                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    646410865                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    541537295                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    541537295                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1187948160                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1187948160                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1187948160                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1187948160                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          44981                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         44981                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         25015                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        25015                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           69996                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          69996                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          69996                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         69996                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.809898                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.809898                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952229                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.952229                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.860763                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.860763                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.860763                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.860763                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs       719943                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               61957                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               58800                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.997676                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.243929                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9749                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9749                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36223                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36223                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23758                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23758                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        59981                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        59981                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        59981                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        59981                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9847                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9847                       # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5452                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5452                       # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15299                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15299                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    551729444                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    551729444                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    692447349                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    692447349                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1244176793                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1244176793                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1244176793                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1244176793                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    708336585                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    708336585                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    860694197                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    860694197                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1569030782                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1569030782                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.808910                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.808910                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953065                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953065                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860461                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.860461                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860461                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.860461                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623                       # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks           9851                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9851                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36430                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        36430                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23820                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23820                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60250                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60250                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60250                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60250                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9773                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9773                       # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5424                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5424                       # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15197                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15197                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    609980865                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    609980865                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    517717295                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    517717295                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1127698160                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1127698160                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1127698160                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1127698160                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    724329762                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    724329762                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    945564873                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    945564873                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1669894635                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1669894635                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.809898                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.809898                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952229                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952229                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.860763                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.860763                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614                       # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           99530                       # number of read accesses completed
-system.cpu5.num_writes                          55068                       # number of write accesses completed
-system.cpu5.l1c.tags.replacements               22260                       # number of replacements
-system.cpu5.l1c.tags.tagsinuse             393.692529                       # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs                 13670                       # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs               22641                       # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs                0.603772                       # Average number of references to valid blocks.
+system.cpu5.num_reads                           99011                       # number of read accesses completed
+system.cpu5.num_writes                          55007                       # number of write accesses completed
+system.cpu5.l1c.tags.replacements               22453                       # number of replacements
+system.cpu5.l1c.tags.tagsinuse             391.576438                       # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs                 13255                       # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs               22854                       # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs                0.579986                       # Average number of references to valid blocks.
 system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5      393.692529                       # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5       0.768931                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total      0.768931                       # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024          381                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024     0.744141                       # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses              337364                       # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses             337364                       # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5               8908                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8908                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1154                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1154                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5               10062                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total              10062                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5              10062                       # number of overall hits
-system.cpu5.l1c.overall_hits::total             10062                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36264                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36264                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           23895                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          23895                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             60159                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            60159                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            60159                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           60159                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    595565994                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    595565994                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    715910266                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    715910266                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1311476260                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1311476260                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1311476260                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1311476260                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          45172                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         45172                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         25049                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        25049                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           70221                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          70221                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          70221                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         70221                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.802798                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.802798                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.953930                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.953930                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.856710                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.856710                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.856710                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.856710                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs       800309                       # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5      391.576438                       # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5       0.764798                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total      0.764798                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              336606                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             336606                       # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5               8524                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8524                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1134                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1134                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9658                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9658                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9658                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9658                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36435                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36435                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23892                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23892                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60327                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60327                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60327                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60327                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    644721410                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    644721410                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    540612961                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    540612961                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1185334371                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1185334371                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1185334371                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1185334371                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          44959                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         44959                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         25026                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        25026                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           69985                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          69985                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          69985                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         69985                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.810405                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.810405                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954687                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.954687                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.861999                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.861999                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.861999                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.861999                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs       717184                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               61932                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               58708                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.922383                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.216120                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9774                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9774                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36264                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36264                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23895                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        23895                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        60159                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        60159                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        60159                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        60159                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9698                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9698                       # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5363                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5363                       # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15061                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15061                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    559302994                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    559302994                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    692016266                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    692016266                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1251319260                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1251319260                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1251319260                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1251319260                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    697234186                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    697234186                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    847695253                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    847695253                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1544929439                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1544929439                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.802798                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.802798                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.953930                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.953930                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.856710                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.856710                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.856710                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.856710                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811                       # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks           9910                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9910                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36435                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36435                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23892                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23892                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60327                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60327                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60327                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60327                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9763                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9763                       # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5458                       # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15221                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15221                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    608288410                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    608288410                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    516720961                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    516720961                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1125009371                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1125009371                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1125009371                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1125009371                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    723860386                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    723860386                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    946272316                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    946272316                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1670132702                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1670132702                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.810405                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.810405                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954687                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954687                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.861999                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.861999                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928                       # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                          100001                       # number of read accesses completed
-system.cpu6.num_writes                          54955                       # number of write accesses completed
-system.cpu6.l1c.tags.replacements               22371                       # number of replacements
-system.cpu6.l1c.tags.tagsinuse             392.789220                       # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs                 13659                       # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs               22773                       # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs                0.599789                       # Average number of references to valid blocks.
+system.cpu6.num_reads                           99860                       # number of read accesses completed
+system.cpu6.num_writes                          55212                       # number of write accesses completed
+system.cpu6.l1c.tags.replacements               22379                       # number of replacements
+system.cpu6.l1c.tags.tagsinuse             392.641405                       # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs                 13476                       # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs               22769                       # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs                0.591857                       # Average number of references to valid blocks.
 system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6      392.789220                       # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6       0.767166                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total      0.767166                       # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0          393                       # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses              338676                       # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses             338676                       # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6               8791                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8791                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1193                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1193                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9984                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9984                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9984                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9984                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36779                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36779                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           23715                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          23715                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             60494                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            60494                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            60494                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           60494                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    595549144                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    595549144                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    708070907                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    708070907                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1303620051                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1303620051                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1303620051                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1303620051                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          45570                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         45570                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         24908                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        24908                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           70478                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          70478                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          70478                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         70478                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.807088                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.807088                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.952104                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.952104                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.858339                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.858339                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.858339                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.858339                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs       794028                       # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6      392.641405                       # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6       0.766878                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total      0.766878                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              338111                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             338111                       # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6               8761                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8761                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1100                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1100                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9861                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9861                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9861                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9861                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36533                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36533                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23935                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23935                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60468                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60468                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60468                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60468                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    641137331                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    641137331                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    545446790                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    545446790                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1186584121                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1186584121                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1186584121                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1186584121                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45294                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45294                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         25035                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        25035                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           70329                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          70329                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          70329                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         70329                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806575                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.806575                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956062                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.956062                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.859788                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.859788                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.859788                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.859788                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs       722832                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               62044                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               59177                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.797821                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.214746                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9773                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9773                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36779                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36779                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23715                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        23715                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        60494                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        60494                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        60494                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        60494                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9743                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9743                       # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5502                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5502                       # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15245                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15245                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    558770144                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    558770144                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    684356907                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    684356907                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1243127051                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1243127051                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1243127051                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1243127051                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    702205139                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    702205139                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    875087157                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    875087157                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1577292296                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1577292296                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.807088                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.807088                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.952104                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.952104                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858339                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.858339                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858339                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.858339                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287                       # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks           9900                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9900                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36533                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36533                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23935                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23935                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60468                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60468                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60468                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60468                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9853                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9853                       # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5386                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5386                       # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15239                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15239                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    604606331                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    604606331                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    521511790                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    521511790                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1126118121                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1126118121                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1126118121                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1126118121                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    730958843                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    730958843                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    936459347                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    936459347                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1667418190                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1667418190                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806575                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806575                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956062                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956062                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.859788                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.859788                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036                       # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           99732                       # number of read accesses completed
-system.cpu7.num_writes                          55186                       # number of write accesses completed
-system.cpu7.l1c.tags.replacements               22105                       # number of replacements
-system.cpu7.l1c.tags.tagsinuse             391.370136                       # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs                 13595                       # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs               22490                       # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs                0.604491                       # Average number of references to valid blocks.
+system.cpu7.num_reads                           99316                       # number of read accesses completed
+system.cpu7.num_writes                          55530                       # number of write accesses completed
+system.cpu7.l1c.tags.replacements               22262                       # number of replacements
+system.cpu7.l1c.tags.tagsinuse             392.242621                       # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs                 13656                       # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs               22650                       # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs                0.602914                       # Average number of references to valid blocks.
 system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7      391.370136                       # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7       0.764395                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total      0.764395                       # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024          385                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_blocks::cpu7      392.242621                       # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7       0.766099                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total      0.766099                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
 system.cpu7.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024     0.751953                       # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses              337196                       # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses             337196                       # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7               8779                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8779                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7              1155                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total             1155                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9934                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9934                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9934                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9934                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            36327                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           36327                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23913                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23913                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             60240                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            60240                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            60240                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           60240                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    591115609                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    591115609                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    714870765                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    714870765                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1305986374                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1305986374                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1305986374                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1305986374                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          45106                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         45106                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         25068                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        25068                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           70174                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          70174                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          70174                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         70174                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.805370                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.805370                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953925                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.953925                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.858438                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.858438                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.858438                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.858438                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs       800916                       # number of cycles access was blocked
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              338652                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             338652                       # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7               8912                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8912                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1186                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1186                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7               10098                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total              10098                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7              10098                       # number of overall hits
+system.cpu7.l1c.overall_hits::total             10098                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36380                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36380                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23998                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23998                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60378                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60378                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60378                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60378                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    644409565                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    644409565                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    538142857                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    538142857                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1182552422                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1182552422                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1182552422                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1182552422                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45292                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45292                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         25184                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        25184                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           70476                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          70476                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          70476                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         70476                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803232                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.803232                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.952907                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.952907                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.856717                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.856717                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.856717                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.856717                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs       716334                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               62109                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.895329                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.180065                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9688                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9688                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36327                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        36327                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23913                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23913                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        60240                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        60240                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        60240                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        60240                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9808                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9808                       # number of ReadReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5490                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5490                       # number of WriteReq MSHR uncacheable
-system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15298                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15298                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    554789609                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    554789609                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    690958765                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    690958765                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1245748374                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1245748374                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1245748374                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1245748374                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    704741576                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    704741576                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    868948151                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    868948151                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1573689727                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1573689727                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.805370                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.805370                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953925                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953925                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858438                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.858438                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858438                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.858438                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639                       # average overall mshr uncacheable latency
+system.cpu7.l1c.writebacks::writebacks           9846                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9846                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36380                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36380                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23998                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23998                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60378                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60378                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60378                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60378                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9762                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9762                       # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5539                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5539                       # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15301                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15301                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    608029565                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    608029565                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    514144857                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    514144857                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1122174422                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1122174422                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1122174422                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1122174422                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    722808914                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    722808914                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    961004780                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    961004780                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1683813694                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1683813694                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803232                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803232                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.952907                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.952907                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.856717                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.856717                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066                       # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    13995                       # number of replacements
-system.l2c.tags.tagsinuse                  787.283340                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     163090                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                    14802                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    11.018106                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    13767                       # number of replacements
+system.l2c.tags.tagsinuse                  787.442113                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     164717                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                    14568                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.306768                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     729.204744                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0             7.276243                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1             7.685702                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2             7.303189                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3             7.305571                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4             6.947966                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5             7.333904                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6             7.314281                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7             6.911739                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.712114                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0            0.007106                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1            0.007506                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2            0.007132                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3            0.007134                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu4            0.006785                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu5            0.007162                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu6            0.007143                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu7            0.006750                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.768831                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024          807                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          673                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.788086                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  2092027                       # Number of tag accesses
-system.l2c.tags.data_accesses                 2092027                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks        76994                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total           76994                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0                  283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  283                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  290                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  275                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  271                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  268                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  273                       # number of UpgradeReq hits
+system.l2c.tags.occ_blocks::writebacks     730.095360                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0             6.568517                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1             7.047502                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2             7.052359                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3             7.453742                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4             6.826765                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5             7.175771                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6             7.149899                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7             8.072198                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.712984                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0            0.006415                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1            0.006882                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu3            0.007279                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu7            0.007883                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.768986                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          661                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          140                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.782227                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  2101238                       # Number of tag accesses
+system.l2c.tags.data_accesses                 2101238                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks        77585                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total           77585                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0                  280                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  286                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  296                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  265                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  264                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  299                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  295                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu7                  273                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2216                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1696                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1826                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1766                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  1793                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1691                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1701                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1693                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1794                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                13960                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0             10787                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1             10737                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2             10799                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3             10853                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4             10789                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5             10747                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6             10936                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7             10812                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total            86460                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0                    12483                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12563                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12565                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12646                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12480                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12448                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12629                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12606                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  100420                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12483                       # number of overall hits
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-system.l2c.overall_hits::cpu2                   12565                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12646                       # number of overall hits
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-system.l2c.overall_hits::cpu5                   12448                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12629                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12606                       # number of overall hits
-system.l2c.overall_hits::total                 100420                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0               2004                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               2095                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               2038                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2061                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               2078                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               2100                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               2074                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               2069                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             16519                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4524                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4568                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4664                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4580                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4684                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4609                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4587                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4667                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              36883                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0             734                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1             790                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2             729                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3             742                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu4             716                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu5             769                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu6             725                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7             744                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total           5949                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0                   5258                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5358                       # number of demand (read+write) misses
+system.l2c.UpgradeReq_hits::total                2258                       # number of UpgradeReq hits
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+system.l2c.ReadSharedReq_hits::total            86787                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::total                  101046                       # number of demand (read+write) hits
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+system.l2c.overall_hits::total                 101046                       # number of overall hits
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+system.l2c.UpgradeReq_misses::cpu3               2014                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::cpu5               1987                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::cpu7               2019                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             16296                       # number of UpgradeReq misses
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+system.l2c.ReadExReq_misses::total              36984                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0             715                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1             735                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu3             731                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu4             726                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::cpu6             671                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total           5780                       # number of ReadSharedReq misses
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 system.l2c.demand_misses::cpu2                   5393                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5322                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5400                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5378                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5312                       # number of demand (read+write) misses
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-system.l2c.demand_misses::total                 42832                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5258                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5358                       # number of overall misses
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 system.l2c.overall_misses::cpu2                  5393                       # number of overall misses
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-system.l2c.overall_misses::total                42832                       # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::cpu1     71351474                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     71595476                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     70154979                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     71820479                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     71543984                       # number of UpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu7     74781299                       # number of UpgradeReq miss cycles
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-system.l2c.demand_miss_latency::cpu3        336285098                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu0       332201277                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::cpu3       336285098                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total     2703394563                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks        76994                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total        76994                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2287                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu3             2336                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu7             2342                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu0        0.876257                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.880992                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.875430                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.882277                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.884632                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.886824                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.883681                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.883433                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.881719                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.727331                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.714420                       # miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu3         0.718657                       # miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu6         0.730414                       # miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0     0.063710                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu2     0.063237                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3     0.063993                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu4     0.062234                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu5     0.066777                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu6     0.062173                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu7     0.064382                       # miss rate for ReadSharedReq accesses
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-system.l2c.demand_miss_rate::total           0.298998                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.296376                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.298979                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.300312                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.296193                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.302013                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.301694                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.296082                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.300327                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.298998                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 34087.565868                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 34057.982816                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 35130.263003                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 34039.291121                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 34562.309432                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 34068.563810                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 34543.625362                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 36143.692122                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 34578.524850                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 62346.677498                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 62366.215193                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 62292.319468                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 62368.274236                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 62437.420581                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 62472.091777                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 62298.752780                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 62298.127919                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 62359.997967                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68317.313351                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1 67416.955696                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2 67918.938272                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68245.824798                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu4 67426.558659                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu5 66964.131339                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68142.623448                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68063.053763                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 67804.800471                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 63180.159186                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 63110.911907                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 63052.898943                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 63187.729801                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 63098.943333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 63114.408330                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 63096.344315                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 63090.791905                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 63116.234661                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 63180.159186                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 63110.911907                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 63052.898943                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 63187.729801                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 63098.943333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 63114.408330                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 63096.344315                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 63090.791905                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 63116.234661                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             33757                       # number of cycles access was blocked
+system.l2c.overall_misses::cpu3                  5272                       # number of overall misses
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+system.l2c.overall_misses::total                42764                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0     32787478                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     32272475                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     34405982                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     32097495                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     34646656                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     31653981                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     32901471                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu7     32271475                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    263037013                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     151347885                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1     149012881                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2     150333871                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3     147794053                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu4     149925888                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu5     151442380                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu6     154217889                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu7     149568871                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1203643718                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0     49081904                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1     50341908                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2     51226892                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3     50079413                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu4     49691401                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu5     48946419                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu6     46272414                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu7     51820900                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total    397461251                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0        200429789                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1        199354789                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2        201560763                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3        197873466                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu4        199617289                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu5        200388799                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu6        200490303                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu7        201389771                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      1601104969                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0       200429789                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1       199354789                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2       201560763                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3       197873466                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu4       199617289                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu5       200388799                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu6       200490303                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu7       201389771                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     1601104969                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks        77585                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total        77585                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0             2308                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1             2322                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2             2410                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3             2279                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2336                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2286                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2321                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             2292                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           18554                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              6429                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1              6475                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2              6394                       # number of ReadExReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu4              6348                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              6435                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              6544                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6328                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            51243                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0         11560                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1         11565                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2         11634                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3         11590                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu4         11509                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu5         11753                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu6         11624                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu7         11332                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total        92567                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                17989                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                18040                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                18028                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                17880                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                17857                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                18188                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                18168                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                17660                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              143810                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               17989                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1               18040                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu3               17880                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               17857                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               18188                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               18168                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               17660                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             143810                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.878683                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.876830                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.877178                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.883721                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.886986                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.869204                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.872900                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.880890                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.878301                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.727018                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.709189                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.728026                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.721940                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.717864                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.720901                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.721883                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.727244                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.721738                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0     0.061851                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1     0.063554                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2     0.063435                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3     0.063072                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu4     0.063081                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu5     0.060836                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu6     0.057725                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu7     0.066096                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.062441                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0            0.299572                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.295288                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.299146                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.294855                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.295850                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.294370                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.296951                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.303001                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.297365                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.299572                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.295288                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.299146                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.294855                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.295850                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.294370                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.296951                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.303001                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.297365                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 16167.395464                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 15850.920923                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 16275.298959                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 15937.187190                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 16721.359073                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 15930.539004                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 16239.620434                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 15983.890540                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16141.201092                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 32380.805520                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 32450.540287                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 32295.138776                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 32546.587316                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 32900.129032                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 32645.479629                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 32645.615792                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 32500.841156                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 32544.984804                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68646.019580                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68492.391837                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69413.132791                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68508.088919                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68445.455923                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68456.530070                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68960.378539                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69186.782377                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 68764.922318                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 37440.486601                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 37440.486601                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             15217                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                     6432                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                     2217                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      5.248290                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs      6.863780                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                6537                       # number of writebacks
-system.l2c.writebacks::total                     6537                       # number of writebacks
-system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              2                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
+system.l2c.writebacks::writebacks                6315                       # number of writebacks
+system.l2c.writebacks::total                     6315                       # number of writebacks
+system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
 system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2                2                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5               10                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                7                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              39                       # number of ReadExReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                5                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3                5                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4                2                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7                8                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              38                       # number of ReadExReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu0           13                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1            7                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2            5                       # number of ReadSharedReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu3            6                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu4           14                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu5           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu6            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu7           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           75                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  17                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                   9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  18                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  21                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                  16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                  15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                114                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 17                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                  9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 18                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                 21                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                 16                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                 15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               114                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         1240                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         1240                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          2003                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          2095                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          2038                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2061                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          2078                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          2099                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          2074                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          2069                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        16517                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4519                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4564                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4662                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4577                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4680                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4599                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4580                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4663                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         36844                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0          730                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1          777                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2          722                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3          736                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu4          702                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu5          758                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu6          716                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu7          733                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total         5874                       # number of ReadSharedReq MSHR misses
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-system.l2c.demand_mshr_misses::cpu4              5382                       # number of demand (read+write) MSHR misses
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-system.l2c.overall_mshr_misses::total           42718                       # number of overall MSHR misses
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-system.l2c.overall_mshr_uncacheable_misses::total       121771                       # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu3    106934463                       # number of UpgradeReq MSHR miss cycles
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-system.l2c.UpgradeReq_mshr_miss_latency::total    856095511                       # number of UpgradeReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::total    341873266                       # number of ReadSharedReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu4    286276796                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total   2272275073                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    503232104                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    504891308                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    500756647                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    501380612                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    505534787                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    497694775                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    500159589                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    503166776                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   4016816598                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    292229228                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    286836409                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    283709721                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    292753904                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    289394212                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    284248382                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    293152393                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    291492896                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2313817145                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu1    791727717                       # number of overall MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu3    794134516                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    794928999                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    781943157                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    793311982                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    794659672                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6330633743                       # number of overall MSHR uncacheable cycles
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+system.l2c.UpgradeReq_mshr_misses::cpu3          2013                       # number of UpgradeReq MSHR misses
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+system.l2c.ReadReq_mshr_uncacheable::cpu6         9852                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu7         9762                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        78309                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0         5486                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1         5400                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2         5419                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3         5526                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu4         5423                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu6         5386                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu7         5538                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        43636                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0        15191                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1        15115                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2        15186                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3        15498                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu4        15196                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu5        15221                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu6        15238                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu7        15300                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       121945                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     39014213                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     39232059                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     40780597                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     38858267                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     39920741                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     38246941                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     38960747                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     38849596                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    313863161                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    104350937                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    102876549                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    103582540                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    102275935                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    104240403                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    104871121                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    106828418                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    103332582                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total    832358485                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     41502671                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     42773140                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     43592644                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     42525173                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     42051842                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     41416678                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     39402449                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     44058192                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total    337322789                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    145853608                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    145649689                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    147175184                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    144801108                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    146292245                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    146287799                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    146230867                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    147390774                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1169681274                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    145853608                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    145649689                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    147175184                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    144801108                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    146292245                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    146287799                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    146230867                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    147390774                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1169681274                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    503077334                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    503572362                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    506294012                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    516868052                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    506181413                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    506175452                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    511232158                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    505608163                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   4059008946                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    292251287                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    290147025                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    292888717                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    297220505                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    290868538                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    292450481                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    288970880                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    297704385                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2342501818                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    795328621                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    793719387                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    799182729                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    814088557                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    797049951                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    798625933                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    800203038                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    803312548                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   6401510764                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.875820                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.880992                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.875430                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.882277                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.884632                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.886402                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.883681                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.883433                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.881612                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.726527                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.713794                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.725039                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.718186                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.734118                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.728843                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.729299                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.721715                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.724662                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.063363                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.067407                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.062630                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.063476                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.061017                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.065821                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.061401                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.063430                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.063565                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.295868                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.298030                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.299811                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.295692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.301007                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.300516                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.295190                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.299495                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.298202                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.295868                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.298030                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.299811                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.295692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.301007                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.300516                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.295190                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.299495                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.298202                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 53192.449857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 53192.449857                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.878683                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.876830                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.877178                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.883282                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.886558                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.869204                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.872900                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.880454                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.878139                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.726085                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.708571                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.727244                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.721145                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717549                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720280                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.721271                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.725980                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.720996                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060727                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.062949                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.063005                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062554                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.062125                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.059985                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.057467                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.065743                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.061804                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.298516                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.294678                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.298591                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.294239                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.295122                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.293600                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.296565                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.302322                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.296690                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.298516                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.294678                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.298591                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.294239                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.295122                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.293600                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.296565                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.302322                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.296690                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               78245                       # Transaction distribution
-system.membus.trans_dist::ReadResp              84100                       # Transaction distribution
-system.membus.trans_dist::WriteReq              43522                       # Transaction distribution
-system.membus.trans_dist::WriteResp             43520                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty         6537                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             1268                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            61107                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           50201                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             48942                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3181                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          5862                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       426485                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 426485                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1118817                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1118817                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            56662                       # Total snoops (count)
-system.membus.snoop_fanout::samples            253744                       # Request fanout histogram
+system.membus.trans_dist::ReadReq               78306                       # Transaction distribution
+system.membus.trans_dist::ReadResp              84006                       # Transaction distribution
+system.membus.trans_dist::WriteReq              43633                       # Transaction distribution
+system.membus.trans_dist::WriteResp             43633                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty         6315                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             1254                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            60980                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             48711                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3097                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          5709                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       375644                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 375644                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1089674                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1089674                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            56426                       # Total snoops (count)
+system.membus.snoop_fanout::samples            252331                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  253744    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  252331    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              253744                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           292620525                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization              54.8                       # Layer utilization (%)
-system.membus.respLayer0.occupancy          295409000                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization             55.3                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests       663684                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       282033                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       335738                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          12570                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         5835                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         6735                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              78248                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            369469                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate            4                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             43523                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            43520                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty        83531                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           20342                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           29636                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          29633                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           160854                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          160848                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       291239                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       121995                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122071                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122139                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122334                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122013                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       121723                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122513                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122322                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                977110                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1766349                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1778610                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1781270                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1785072                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1775296                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1771667                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1779976                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1778751                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               14216991                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          333737                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           624990                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            1.150519                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.991140                       # Request fanout histogram
+system.membus.snoop_fanout::total              252331                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           290210873                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization              54.7                       # Layer utilization (%)
+system.membus.respLayer0.occupancy          244257000                       # Layer occupancy (ticks)
+system.membus.respLayer0.utilization             46.1                       # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests       663692                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       283641                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       333885                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          12353                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         5692                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops         6661                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              78309                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            370176                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             43636                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            43632                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty        83900                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105566                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           29367                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          29367                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           161854                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          161852                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       291888                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133128                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133137                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133276                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133136                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       132901                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133285                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133385                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       132788                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1065036                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1790740                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1793737                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1783183                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1779785                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1777562                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1801715                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1799686                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1764480                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               14290888                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          334512                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           624442                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            1.148246                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.987708                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 174852     27.98%     27.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 256379     41.02%     69.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                 133497     21.36%     90.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                  47307      7.57%     97.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4                  11157      1.79%     99.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5                   1650      0.26%     99.98% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6                    145      0.02%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7                      3      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 174331     27.92%     27.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 257461     41.23%     69.15% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                 132941     21.29%     90.44% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                  47060      7.54%     97.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4                  10899      1.75%     99.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5                   1610      0.26%     99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6                    136      0.02%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7                      4      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             624990                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          497290718                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization             93.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         100872915                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization            18.9                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         100601006                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization            18.8                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         101141480                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization            18.9                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         100780789                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization            18.9                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy         100568051                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization            18.8                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy         100691951                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization            18.9                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy         101210192                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization            19.0                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy         100872512                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization            18.9                       # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total             624442                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          496537925                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization             93.7                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy         101982318                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy         102105458                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization            19.3                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy         101942894                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         101777352                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy         101724075                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy         101820787                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization            19.2                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy         102063169                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization            19.3                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy         101980781                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization            19.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 564642e9d..7f5c6bd39 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.128077                       # Nu
 sim_ticks                                128076812500                       # Number of ticks simulated
 final_tick                               128076812500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 329011                       # Simulator instruction rate (inst/s)
-host_op_rate                                   420055                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              598785355                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256952                       # Number of bytes of host memory used
-host_seconds                                   213.89                       # Real time elapsed on the host
+host_inst_rate                                 887065                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1132533                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1614418321                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277452                       # Number of bytes of host memory used
+host_seconds                                    79.33                       # Real time elapsed on the host
 sim_insts                                    70373629                       # Number of instructions simulated
 sim_ops                                      89847363                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -612,18 +612,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3089
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           30                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       214325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        15790                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        34314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        16890                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        36910                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       107032                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       107032                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        18908                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq        52966                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        53606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473302                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            526908                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2220672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54706                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       475898                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            530604                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2291072                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18443072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           20663744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           20734144                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       95333                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples       274239                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.025051                       # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index c506601b8..d6835fc82 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.203116                       # Nu
 sim_ticks                                203115876500                       # Number of ticks simulated
 final_tick                               203115876500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 563415                       # Simulator instruction rate (inst/s)
-host_op_rate                                   570710                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              851483432                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239344                       # Number of bytes of host memory used
-host_seconds                                   238.54                       # Real time elapsed on the host
+host_inst_rate                                1130669                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1145309                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1708768878                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305928                       # Number of bytes of host memory used
+host_seconds                                   118.87                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -485,18 +485,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3547
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        232523                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       209135                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       184923                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        36455                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       184976                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        36468                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       105179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       105179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq       187024                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq        45499                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       558971                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       447925                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1006896                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     23804608                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       559024                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       447938                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           1006962                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     23808000                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     17570752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           41375360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           41378752                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       99021                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples       436723                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.008273                       # Request fanout histogram
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index dac1409b7..5cadbdde3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000043                       # Nu
 sim_ticks                                       43191                       # Number of ticks simulated
 final_tick                                      43191                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 247811                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388428                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_tick_rate                                 428274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410016                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        57728                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index a72f38554..1db6620aa 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000054                       # Nu
 sim_ticks                                       54211                       # Number of ticks simulated
 final_tick                                      54211                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 192824                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389940                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
+host_tick_rate                                 316777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410608                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        54016                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index 016399c56..5a3d40466 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000030                       # Nu
 sim_ticks                                       29561                       # Number of ticks simulated
 final_tick                                      29561                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 198957                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389156                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_tick_rate                                 334780                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 410240                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        56000                       # Number of bytes read from this memory
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 122a8ae41..d1da3d54a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000038                       # Nu
 sim_ticks                                       37741                       # Number of ticks simulated
 final_tick                                      37741                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 330031                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 387076                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_tick_rate                                 544029                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 408776                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                             1                       # Clock period in ticks
 system.mem_ctrls.bytes_read::ruby.dir_cntrl0        60992                       # Number of bytes read from this memory
diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index d7fd446da..9f34f3699 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.230198                       # Nu
 sim_ticks                                230197694500                       # Number of ticks simulated
 final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 435347                       # Simulator instruction rate (inst/s)
-host_op_rate                                   458966                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              583184688                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252480                       # Number of bytes of host memory used
-host_seconds                                   394.73                       # Real time elapsed on the host
+host_inst_rate                                1151849                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1214340                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1543000471                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272972                       # Number of bytes of host memory used
+host_seconds                                   149.19                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -596,18 +596,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         1448                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           18                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         1506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           24                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1100                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1100                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         3051                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          689                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         7550                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3612                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             11162                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       287936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         7608                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3618                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             11226                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       291648                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       115520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             403456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             407168                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples         4840                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.033471                       # Request fanout histogram