diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:34 -0600 |
| commit | cfb805cc71bd1c4b72691b69faa879663e548c11 (patch) | |
| tree | 4ef4be8b34eb3722e303546a96956b1adaa3315b /tests/quick | |
| parent | 612f8f074fa1099cf70faf495d46cc647762a031 (diff) | |
| download | gem5-cfb805cc71bd1c4b72691b69faa879663e548c11.tar.xz | |
stats: update stats for ARMv8 changes
Diffstat (limited to 'tests/quick')
35 files changed, 4115 insertions, 2436 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 894acecbc..b5633ad46 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,13 +325,14 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fastmem=false @@ -264,6 +340,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -309,7 +386,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -321,10 +398,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -332,9 +434,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -359,7 +462,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -379,24 +482,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -404,9 +543,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1019,7 +1159,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 1e2520995..bf118f1e9 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:53 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:07:33 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800 + 0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 912096763500 because m5_exit instruction encountered +Exiting @ tick 912096767500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index eb8cedaf3..f0bd97b20 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,30 +1,30 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.912097 # Number of seconds simulated -sim_ticks 912096763500 # Number of ticks simulated -final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 912096767500 # Number of ticks simulated +final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1859152 # Simulator instruction rate (inst/s) -host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27516397451 # Simulator tick rate (ticks/s) -host_mem_usage 399324 # Number of bytes of host memory used -host_seconds 33.15 # Real time elapsed on the host -sim_insts 61625970 # Number of instructions simulated -sim_ops 79343340 # Number of ops (including micro ops) simulated +host_inst_rate 1391627 # Simulator instruction rate (inst/s) +host_op_rate 1791703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20594093924 # Simulator tick rate (ticks/s) +host_mem_usage 421260 # Number of bytes of host memory used +host_seconds 44.29 # Real time elapsed on the host +sim_insts 61634065 # Number of instructions simulated +sim_ops 79353129 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory @@ -32,12 +32,12 @@ system.physmem.bytes_written::total 7222864 # Nu system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory @@ -45,29 +45,29 @@ system.physmem.num_writes::total 822331 # Nu system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -86,24 +86,24 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64986577 # Throughput (bytes/s) -system.membus.data_through_bus 59274047 # Total data (bytes) +system.membus.throughput 64986682 # Throughput (bytes/s) +system.membus.data_through_bus 59274143 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -124,8 +124,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 # system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16906854 # Number of tag accesses -system.l2c.tags.data_accesses 16906854 # Number of data accesses +system.l2c.tags.tag_accesses 16908094 # Number of tag accesses +system.l2c.tags.data_accesses 16908094 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -172,9 +172,9 @@ system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses @@ -208,9 +208,9 @@ system.l2c.ReadReq_accesses::cpu1.data 174787 # nu system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) @@ -243,9 +243,9 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses @@ -285,33 +285,75 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154009014 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140471123 # Total data (bytes) +system.toL2Bus.throughput 154019994 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140481139 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 45730949 # Throughput (bytes/s) system.iobus.data_through_bus 41711051 # Total data (bytes) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7975768 # DTB read hits +system.cpu0.dtb.read_hits 7977216 # DTB read hits system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5966574 # DTB write hits +system.cpu0.dtb.write_hits 5966960 # DTB write hits system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7979379 # DTB read accesses -system.cpu0.dtb.write_accesses 5967246 # DTB write accesses +system.cpu0.dtb.read_accesses 7980827 # DTB read accesses +system.cpu0.dtb.write_accesses 5967632 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13942342 # DTB hits +system.cpu0.dtb.hits 13944176 # DTB hits system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13946625 # DTB accesses -system.cpu0.itb.inst_hits 30238804 # ITB inst hits +system.cpu0.dtb.accesses 13948459 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30245736 # ITB inst hits system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -321,80 +363,80 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses -system.cpu0.itb.hits 30238804 # DTB hits +system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses +system.cpu0.itb.hits 30245736 # DTB hits system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30240979 # DTB accesses -system.cpu0.numCycles 1823671407 # number of cpu cycles simulated +system.cpu0.itb.accesses 30247911 # DTB accesses +system.cpu0.numCycles 1823671415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29750005 # Number of instructions committed -system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses +system.cpu0.committedInsts 29756754 # Number of instructions committed +system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1241903 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34471201 # number of integer instructions +system.cpu0.num_func_calls 1242676 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34752271 # number of integer instructions system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written +system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14626951 # number of memory refs -system.cpu0.num_load_insts 8357226 # Number of load instructions -system.cpu0.num_store_insts 6269725 # Number of store instructions -system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles -system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles +system.cpu0.num_mem_refs 14629077 # number of memory refs +system.cpu0.num_load_insts 8358676 # Number of load instructions +system.cpu0.num_store_insts 6270401 # Number of store instructions +system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles +system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits -system.cpu0.icache.overall_hits::total 29811115 # number of overall hits +system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits +system.cpu0.icache.overall_hits::total 29818047 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,67 +447,67 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits -system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits +system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses -system.cpu0.dcache.overall_misses::total 364509 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses +system.cpu0.dcache.overall_misses::total 364518 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,28 +519,70 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks system.cpu0.dcache.writebacks::total 300958 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7364781 # DTB read hits +system.cpu1.dtb.read_hits 7365100 # DTB read hits system.cpu1.dtb.read_misses 3705 # DTB read misses -system.cpu1.dtb.write_hits 5489656 # DTB write hits +system.cpu1.dtb.write_hits 5489754 # DTB write hits system.cpu1.dtb.write_misses 1595 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7368486 # DTB read accesses -system.cpu1.dtb.write_accesses 5491251 # DTB write accesses +system.cpu1.dtb.read_accesses 7368805 # DTB read accesses +system.cpu1.dtb.write_accesses 5491349 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12854437 # DTB hits +system.cpu1.dtb.hits 12854854 # DTB hits system.cpu1.dtb.misses 5300 # DTB misses -system.cpu1.dtb.accesses 12859737 # DTB accesses -system.cpu1.itb.inst_hits 32412306 # ITB inst hits +system.cpu1.dtb.accesses 12860154 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 32413691 # ITB inst hits system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -508,48 +592,48 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses -system.cpu1.itb.hits 32412306 # DTB hits +system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses +system.cpu1.itb.hits 32413691 # DTB hits system.cpu1.itb.misses 2200 # DTB misses -system.cpu1.itb.accesses 32414506 # DTB accesses -system.cpu1.numCycles 1824193528 # number of cpu cycles simulated +system.cpu1.itb.accesses 32415891 # DTB accesses +system.cpu1.numCycles 1824193536 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31875965 # Number of instructions committed -system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses +system.cpu1.committedInsts 31877311 # Number of instructions committed +system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses -system.cpu1.num_func_calls 955227 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35797832 # number of integer instructions +system.cpu1.num_func_calls 955425 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35862250 # number of integer instructions system.cpu1.num_fp_insts 4436 # number of float instructions -system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written +system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written -system.cpu1.num_mem_refs 13370713 # number of memory refs -system.cpu1.num_load_insts 7642673 # Number of load instructions -system.cpu1.num_store_insts 5728040 # Number of store instructions -system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles -system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles +system.cpu1.num_mem_refs 13371151 # number of memory refs +system.cpu1.num_load_insts 7642991 # Number of load instructions +system.cpu1.num_store_insts 5728160 # Number of store instructions +system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles +system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -558,26 +642,26 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits -system.cpu1.icache.overall_hits::total 31979125 # number of overall hits +system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits +system.cpu1.icache.overall_hits::total 31980510 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses system.cpu1.icache.overall_misses::total 434454 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses @@ -595,10 +679,10 @@ system.cpu1.icache.cache_copies 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 294289 # number of replacements system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy @@ -608,56 +692,56 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses -system.cpu1.dcache.overall_misses::total 324195 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses +system.cpu1.dcache.overall_misses::total 324341 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index ab338ac30..54d6bfa01 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -288,7 +363,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 41742298b..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 8105d53fc..c1d447bb6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:43 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x55f5800 0x55f5800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332810264000 because m5_exit instruction encountered +Exiting @ tick 2332810269000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 0b833a71d..75a8f8d3e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810264000 # Number of ticks simulated -final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2332810269000 # Number of ticks simulated +final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1656319 # Simulator instruction rate (inst/s) -host_op_rate 2129924 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63962280307 # Simulator tick rate (ticks/s) -host_mem_usage 398176 # Number of bytes of host memory used -host_seconds 36.47 # Real time elapsed on the host -sim_insts 60408639 # Number of instructions simulated -sim_ops 77681819 # Number of ops (including micro ops) simulated +host_inst_rate 1274625 # Simulator instruction rate (inst/s) +host_op_rate 1639090 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49222371545 # Simulator tick rate (ticks/s) +host_mem_usage 420236 # Number of bytes of host memory used +host_seconds 47.39 # Real time elapsed on the host +sim_insts 60408649 # Number of instructions simulated +sim_ops 77681829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) @@ -48,9 +48,9 @@ system.physmem.bw_total::writebacks 1587455 # To system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -63,8 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969585 # Throughput (bytes/s) -system.membus.data_through_bus 130566422 # Total data (bytes) +system.membus.throughput 55969605 # Throughput (bytes/s) +system.membus.data_through_bus 130566470 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -75,9 +75,30 @@ system.cf0.dma_write_txs 0 # Nu system.iobus.throughput 48895252 # Throughput (bytes/s) system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971214 # DTB read hits +system.cpu.dtb.read_hits 14971217 # DTB read hits system.cpu.dtb.read_misses 7294 # DTB read misses system.cpu.dtb.write_hits 11217004 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses @@ -85,17 +106,38 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978508 # DTB read accesses +system.cpu.dtb.read_accesses 14978511 # DTB read accesses system.cpu.dtb.write_accesses 11219185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188218 # DTB hits +system.cpu.dtb.hits 26188221 # DTB hits system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26197693 # DTB accesses +system.cpu.dtb.accesses 26197696 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 61431840 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -106,7 +148,7 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -117,37 +159,37 @@ system.cpu.itb.inst_accesses 61436311 # IT system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665620529 # number of cpu cycles simulated +system.cpu.numCycles 4665620539 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60408639 # Number of instructions committed -system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses +system.cpu.committedInsts 60408649 # Number of instructions committed +system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 2136008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls -system.cpu.num_int_insts 68795605 # number of integer instructions +system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls +system.cpu.num_int_insts 69130761 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read -system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written +system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read +system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361637 # number of memory refs -system.cpu.num_load_insts 15639527 # Number of load instructions +system.cpu.num_mem_refs 27361639 # number of memory refs +system.cpu.num_load_insts 15639529 # Number of load instructions system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles -system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles +system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles +system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -192,16 +234,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy @@ -312,12 +354,12 @@ system.cpu.l2cache.writebacks::writebacks 57863 # n system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 623337 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -382,8 +424,8 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) +system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index da0c44ae8..9fa392075 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -295,7 +372,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -307,10 +384,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -318,9 +420,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -345,7 +448,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -365,24 +468,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -390,9 +529,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1029,7 +1169,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 012824f20..2b6d5c5d8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:31:37 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:08:43 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6319800 0x6319800 + 0: system.cpu1.isa: ISA system set to: 0x6319800 0x6319800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1196134388000 because m5_exit instruction encountered +Exiting @ tick 1196139241000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index da78d67e8..6ed9b7b45 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196134 # Number of seconds simulated -sim_ticks 1196134388000 # Number of ticks simulated -final_tick 1196134388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196139 # Number of seconds simulated +sim_ticks 1196139241000 # Number of ticks simulated +final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708523 # Simulator instruction rate (inst/s) -host_op_rate 902798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13791811883 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 86.73 # Real time elapsed on the host -sim_insts 61448705 # Number of instructions simulated -sim_ops 78297711 # Number of ops (including micro ops) simulated +host_inst_rate 553961 # Simulator instruction rate (inst/s) +host_op_rate 705843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10781179789 # Simulator tick rate (ticks/s) +host_mem_usage 425360 # Number of bytes of host memory used +host_seconds 110.95 # Real time elapsed on the host +sim_insts 61460236 # Number of instructions simulated +sim_ops 78311148 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4798512 # Number of bytes read from this memory -system.physmem.bytes_read::total 62145764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4112768 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory +system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7140112 # Number of bytes written to this memory +system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654482 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64262 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821098 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393546 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3950101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 270869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4011683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51955503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 270869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3438383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516727 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5969323 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3438383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3964314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 270869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6528410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57924826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654482 # Number of read requests accepted -system.physmem.writeReqs 821098 # Number of write requests accepted -system.physmem.readBursts 6654482 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425858048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 28800 # Total number of bytes read from write queue -system.physmem.bytesWritten 7268928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62145764 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7140112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 450 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707519 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11807 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415388 # Per bank write bursts -system.physmem.perBankRdBursts::1 415219 # Per bank write bursts -system.physmem.perBankRdBursts::2 415339 # Per bank write bursts -system.physmem.perBankRdBursts::3 415675 # Per bank write bursts -system.physmem.perBankRdBursts::4 422391 # Per bank write bursts -system.physmem.perBankRdBursts::5 415542 # Per bank write bursts -system.physmem.perBankRdBursts::6 415783 # Per bank write bursts -system.physmem.perBankRdBursts::7 415483 # Per bank write bursts -system.physmem.perBankRdBursts::8 416074 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415272 # Per bank write bursts -system.physmem.perBankRdBursts::11 414856 # Per bank write bursts -system.physmem.perBankRdBursts::12 415143 # Per bank write bursts -system.physmem.perBankRdBursts::13 415555 # Per bank write bursts -system.physmem.perBankRdBursts::14 415537 # Per bank write bursts -system.physmem.perBankRdBursts::15 415198 # Per bank write bursts -system.physmem.perBankWrBursts::0 6998 # Per bank write bursts -system.physmem.perBankWrBursts::1 6842 # Per bank write bursts -system.physmem.perBankWrBursts::2 7022 # Per bank write bursts -system.physmem.perBankWrBursts::3 7170 # Per bank write bursts -system.physmem.perBankWrBursts::4 7417 # Per bank write bursts -system.physmem.perBankWrBursts::5 7181 # Per bank write bursts -system.physmem.perBankWrBursts::6 7437 # Per bank write bursts -system.physmem.perBankWrBursts::7 7180 # Per bank write bursts -system.physmem.perBankWrBursts::8 7616 # Per bank write bursts -system.physmem.perBankWrBursts::9 7218 # Per bank write bursts -system.physmem.perBankWrBursts::10 7106 # Per bank write bursts -system.physmem.perBankWrBursts::11 6658 # Per bank write bursts -system.physmem.perBankWrBursts::12 6803 # Per bank write bursts -system.physmem.perBankWrBursts::13 7016 # Per bank write bursts -system.physmem.perBankWrBursts::14 7092 # Per bank write bursts -system.physmem.perBankWrBursts::15 6821 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654445 # Number of read requests accepted +system.physmem.writeReqs 821063 # Number of write requests accepted +system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue +system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415328 # Per bank write bursts +system.physmem.perBankRdBursts::1 415204 # Per bank write bursts +system.physmem.perBankRdBursts::2 415403 # Per bank write bursts +system.physmem.perBankRdBursts::3 415627 # Per bank write bursts +system.physmem.perBankRdBursts::4 422407 # Per bank write bursts +system.physmem.perBankRdBursts::5 415617 # Per bank write bursts +system.physmem.perBankRdBursts::6 415785 # Per bank write bursts +system.physmem.perBankRdBursts::7 415500 # Per bank write bursts +system.physmem.perBankRdBursts::8 416027 # Per bank write bursts +system.physmem.perBankRdBursts::9 415632 # Per bank write bursts +system.physmem.perBankRdBursts::10 415316 # Per bank write bursts +system.physmem.perBankRdBursts::11 414840 # Per bank write bursts +system.physmem.perBankRdBursts::12 415044 # Per bank write bursts +system.physmem.perBankRdBursts::13 415557 # Per bank write bursts +system.physmem.perBankRdBursts::14 415554 # Per bank write bursts +system.physmem.perBankRdBursts::15 415143 # Per bank write bursts +system.physmem.perBankWrBursts::0 6946 # Per bank write bursts +system.physmem.perBankWrBursts::1 6844 # Per bank write bursts +system.physmem.perBankWrBursts::2 7080 # Per bank write bursts +system.physmem.perBankWrBursts::3 7140 # Per bank write bursts +system.physmem.perBankWrBursts::4 7438 # Per bank write bursts +system.physmem.perBankWrBursts::5 7223 # Per bank write bursts +system.physmem.perBankWrBursts::6 7431 # Per bank write bursts +system.physmem.perBankWrBursts::7 7190 # Per bank write bursts +system.physmem.perBankWrBursts::8 7575 # Per bank write bursts +system.physmem.perBankWrBursts::9 7264 # Per bank write bursts +system.physmem.perBankWrBursts::10 7139 # Per bank write bursts +system.physmem.perBankWrBursts::11 6649 # Per bank write bursts +system.physmem.perBankWrBursts::12 6729 # Per bank write bursts +system.physmem.perBankWrBursts::13 7011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7090 # Per bank write bursts +system.physmem.perBankWrBursts::15 6760 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196129800000 # Total gap between requests +system.physmem.totGap 1196134740000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6825 # Read request sizes (log2) +system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159593 # Read request sizes (log2) +system.physmem.readPktSize::6 159532 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64262 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 634838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 481612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 482409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1125551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1120257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1116869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -165,28 +165,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -197,401 +197,419 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5819.401301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 396.636644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13081.491079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25728 34.57% 34.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15292 20.55% 55.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3262 4.38% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2304 3.10% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1614 2.17% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1322 1.78% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1040 1.40% 67.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1190 1.60% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 729 0.98% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 570 0.77% 71.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 569 0.76% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 665 0.89% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 312 0.42% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 285 0.38% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 210 0.28% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 384 0.52% 74.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 194 0.26% 74.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 136 0.18% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 150 0.20% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 155 0.21% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2260 3.04% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 107 0.14% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 57 0.08% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 59 0.08% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 48 0.06% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 56 0.08% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 51 0.07% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 23 0.03% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 212 0.28% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 23 0.03% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 26 0.03% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 105 0.14% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 24 0.03% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 92 0.12% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 21 0.03% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 18 0.02% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 21 0.03% 80.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 12 0.02% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 19 0.03% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 7 0.01% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 116 0.16% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 25 0.03% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 13 0.02% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 99 0.13% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 8 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 17 0.02% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 23 0.03% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 8 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 15 0.02% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 26 0.03% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 126 0.17% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 15 0.02% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 15 0.02% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 38 0.05% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 85 0.11% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 9 0.01% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 16 0.02% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 156 0.21% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 81.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 15 0.02% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 169 0.23% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 88 0.12% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 23 0.03% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 97 0.13% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 26 0.03% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 83 0.11% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 1 0.00% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 16 0.02% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 74 0.10% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 17 0.02% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 18 0.02% 82.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 158 0.21% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 22 0.03% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 1 0.00% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 18 0.02% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 80 0.11% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 161 0.22% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 14 0.02% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 83 0.11% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 26 0.03% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 95 0.13% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 23 0.03% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 85 0.11% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 14 0.02% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 2 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 160 0.21% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.10% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 35 0.05% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 73 0.10% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 102 0.14% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 14 0.02% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.02% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 79 0.11% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 6 0.01% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 79 0.11% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 82 0.11% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 173 0.23% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 28 0.04% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 20 0.03% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 17 0.02% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 1 0.00% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 165 0.22% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 18 0.02% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.46% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::23040-23047 83 0.11% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 156 0.21% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 72 0.10% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 14 0.02% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 162 0.22% 88.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 2 0.00% 88.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 25 0.03% 88.83% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::28160-28167 33 0.04% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 78 0.10% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 106 0.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 16 0.02% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 11 0.01% 90.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 79 0.11% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 86 0.12% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 2 0.00% 90.47% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::33344-33351 3 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 12 0.02% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 159 0.21% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 20 0.03% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 27 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 160 0.21% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::35072-35079 84 0.11% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 78 0.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 3 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 85 0.11% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 78 0.10% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 11 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 15 0.02% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 99 0.13% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 73 0.10% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 93.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 31 0.04% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 71 0.10% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 147 0.20% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 15 0.02% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 87 0.12% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 22 0.03% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 90 0.12% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 2 0.00% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 24 0.03% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 84 0.11% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 9 0.01% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 2 0.00% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 152 0.20% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 74 0.10% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40263 2 0.00% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 22 0.03% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40768-40775 2 0.00% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 160 0.21% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 14 0.02% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 72 0.10% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 153 0.21% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 1 0.00% 94.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 11 0.01% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 81 0.11% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 25 0.03% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 90 0.12% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 18 0.02% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43392-43399 1 0.00% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 87 0.12% 95.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 17 0.02% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 146 0.20% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 71 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 32 0.04% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 1 0.00% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 75 0.10% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 96 0.13% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 16 0.02% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 9 0.01% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 79 0.11% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 86 0.12% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 3 0.00% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46784-46791 1 0.00% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 84 0.11% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 165 0.22% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 25 0.03% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 19 0.03% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 184 0.25% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 2 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 42 0.06% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48448-48455 1 0.00% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 81 0.11% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 14 0.02% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 7 0.01% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 10 0.01% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 7 0.01% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2105 2.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74428 # Bytes accessed per row activation -system.physmem.totQLat 159442536500 # Total ticks spent queuing -system.physmem.totMemAccLat 202459287750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33270160000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9746591250 # Total ticks spent accessing banks -system.physmem.avgQLat 23961.79 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1464.76 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation +system.physmem.totQLat 159552537250 # Total ticks spent queuing +system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks +system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30426.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.52 # Average write queue length when enqueuing -system.physmem.readRowHits 6598367 # Number of row buffer hits during reads -system.physmem.writeRowHits 94814 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing +system.physmem.readRowHits 6598277 # Number of row buffer hits during reads +system.physmem.writeRowHits 94784 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 160004.95 # Average gap between requests +system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes +system.physmem.avgGap 160007.15 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.95 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -610,314 +628,314 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59941628 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703327 # Transaction distribution -system.membus.trans_dist::ReadResp 7703327 # Transaction distribution -system.membus.trans_dist::WriteReq 767563 # Transaction distribution -system.membus.trans_dist::WriteResp 767563 # Transaction distribution -system.membus.trans_dist::Writeback 64262 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31362 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17250 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11807 # Transaction distribution -system.membus.trans_dist::ReadExReq 137774 # Transaction distribution -system.membus.trans_dist::ReadExResp 137331 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382556 # Packet count per connected master and slave (bytes) +system.membus.throughput 59936382 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703367 # Transaction distribution +system.membus.trans_dist::ReadResp 7703367 # Transaction distribution +system.membus.trans_dist::WriteReq 767572 # Transaction distribution +system.membus.trans_dist::WriteResp 767572 # Transaction distribution +system.membus.trans_dist::Writeback 64227 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution +system.membus.trans_dist::ReadExReq 137706 # Transaction distribution +system.membus.trans_dist::ReadExResp 137264 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17341566 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389866 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17381364 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19793730 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71698242 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71698242 # Total data (bytes) +system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71692258 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224728000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9233500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211169999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5081009046 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657682249 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69474 # number of replacements -system.l2c.tags.tagsinuse 52958.436277 # Cycle average of tags in use -system.l2c.tags.total_refs 1673866 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134633 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.432806 # Average number of references to valid blocks. +system.l2c.tags.replacements 69413 # number of replacements +system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use +system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40141.137275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3711.443492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4231.516476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2812.646868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2058.946054 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612505 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056632 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17208079 # Number of tag accesses -system.l2c.tags.data_accesses 17208079 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1845 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464495 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143269 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246060 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570845 # number of Writeback hits -system.l2c.Writeback_hits::total 570845 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 560 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1719 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56634 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109230 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1845 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464495 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 195865 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355290 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3830 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1752 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits -system.l2c.overall_hits::cpu0.data 262480 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5350 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1845 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464495 # number of overall hits -system.l2c.overall_hits::cpu1.data 195865 # number of overall hits -system.l2c.overall_hits::total 1355290 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17211018 # Number of tag accesses +system.l2c.tags.data_accesses 17211018 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits +system.l2c.Writeback_hits::total 571037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits 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# number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7847 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5729 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5057 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3618 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22263 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4707 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3611 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8318 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 483 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1046 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67314 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72460 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139774 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 5067 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3614 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22269 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3647 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8566 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000747 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000542 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279757 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106790 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 300318250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4786751376 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9560422936 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 345201250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12449699492 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5636750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292835997 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167093373489 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1043988495 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722457655 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16766446150 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 345201250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13493687987 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5636750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015293652 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183859819639 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036725 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809712 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865654 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.832621 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721649 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823224 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579058 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561585 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61887.663948 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62450.197300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66205.776672 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61371.473767 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.017846 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.629189 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.097379 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.436945 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.561077 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.035373 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54391.368616 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62609.247888 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58651.585338 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58655.624576 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55174.000958 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62780.286049 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59025.268693 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58768.841591 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55174.000958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60061.894404 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62780.286049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59025.268693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1111,62 +1129,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119504988 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535165 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535165 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767563 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767563 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570845 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30638 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17564 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48202 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260860 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260860 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864640 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226897 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6150 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600271 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7671923 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41401460 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30051724 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39586058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138342918 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138342918 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4601108 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4758624958 # Layer occupancy (ticks) +system.toL2Bus.throughput 119505667 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138342022 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1926201968 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1755625353 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2116407722 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2924723840 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326499 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 9919749 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391537 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671396 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671396 # Transaction distribution -system.iobus.trans_dist::WriteReq 7946 # Transaction distribution -system.iobus.trans_dist::WriteResp 7946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8052 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 45391376 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution +system.iobus.trans_dist::WriteReq 7950 # Transaction distribution +system.iobus.trans_dist::WriteResp 7950 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1188,12 +1206,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358684 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1215,14 +1233,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389866 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294378 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294406 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4032000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1268,32 +1286,74 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374610000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778098751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7069308 # DTB read hits -system.cpu0.dtb.read_misses 3747 # DTB read misses -system.cpu0.dtb.write_hits 5655300 # DTB write hits -system.cpu0.dtb.write_misses 806 # DTB write misses +system.cpu0.dtb.read_hits 7064121 # DTB read hits +system.cpu0.dtb.read_misses 3756 # DTB read misses +system.cpu0.dtb.write_hits 5649416 # DTB write hits +system.cpu0.dtb.write_misses 801 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1799 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073055 # DTB read accesses -system.cpu0.dtb.write_accesses 5656106 # DTB write accesses +system.cpu0.dtb.read_accesses 7067877 # DTB read accesses +system.cpu0.dtb.write_accesses 5650217 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12724608 # DTB hits -system.cpu0.dtb.misses 4553 # DTB misses -system.cpu0.dtb.accesses 12729161 # DTB accesses -system.cpu0.itb.inst_hits 29565201 # ITB inst hits +system.cpu0.dtb.hits 12713537 # DTB hits +system.cpu0.dtb.misses 4557 # DTB misses +system.cpu0.dtb.accesses 12718094 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 29561361 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1303,94 +1363,94 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29567406 # ITB inst accesses -system.cpu0.itb.hits 29565201 # DTB hits +system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses +system.cpu0.itb.hits 29561361 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29567406 # DTB accesses -system.cpu0.numCycles 2392268776 # number of cpu cycles simulated +system.cpu0.itb.accesses 29563566 # DTB accesses +system.cpu0.numCycles 2392278482 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28867316 # Number of instructions committed -system.cpu0.committedOps 37205643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33092917 # Number of integer alu accesses +system.cpu0.committedInsts 28863304 # Number of instructions committed +system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241596 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372519 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33092917 # number of integer instructions +system.cpu0.num_func_calls 1241816 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33114268 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190017972 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36219842 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13392372 # number of memory refs -system.cpu0.num_load_insts 7406786 # Number of load instructions -system.cpu0.num_store_insts 5985586 # Number of store instructions -system.cpu0.num_idle_cycles 2246456550.382122 # Number of idle cycles -system.cpu0.num_busy_cycles 145812225.617878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060951 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939049 # Percentage of idle cycles +system.cpu0.num_mem_refs 13380719 # number of memory refs +system.cpu0.num_load_insts 7401377 # Number of load instructions +system.cpu0.num_store_insts 5979342 # Number of store instructions +system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles +system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46712 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 425445 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.359322 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29139226 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.408844 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 424872 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359322 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29991142 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29991142 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29139226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29139226 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29139226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29139226 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29139226 # number of overall hits -system.cpu0.icache.overall_hits::total 29139226 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses -system.cpu0.icache.overall_misses::total 425958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5905644218 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5905644218 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5905644218 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5905644218 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5905644218 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5905644218 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29565184 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29565184 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29565184 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29565184 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29565184 # number of overall (read+write) accesses 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11860.470581 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 330301 # number of replacements -system.cpu0.dcache.tags.tagsinuse 454.615886 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12269300 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330813 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.088325 # Average number of references to valid blocks. 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of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149654 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149654 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11938799 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11938799 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11938799 # number of overall hits +system.cpu0.dcache.overall_hits::total 11938799 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227537 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227537 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141373 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141373 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9339 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9339 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7481 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7481 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368910 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368910 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368910 # number of overall misses +system.cpu0.dcache.overall_misses::total 368910 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3307426746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3307426746 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5667209233 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5667209233 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93091750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 93091750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44245560 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44245560 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8974635979 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8974635979 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8974635979 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8974635979 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821698 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6821698 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5486011 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5486011 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157343 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157343 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157135 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12307709 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12307709 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12307709 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12307709 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033355 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033355 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025770 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025770 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059354 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059354 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047609 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047609 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14505.321584 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14505.321584 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40159.378806 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40159.378806 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9827.753788 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9827.753788 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5915.322379 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5915.322379 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24339.217056 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24339.217056 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1529,66 +1589,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305829 # number of writebacks -system.cpu0.dcache.writebacks::total 305829 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227704 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227704 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141542 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141542 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9305 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9305 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7514 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7514 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369246 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369246 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369246 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369246 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2845576254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2845576254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5370172205 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5370172205 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72789751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72789751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29432437 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29432437 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8215748459 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8215748459 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8215748459 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8215748459 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13558596000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13558596000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167114500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167114500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14725710500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14725710500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047817 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047817 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks +system.cpu0.dcache.writebacks::total 305670 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9339 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9339 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368910 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 368910 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368910 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368910 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2850420254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2850420254 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5353542767 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5353542767 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74365250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74365250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29286440 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29286440 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8203963021 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12496.821549 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12496.821549 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37940.485545 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37940.485545 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7822.649221 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7822.649221 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3917.013175 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3917.013175 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1596,28 +1652,70 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311308 # DTB read hits -system.cpu1.dtb.read_misses 3642 # DTB read misses -system.cpu1.dtb.write_hits 5827742 # DTB write hits -system.cpu1.dtb.write_misses 1438 # DTB write misses +system.cpu1.dtb.read_hits 8319266 # DTB read hits +system.cpu1.dtb.read_misses 3647 # DTB read misses +system.cpu1.dtb.write_hits 5834802 # DTB write hits +system.cpu1.dtb.write_misses 1433 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314950 # DTB read accesses -system.cpu1.dtb.write_accesses 5829180 # DTB write accesses +system.cpu1.dtb.read_accesses 8322913 # DTB read accesses +system.cpu1.dtb.write_accesses 5836235 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14139050 # DTB hits +system.cpu1.dtb.hits 14154068 # DTB hits system.cpu1.dtb.misses 5080 # DTB misses -system.cpu1.dtb.accesses 14144130 # DTB accesses -system.cpu1.itb.inst_hits 33191969 # ITB inst hits +system.cpu1.dtb.accesses 14159148 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 33207997 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1627,93 +1725,93 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33194140 # ITB inst accesses -system.cpu1.itb.hits 33191969 # DTB hits +system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses +system.cpu1.itb.hits 33207997 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33194140 # DTB accesses -system.cpu1.numCycles 2390799575 # number of cpu cycles simulated +system.cpu1.itb.accesses 33210168 # DTB accesses +system.cpu1.numCycles 2390803785 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32581389 # Number of instructions committed -system.cpu1.committedOps 41092068 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37316324 # Number of integer alu accesses +system.cpu1.committedInsts 32596932 # Number of instructions committed +system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962102 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732829 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37316324 # number of integer instructions +system.cpu1.num_func_calls 962790 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37644247 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213681333 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39457808 # number of times the integer registers were written +system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14676854 # number of memory refs -system.cpu1.num_load_insts 8633232 # Number of load instructions -system.cpu1.num_store_insts 6043622 # Number of store instructions -system.cpu1.num_idle_cycles 1874349488.166457 # Number of idle cycles -system.cpu1.num_busy_cycles 516450086.833543 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216016 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783984 # Percentage of idle cycles +system.cpu1.num_mem_refs 14692820 # number of memory refs +system.cpu1.num_load_insts 8641241 # Number of load instructions +system.cpu1.num_store_insts 6051579 # Number of store instructions +system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles +system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43916 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469558 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.567582 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32721895 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470070 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.610686 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93987592500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.567582 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934702 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934702 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469929 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33662035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33662035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32721895 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32721895 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32721895 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32721895 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32721895 # number of overall hits -system.cpu1.icache.overall_hits::total 32721895 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470070 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470070 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470070 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470070 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470070 # number of overall misses -system.cpu1.icache.overall_misses::total 470070 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6444934971 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6444934971 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6444934971 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6444934971 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6444934971 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6444934971 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33191965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33191965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33191965 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33191965 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33191965 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33191965 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014162 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014162 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014162 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014162 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014162 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014162 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13710.585596 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13710.585596 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13710.585596 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13710.585596 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits +system.cpu1.icache.overall_hits::total 32737552 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses +system.cpu1.icache.overall_misses::total 470441 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1722,126 +1820,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470070 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470070 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 470070 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 470070 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 470070 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 470070 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5502849027 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5502849027 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5502849027 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5502849027 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5502849027 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5502849027 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014162 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014162 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014162 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014162 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11706.445906 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.445906 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles 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11698.166778 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292078 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.633961 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11962120 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292453 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.902709 # Average number of references to valid blocks. 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Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49497647 # 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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70722250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70722250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32100518 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32100518 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8123818550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8123818550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8123818550 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8123818550 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168605274000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168605274000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182596842 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182596842 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193787870842 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193787870842 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023964 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023964 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030127 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118999 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118999 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026501 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026501 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11009.033384 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11009.033384 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41652.856825 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41652.856825 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6397.308910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6397.308910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3193.445881 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3193.445881 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks +system.cpu1.dcache.writebacks::total 265367 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1933,10 +2027,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651789578751 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651789578751 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651789578751 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651789578751 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index ea47afb6b..4a127f1c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -281,7 +356,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 41742298b..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 866b5bc98..a3076394e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:31:30 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:08:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x6b2c800 0x6b2c800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2616536483000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 9c560044d..9cf325a75 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,43 +4,43 @@ sim_seconds 2.616536 # Nu sim_ticks 2616536483000 # Number of ticks simulated final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 577538 # Simulator instruction rate (inst/s) -host_op_rate 734941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25103147507 # Simulator tick rate (ticks/s) -host_mem_usage 400220 # Number of bytes of host memory used -host_seconds 104.23 # Real time elapsed on the host -sim_insts 60197580 # Number of instructions simulated -sim_ops 76603973 # Number of ops (including micro ops) simulated +host_inst_rate 506890 # Simulator instruction rate (inst/s) +host_op_rate 645039 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22032386663 # Simulator tick rate (ticks/s) +host_mem_usage 421264 # Number of bytes of host memory used +host_seconds 118.76 # Real time elapsed on the host +sim_insts 60197590 # Number of instructions simulated +sim_ops 76603983 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089752 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142063 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494705 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) @@ -48,17 +48,17 @@ system.physmem.bw_total::writebacks 1416443 # To system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494693 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53200016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494705 # Number of read requests accepted system.physmem.writeReqs 811927 # Number of write requests accepted -system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15494705 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 991556032 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 132477536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one @@ -77,7 +77,7 @@ system.physmem.perBankRdBursts::10 967949 # Pe system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967766 # Per bank write bursts +system.physmem.perBankRdBursts::14 967778 # Per bank write bursts system.physmem.perBankRdBursts::15 967796 # Per bank write bursts system.physmem.perBankWrBursts::0 6610 # Per bank write bursts system.physmem.perBankWrBursts::1 6410 # Per bank write bursts @@ -100,7 +100,7 @@ system.physmem.numWrRetry 0 # Nu system.physmem.totGap 2616532122000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6652 # Read request sizes (log2) +system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) @@ -112,7 +112,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1247001 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see @@ -176,98 +176,98 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11133.405772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.811660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16712.159564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23202 25.87% 25.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14564 16.24% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2857 3.19% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2044 2.28% 47.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1359 1.52% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1218 1.36% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 957 1.07% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1129 1.26% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 646 0.72% 53.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 589 0.66% 54.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 513 0.57% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 690 0.77% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 338 0.38% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 262 0.29% 56.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 213 0.24% 56.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 156 0.17% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 151 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 136 0.15% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 156 0.17% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 102 0.11% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2292 2.56% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 63 0.07% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 60 0.07% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 44 0.05% 61.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 30 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 303 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 33 0.04% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.01% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 97 0.11% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 22 0.02% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 14 0.02% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 28 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 19 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 14 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 14 0.02% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 9 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 370 0.41% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 17 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 15 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 14 0.02% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 12 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 37 0.04% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 13 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 11 0.01% 63.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 11 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 10 0.01% 63.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 84 0.09% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 83 0.09% 63.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 89 0.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 88 0.10% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 434 0.48% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 435 0.49% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 9 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 6 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 9 0.01% 64.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 65 0.07% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 67 0.07% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 280 0.31% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation @@ -291,7 +291,7 @@ system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation @@ -420,7 +420,7 @@ system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation @@ -456,7 +456,7 @@ system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation @@ -489,7 +489,7 @@ system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation @@ -507,7 +507,7 @@ system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation @@ -613,15 +613,15 @@ system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation -system.physmem.totQLat 373683436750 # Total ticks spent queuing -system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks -system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 89676 # Bytes accessed per row activation +system.physmem.totQLat 373682624750 # Total ticks spent queuing +system.physmem.totMemAccLat 469595819750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465315000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18447880000 # Total ticks spent accessing banks +system.physmem.avgQLat 24119.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.72 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30310.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s @@ -632,11 +632,11 @@ system.physmem.busUtilRead 2.96 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419160 # Number of row buffer hits during reads +system.physmem.readRowHits 15419173 # Number of row buffer hits during reads system.physmem.writeRowHits 91146 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes -system.physmem.avgGap 160458.28 # Average gap between requests +system.physmem.avgGap 160458.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -651,9 +651,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54116520 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546551 # Transaction distribution -system.membus.trans_dist::ReadResp 16546551 # Transaction distribution +system.membus.throughput 54116538 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546563 # Transaction distribution +system.membus.trans_dist::ReadResp 16546563 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution system.membus.trans_dist::Writeback 57909 # Transaction distribution @@ -665,21 +665,21 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 23 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280385 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951233 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914505 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597849 # Total data (bytes) +system.membus.tot_pkt_size::total 141597897 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597897 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -689,9 +689,9 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910622000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950375335 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) @@ -814,9 +814,30 @@ system.iobus.respLayer0.utilization 0.1 # La system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995644 # DTB read hits +system.cpu.dtb.read_hits 14995647 # DTB read hits system.cpu.dtb.read_misses 7334 # DTB read misses system.cpu.dtb.write_hits 11230146 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses @@ -824,17 +845,38 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002978 # DTB read accesses +system.cpu.dtb.read_accesses 15002981 # DTB read accesses system.cpu.dtb.write_accesses 11232358 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26225790 # DTB hits +system.cpu.dtb.hits 26225793 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26235336 # DTB accesses +system.cpu.dtb.accesses 26235339 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 61491413 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -845,7 +887,7 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -859,20 +901,20 @@ system.cpu.itb.accesses 61495884 # DT system.cpu.numCycles 5233072966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197580 # Number of instructions committed -system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses +system.cpu.committedInsts 60197590 # Number of instructions committed +system.cpu.committedOps 76603983 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69206189 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 2140403 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls -system.cpu.num_int_insts 68871033 # number of integer instructions +system.cpu.num_conditional_control_insts 7948249 # number of instructions that are conditional controls +system.cpu.num_int_insts 69206189 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written +system.cpu.num_int_register_reads 401354573 # number of times the integer registers were read +system.cpu.num_int_register_writes 74515956 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393280 # number of memory refs -system.cpu.num_load_insts 15659727 # Number of load instructions +system.cpu.num_mem_refs 27393282 # number of memory refs +system.cpu.num_load_insts 15659729 # Number of load instructions system.cpu.num_store_insts 11733553 # Number of store instructions system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles @@ -881,12 +923,12 @@ system.cpu.idle_fraction 0.875495 # Pe system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed system.cpu.icache.tags.replacements 856260 # number of replacements -system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.868407 # Cycle average of tags in use system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.868407 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -909,12 +951,12 @@ system.cpu.icache.demand_misses::cpu.inst 856772 # n system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses system.cpu.icache.overall_misses::total 856772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11774021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11774021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11774021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11774021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11774021000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses @@ -927,12 +969,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.303670 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.303670 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.303670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.303670 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,44 +989,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856772 system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 435943750 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.580126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.580126 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 50754.656257 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.394097 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977018 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -1045,23 +1087,23 @@ system.cpu.l2cache.overall_misses::cpu.data 143632 # system.cpu.l2cache.overall_misses::total 154224 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752204750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737637250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1490297250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752512000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 736932000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1489899250 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9620282393 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9620282393 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9619897393 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9619897393 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 752204750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10357919643 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11110579643 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 752512000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10356829393 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11109796643 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 752204750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10357919643 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11110579643 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 752512000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10356829393 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11109796643 # number of overall miss cycles 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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71092.300425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.147620 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73030.697025 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71888.108868 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71888.108868 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71885.231933 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71885.231933 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72041.832938 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72036.755907 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72041.832938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72036.755907 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1152,31 +1194,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss 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16702635150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582400 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703453650 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359679900 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183704038650 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses @@ -1198,23 +1240,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58539.230043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62672.418187 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60524.447331 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58568.351441 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62600.316036 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60504.889466 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59371.424247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59371.424247 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1225,12 +1267,12 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 626139 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 511.876590 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1262,16 +1304,16 @@ system.cpu.dcache.demand_misses::cpu.data 618199 # n system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses system.cpu.dcache.overall_misses::total 618199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5415523000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5415523000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621830515 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11621830515 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158390000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158390000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17037353515 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17037353515 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17037353515 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17037353515 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) @@ -1294,16 +1336,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.935999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.935999 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46460.375042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46460.375042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13910.943264 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13910.943264 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27559.658807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27559.658807 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1324,22 +1366,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 618199 system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069604485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069604485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135564000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135564000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15746722485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15746722485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15746722485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15746722485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050737750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050737750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284890100 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284890100 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses @@ -1350,16 +1392,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.695066 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.695066 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44252.751344 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44252.751344 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11906.200597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11906.200597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1367,9 +1409,9 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution +system.cpu.toL2Bus.throughput 52965212 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454596 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution @@ -1377,23 +1419,23 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749353 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614893 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138419097 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138419097 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008588500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295451750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534384415 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 4f02f4af8..20c714ee4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,13 +325,14 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fastmem=false @@ -264,6 +340,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -284,10 +361,34 @@ tracer=system.cpu1.tracer width=1 workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -295,6 +396,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -302,24 +404,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -327,6 +464,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -941,7 +1079,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index 38a425305..08406cf3a 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -11,8 +11,12 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 312a2d840..f0d337e74 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:32:17 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:10:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x56d2400 0x56d2400 + 0: system.cpu1.isa: ISA system set to: 0x56d2400 0x56d2400 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index af2c3099c..9511fe4d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,29 +1,29 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810264000 # Number of ticks simulated -final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2332810269000 # Number of ticks simulated +final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1583722 # Simulator instruction rate (inst/s) -host_op_rate 2036569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61158803315 # Simulator tick rate (ticks/s) -host_mem_usage 399324 # Number of bytes of host memory used -host_seconds 38.14 # Real time elapsed on the host -sim_insts 60408639 # Number of instructions simulated -sim_ops 77681819 # Number of ops (including micro ops) simulated +host_inst_rate 1221068 # Simulator instruction rate (inst/s) +host_op_rate 1570218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47154151043 # Simulator tick rate (ticks/s) +host_mem_usage 421264 # Number of bytes of host memory used +host_seconds 49.47 # Real time elapsed on the host +sim_insts 60408649 # Number of instructions simulated +sim_ops 77681829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6494800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 492744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6494808 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492704 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 121450764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 492744 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory @@ -31,11 +31,11 @@ system.physmem.bytes_written::total 6718884 # Nu system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101517 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118198 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory @@ -43,14 +43,14 @@ system.physmem.num_writes::total 811821 # Nu system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2784110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2784113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211223 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s) @@ -59,11 +59,11 @@ system.physmem.bw_total::writebacks 1587373 # To system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3386724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3386727 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942166 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,23 +76,23 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969561 # Throughput (bytes/s) -system.membus.data_through_bus 130566366 # Total data (bytes) +system.membus.throughput 55969581 # Throughput (bytes/s) +system.membus.data_through_bus 130566414 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.tagsinuse 50006.300115 # Cycle average of tags in use system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571374 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495752 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy @@ -115,38 +115,38 @@ system.l2c.tags.tag_accesses 17104735 # Nu system.l2c.tags.data_accesses 17104735 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 473132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 196968 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 365737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169792 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 365739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169796 # number of ReadReq hits system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits system.l2c.Writeback_hits::total 592682 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63335 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50403 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 63334 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50404 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 473134 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 473132 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 260302 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 365737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 365739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 220200 # number of demand (read+write) hits system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits -system.l2c.overall_hits::cpu0.inst 473134 # number of overall hits -system.l2c.overall_hits::cpu0.data 260307 # number of overall hits +system.l2c.overall_hits::cpu0.inst 473132 # number of overall hits +system.l2c.overall_hits::cpu0.data 260302 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits -system.l2c.overall_hits::cpu1.inst 365737 # number of overall hits -system.l2c.overall_hits::cpu1.data 220195 # number of overall hits +system.l2c.overall_hits::cpu1.inst 365739 # number of overall hits +system.l2c.overall_hits::cpu1.data 220200 # number of overall hits system.l2c.overall_hits::total 1338580 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses @@ -177,65 +177,65 @@ system.l2c.overall_misses::cpu1.data 41049 # nu system.l2c.overall_misses::total 153953 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 480419 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 202779 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 480417 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202775 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 369056 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173857 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 369058 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 173861 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159823 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 87387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 159822 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 87388 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 480419 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 362602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 480417 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 362597 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 369056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261244 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 369058 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 261249 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 480419 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 362602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 480417 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 362597 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 369056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261244 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 369058 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 261249 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603718 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423221 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.603722 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.423216 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282118 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157129 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157126 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.282118 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157129 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157126 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -254,87 +254,129 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119250 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137913994 # Total data (bytes) +system.toL2Bus.throughput 59119271 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137914042 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 48895252 # Throughput (bytes/s) system.iobus.data_through_bus 114063346 # Total data (bytes) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929205 # DTB read hits -system.cpu0.dtb.read_misses 6441 # DTB read misses -system.cpu0.dtb.write_hits 6437098 # DTB write hits -system.cpu0.dtb.write_misses 1932 # DTB write misses -system.cpu0.dtb.flush_tlb 1168 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7929199 # DTB read hits +system.cpu0.dtb.read_misses 6444 # DTB read misses +system.cpu0.dtb.write_hits 6437089 # DTB write hits +system.cpu0.dtb.write_misses 1929 # DTB write misses +system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5576 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5568 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7935646 # DTB read accesses -system.cpu0.dtb.write_accesses 6439030 # DTB write accesses +system.cpu0.dtb.read_accesses 7935643 # DTB read accesses +system.cpu0.dtb.write_accesses 6439018 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14366303 # DTB hits +system.cpu0.dtb.hits 14366288 # DTB hits system.cpu0.dtb.misses 8373 # DTB misses -system.cpu0.dtb.accesses 14374676 # DTB accesses -system.cpu0.itb.inst_hits 32543253 # ITB inst hits +system.cpu0.dtb.accesses 14374661 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 32543256 # ITB inst hits system.cpu0.itb.inst_misses 3703 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1168 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2636 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32546956 # ITB inst accesses -system.cpu0.itb.hits 32543253 # DTB hits +system.cpu0.itb.inst_accesses 32546959 # ITB inst accesses +system.cpu0.itb.hits 32543256 # DTB hits system.cpu0.itb.misses 3703 # DTB misses -system.cpu0.itb.accesses 32546956 # DTB accesses -system.cpu0.numCycles 4633633401 # number of cpu cycles simulated +system.cpu0.itb.accesses 32546959 # DTB accesses +system.cpu0.numCycles 4633654699 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31998091 # Number of instructions committed -system.cpu0.committedOps 41901593 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37065495 # Number of integer alu accesses +system.cpu0.committedInsts 31998107 # Number of instructions committed +system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37244533 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207173 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285544 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37065495 # number of integer instructions +system.cpu0.num_func_calls 1207172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4285554 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37244533 # number of integer instructions system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 188704279 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39536975 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192529528 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39716026 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15013057 # number of memory refs +system.cpu0.num_mem_refs 15013044 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions -system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 4555668120.247687 # Number of idle cycles -system.cpu0.num_busy_cycles 77965280.752313 # Number of busy cycles -system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles +system.cpu0.num_store_insts 6708383 # Number of store instructions +system.cpu0.num_idle_cycles 4553702806.473283 # Number of idle cycles +system.cpu0.num_busy_cycles 79951892.526717 # Number of busy cycles +system.cpu0.not_idle_fraction 0.017255 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.982745 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy +system.cpu0.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.509134 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.169458 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868182 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131190 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id @@ -344,32 +386,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 32064740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28518758 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32064735 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28518763 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 32064740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28518758 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32064735 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28518763 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 32064740 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28518758 # number of overall hits system.cpu0.icache.overall_hits::total 60583498 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 481297 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 369805 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 481295 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 369807 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 481297 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 369805 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 481295 # number of demand (read+write) misses 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system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32546032 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 28888568 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 32546035 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 28888565 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32546032 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 28888568 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32546035 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 28888565 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses @@ -390,13 +432,13 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 623334 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628286 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.avg_refs 37.875190 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298836 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698194 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -405,73 +447,73 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97632366 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97632366 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5776861 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4185204 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 97632374 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97632374 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6995580 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6184442 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13180022 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5776847 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4185218 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139289 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96747 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139292 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96744 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145935 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101283 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145938 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101280 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12772451 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10369634 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23142085 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12772451 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10369634 # number of overall hits -system.cpu0.dcache.overall_hits::total 23142085 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 196132 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 169321 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12772427 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10369660 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23142087 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12772427 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10369660 # number of overall hits +system.cpu0.dcache.overall_hits::total 23142087 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 196128 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 169325 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 365453 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 161355 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 88800 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 161354 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 88801 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 357487 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 258121 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 357482 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 258126 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 615608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 357487 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 258121 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 357482 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 258126 # number of overall misses system.cpu0.dcache.overall_misses::total 615608 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353751 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13545473 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938216 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274004 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353767 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13545475 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938201 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274019 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145936 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145939 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101280 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145935 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101283 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145938 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101280 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13129938 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10627755 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23757693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13129938 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10627755 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23757693 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027272 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026649 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13129909 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10627786 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23757695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13129909 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10627786 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23757695 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027271 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045547 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045546 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044787 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024287 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024287 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -484,68 +526,110 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks system.cpu0.dcache.writebacks::total 592682 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038595 # DTB read hits -system.cpu1.dtb.read_misses 4223 # DTB read misses -system.cpu1.dtb.write_hits 4778906 # DTB write hits -system.cpu1.dtb.write_misses 1249 # DTB write misses -system.cpu1.dtb.flush_tlb 1166 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7038606 # DTB read hits +system.cpu1.dtb.read_misses 4220 # DTB read misses +system.cpu1.dtb.write_hits 4778915 # DTB write hits +system.cpu1.dtb.write_misses 1252 # DTB write misses +system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2949 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2946 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 82 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042818 # DTB read accesses -system.cpu1.dtb.write_accesses 4780155 # DTB write accesses +system.cpu1.dtb.read_accesses 7042826 # DTB read accesses +system.cpu1.dtb.write_accesses 4780167 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11817501 # DTB hits +system.cpu1.dtb.hits 11817521 # DTB hits system.cpu1.dtb.misses 5472 # DTB misses -system.cpu1.dtb.accesses 11822973 # DTB accesses -system.cpu1.itb.inst_hits 28886892 # ITB inst hits +system.cpu1.dtb.accesses 11822993 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 28886889 # ITB inst hits system.cpu1.itb.inst_misses 2463 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1166 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1597 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1658 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28889355 # ITB inst accesses -system.cpu1.itb.hits 28886892 # DTB hits +system.cpu1.itb.inst_accesses 28889352 # ITB inst accesses +system.cpu1.itb.hits 28886889 # DTB hits system.cpu1.itb.misses 2463 # DTB misses -system.cpu1.itb.accesses 28889355 # DTB accesses -system.cpu1.numCycles 4279988156 # number of cpu cycles simulated +system.cpu1.itb.accesses 28889352 # DTB accesses +system.cpu1.numCycles 4277971820 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28410548 # Number of instructions committed -system.cpu1.committedOps 35780226 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31730110 # Number of integer alu accesses +system.cpu1.committedInsts 28410542 # Number of instructions committed +system.cpu1.committedOps 35780270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 31886228 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928835 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3656569 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31730110 # number of integer instructions +system.cpu1.num_func_calls 928836 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3656561 # number of instructions that are conditional controls +system.cpu1.num_int_insts 31886228 # number of integer instructions system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 160619995 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34566633 # number of times the integer registers were written +system.cpu1.num_int_register_reads 163367229 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34722740 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12348580 # number of memory refs -system.cpu1.num_load_insts 7334866 # Number of load instructions -system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 4217686174.280304 # Number of idle cycles -system.cpu1.num_busy_cycles 62301981.719696 # Number of busy cycles +system.cpu1.num_mem_refs 12348595 # number of memory refs +system.cpu1.num_load_insts 7334868 # Number of load instructions +system.cpu1.num_store_insts 5013727 # Number of store instructions +system.cpu1.num_idle_cycles 4215699127.014197 # Number of idle cycles +system.cpu1.num_busy_cycles 62272692.985803 # Number of busy cycles system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 5c3361f47..367b15c5e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -146,13 +149,14 @@ predType=tournament [system.cpu.checker] type=O3Checker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -160,6 +164,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -176,10 +181,35 @@ updateOnError=true warnOnlyOnLoadError=true workload=system.cpu.workload +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -187,32 +217,69 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[7] [system.cpu.checker.isa] type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -220,9 +287,10 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[6] [system.cpu.checker.tracer] type=ExeTracer @@ -263,10 +331,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -274,6 +367,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -628,24 +722,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -653,6 +783,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -701,7 +832,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index dc275e0b8..9a11b77d6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:22 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:05:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second + 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0 + 0: system.cpu.isa: ISA system set to: 0 0x5d826c0 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8e11038e3..783b95f78 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35724 # Simulator instruction rate (inst/s) -host_op_rate 44574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132106037 # Simulator tick rate (ticks/s) -host_mem_usage 247896 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 39940 # Simulator instruction rate (inst/s) +host_op_rate 49834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147693403 # Simulator tick rate (ticks/s) +host_mem_usage 267784 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,27 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -248,6 +269,27 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -273,6 +315,27 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5742 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -294,6 +357,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -366,7 +450,7 @@ system.cpu.rename.ROBFullEvents 2 # Nu system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed @@ -383,7 +467,7 @@ system.cpu.iq.iqNonSpecInstsAdded 49 # Nu system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle @@ -570,7 +654,7 @@ system.cpu.ipc_total 0.135177 # IP system.cpu.int_regfile_reads 39210 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2977 # number of misc regfile reads +system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 9b066fde0..ecd158ad5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 5df86194c..c3c8ec2e1 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:21 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:05:41 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x578c380 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 3ffee0645..20f1d1a3b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34743 # Simulator instruction rate (inst/s) -host_op_rate 43351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128481440 # Simulator tick rate (ticks/s) -host_mem_usage 246872 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 45620 # Simulator instruction rate (inst/s) +host_op_rate 56920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 168691831 # Simulator tick rate (ticks/s) +host_mem_usage 267756 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,27 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -248,6 +269,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -321,7 +363,7 @@ system.cpu.rename.ROBFullEvents 2 # Nu system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed @@ -338,7 +380,7 @@ system.cpu.iq.iqNonSpecInstsAdded 49 # Nu system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle @@ -525,7 +567,7 @@ system.cpu.ipc_total 0.135177 # IP system.cpu.int_regfile_reads 39210 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2977 # number of misc regfile reads +system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1158c75dc..baee5cb0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=checker dtb interrupts isa itb tracer workload +children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=system.cpu.checker clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -79,13 +82,14 @@ icache_port=system.membus.slave[1] [system.cpu.checker] type=DummyChecker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=-1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -93,6 +97,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -109,10 +114,34 @@ updateOnError=false warnOnlyOnLoadError=true workload=system.cpu.workload +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -120,6 +149,7 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -127,24 +157,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -152,6 +217,7 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -159,10 +225,35 @@ sys=system type=ExeTracer eventq_index=0 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -170,6 +261,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -182,24 +274,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -207,6 +335,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -250,7 +379,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 7509c2dae..c5ba01efb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:32 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:13 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second + 0: system.cpu.checker.isa: ISA system set to: 0 0x4499a00 + 0: system.cpu.isa: ISA system set to: 0 0x4499a00 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 4b1e74a91..a171618e9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61907 # Simulator instruction rate (inst/s) -host_op_rate 77238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38693079 # Simulator tick rate (ticks/s) -host_mem_usage 237008 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 147367 # Simulator instruction rate (inst/s) +host_op_rate 183813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92059834 # Simulator tick rate (ticks/s) +host_mem_usage 256900 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9251001568 # Th system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -85,6 +127,27 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +169,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -138,7 +222,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_reads 25360 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 8e0b67b72..02f18b1ff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 618f6d613..380d567ec 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:32 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:03 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5df7a00 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index ea0a0e09c..3aa0b8e66 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81917 # Simulator instruction rate (inst/s) -host_op_rate 102184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51187301 # Simulator tick rate (ticks/s) -host_mem_usage 236980 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 135849 # Simulator instruction rate (inst/s) +host_op_rate 169454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84871687 # Simulator tick rate (ticks/s) +host_mem_usage 256868 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9251001568 # Th system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_reads 25360 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index bae9efedf..b833e8e3a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 6834abec2..16e7e5d49 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:42 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:24 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5fe9040 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 25969000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index a3962cb85..47befeaab 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84539 # Simulator instruction rate (inst/s) -host_op_rate 105013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 480681007 # Simulator tick rate (ticks/s) -host_mem_usage 245716 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 122117 # Simulator instruction rate (inst/s) +host_op_rate 151672 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 694181161 # Simulator tick rate (ticks/s) +host_mem_usage 266760 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 1.3 # La system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28656 # number of times the integer registers were read +system.cpu.num_int_register_reads 28821 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |