diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/quick | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/quick')
11 files changed, 6002 insertions, 5954 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 279bf5056..54bff4f85 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357999000 # Number of ticks simulated -final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869358054000 # Number of ticks simulated +final_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2913867 # Simulator instruction rate (inst/s) -host_op_rate 2913866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83800980413 # Simulator tick rate (ticks/s) -host_mem_usage 338264 # Number of bytes of host memory used -host_seconds 22.31 # Real time elapsed on the host +host_inst_rate 2951277 # Simulator instruction rate (inst/s) +host_op_rate 2951276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84876880961 # Simulator tick rate (ticks/s) +host_mem_usage 336132 # Number of bytes of host memory used +host_seconds 22.02 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory @@ -34,11 +34,11 @@ system.physmem.num_reads::total 1065117 # Nu system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) @@ -46,13 +46,13 @@ system.physmem.bw_write::writebacks 4192823 # Wr system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40658545 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -88,15 +88,15 @@ system.cpu0.itb.data_acv 0 # DT system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 271506704.857374 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 434955692.191892 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3738722793 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3738722903 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -114,12 +114,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -154,7 +154,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed @@ -173,8 +173,8 @@ system.cpu0.num_fp_register_writes 98967 # nu system.cpu0.num_mem_refs 12536107 # number of memory refs system.cpu0.num_load_insts 7783754 # Number of load instructions system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles system.cpu0.Branches 7530826 # Number of branches fetched @@ -217,14 +217,14 @@ system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Cl system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 1781367 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -234,7 +234,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits @@ -291,7 +291,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks system.cpu0.dcache.writebacks::total 633925 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -308,7 +308,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits @@ -375,15 +375,15 @@ system.cpu1.itb.data_acv 0 # DT system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 688459933.247041 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 437290592.854298 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3738296609 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3738296719 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -439,7 +439,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed system.cpu1.committedInsts 15522159 # Number of instructions committed system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed @@ -456,8 +456,8 @@ system.cpu1.num_fp_register_writes 104129 # nu system.cpu1.num_mem_refs 4961786 # number of memory refs system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles system.cpu1.Branches 2214163 # Number of branches fetched @@ -500,14 +500,14 @@ system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Cl system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id @@ -516,7 +516,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits @@ -573,14 +573,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks system.cpu1.dcache.writebacks::total 144832 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor +system.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -589,7 +589,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits @@ -634,7 +634,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7628 # Transaction distribution system.iobus.trans_dist::ReadResp 7628 # Transaction distribution system.iobus.trans_dist::WriteReq 56140 # Transaction distribution @@ -665,7 +665,7 @@ system.iobus.pkt_size_system.bridge.master::total 86162 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -680,7 +680,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -713,18 +713,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 999962 # number of replacements -system.l2c.tags.tagsinuse 65520.418446 # Cycle average of tags in use -system.l2c.tags.total_refs 4560628 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use +system.l2c.tags.total_refs 4560627 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.280391 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 304.654016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4865.757369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58473.870947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1700.964609 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy @@ -738,13 +738,13 @@ system.l2c.tags.age_task_id_blocks_1024::2 2462 # system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46077158 # Number of tag accesses -system.l2c.tags.data_accesses 46077158 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.l2c.tags.tag_accesses 46077150 # Number of tag accesses +system.l2c.tags.data_accesses 46077150 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits @@ -796,8 +796,8 @@ system.l2c.overall_misses::cpu1.data 12080 # nu system.l2c.overall_misses::total 1065509 # number of overall misses system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) @@ -856,12 +856,12 @@ system.l2c.avg_blocked_cycles::no_targets nan # a system.l2c.writebacks::writebacks 80947 # number of writebacks system.l2c.writebacks::total 80947 # number of writebacks system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1068384 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948786 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution @@ -891,24 +891,24 @@ system.membus.pkt_size::total 76119890 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2196431 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000519 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022766 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000560 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2195292 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram +system.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2196431 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018662 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1621 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution @@ -933,25 +933,25 @@ system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1558 system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1000983 # Total snoops (count) -system.toL2Bus.snoopTraffic 5197312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7058665 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106769 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.309069 # Request fanout histogram +system.toL2Bus.snoops 1001076 # Total snoops (count) +system.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6305559 89.33% 89.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752566 10.66% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7058665 # Request fanout histogram -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -983,28 +983,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 5428662b5..50044fb27 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332003500 # Number of ticks simulated -final_tick 1829332003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829332014500 # Number of ticks simulated +final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2961606 # Simulator instruction rate (inst/s) -host_op_rate 2961604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90238056091 # Simulator tick rate (ticks/s) -host_mem_usage 333656 # Number of bytes of host memory used -host_seconds 20.27 # Real time elapsed on the host +host_inst_rate 3082632 # Simulator instruction rate (inst/s) +host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93925630949 # Simulator tick rate (ticks/s) +host_mem_usage 334080 # Number of bytes of host memory used +host_seconds 19.48 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -29,7 +29,7 @@ system.physmem.num_reads::total 1057602 # Nu system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) @@ -38,11 +38,11 @@ system.physmem.bw_write::writebacks 4053799 # Wr system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -78,15 +78,15 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12714 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 283043477.146767 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 441371906.848107 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3658670365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3658670387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -102,11 +102,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929137500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331796000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -141,7 +141,7 @@ system.cpu.kern.mode_switch_good::idle 0.081545 # fr system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033409500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.committedInsts 60038469 # Number of instructions committed system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed @@ -158,8 +158,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115703 # number of memory refs system.cpu.num_load_insts 9747509 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621022.088898 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911102 # Number of busy cycles +system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles system.cpu.Branches 9064428 # Number of branches fetched @@ -202,12 +202,12 @@ system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Cl system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 60050307 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2042707 # number of replacements +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2042708 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -217,31 +217,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7807772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807772 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits -system.cpu.dcache.overall_hits::total 13655981 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721711 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721711 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits +system.cpu.dcache.overall_hits::total 13655980 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses +system.cpu.dcache.overall_misses::total 2026075 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) @@ -272,12 +272,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks system.cpu.dcache.writebacks::total 833476 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 919606 # number of replacements +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130074 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920118 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263577 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy @@ -287,21 +287,21 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970540 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970540 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59130074 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130074 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130074 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130074 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130074 # number of overall hits -system.cpu.icache.overall_hits::total 59130074 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920233 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920233 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920233 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920233 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920233 # number of overall misses -system.cpu.icache.overall_misses::total 920233 # number of overall misses +system.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970539 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits +system.cpu.icache.overall_hits::total 59130075 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses +system.cpu.icache.overall_misses::total 920232 # number of overall misses system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses @@ -320,18 +320,18 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 919606 # number of writebacks -system.cpu.icache.writebacks::total 919606 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 919605 # number of writebacks +system.cpu.icache.writebacks::total 919605 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 992419 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65520.104765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732213 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy @@ -345,24 +345,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919354 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919354 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811229 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811229 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906926 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998522 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906926 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998522 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses @@ -380,21 +380,21 @@ system.cpu.l2cache.overall_misses::cpu.data 1044698 # system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919354 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919354 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses @@ -419,44 +419,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks system.cpu.l2cache.writebacks::total 74359 # number of writebacks system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962435 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1209231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738873 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154670 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301904366 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 993364 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4774656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6936011 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000753 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.027431 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 993442 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6930788 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5223 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6936011 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -469,7 +469,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7358 # Transaction distribution system.iobus.trans_dist::ReadResp 7358 # Transaction distribution system.iobus.trans_dist::WriteReq 51390 # Transaction distribution @@ -500,14 +500,14 @@ system.iobus.pkt_size_system.bridge.master::total 46126 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -515,7 +515,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375534 # Number of tag accesses system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -549,12 +549,12 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1034179 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7184 # Transaction distribution system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution @@ -583,21 +583,21 @@ system.membus.pkt_size::total 75175918 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2149798 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000494 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022210 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2148737 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1061 0.05% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram +system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2149798 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -629,28 +629,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 66d295a56..5f20e9468 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.966742 # Number of seconds simulated -sim_ticks 1966741627000 # Number of ticks simulated -final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1966742176000 # Number of ticks simulated +final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1661877 # Simulator instruction rate (inst/s) -host_op_rate 1661877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53617278530 # Simulator tick rate (ticks/s) -host_mem_usage 335968 # Number of bytes of host memory used -host_seconds 36.68 # Real time elapsed on the host -sim_insts 60959478 # Number of instructions simulated -sim_ops 60959478 # Number of ops (including micro ops) simulated +host_inst_rate 1742915 # Simulator instruction rate (inst/s) +host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56229643103 # Simulator tick rate (ticks/s) +host_mem_usage 335876 # Number of bytes of host memory used +host_seconds 34.98 # Real time elapsed on the host +sim_insts 60961842 # Number of instructions simulated +sim_ops 60961842 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory -system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408131 # Number of read requests accepted -system.physmem.writeReqs 121489 # Number of write requests accepted -system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408118 # Number of read requests accepted +system.physmem.writeReqs 121475 # Number of write requests accepted +system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side +system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write @@ -73,12 +73,12 @@ system.physmem.perBankRdBursts::6 26012 # Pe system.physmem.perBankRdBursts::7 25110 # Per bank write bursts system.physmem.perBankRdBursts::8 25002 # Per bank write bursts system.physmem.perBankRdBursts::9 25326 # Per bank write bursts -system.physmem.perBankRdBursts::10 25348 # Per bank write bursts +system.physmem.perBankRdBursts::10 25349 # Per bank write bursts system.physmem.perBankRdBursts::11 25350 # Per bank write bursts -system.physmem.perBankRdBursts::12 25736 # Per bank write bursts -system.physmem.perBankRdBursts::13 25396 # Per bank write bursts +system.physmem.perBankRdBursts::12 25737 # Per bank write bursts +system.physmem.perBankRdBursts::13 25386 # Per bank write bursts system.physmem.perBankRdBursts::14 25673 # Per bank write bursts -system.physmem.perBankRdBursts::15 25838 # Per bank write bursts +system.physmem.perBankRdBursts::15 25833 # Per bank write bursts system.physmem.perBankWrBursts::0 7888 # Per bank write bursts system.physmem.perBankWrBursts::1 7973 # Per bank write bursts system.physmem.perBankWrBursts::2 7891 # Per bank write bursts @@ -89,30 +89,30 @@ system.physmem.perBankWrBursts::6 8079 # Pe system.physmem.perBankWrBursts::7 7030 # Per bank write bursts system.physmem.perBankWrBursts::8 7056 # Per bank write bursts system.physmem.perBankWrBursts::9 7058 # Per bank write bursts -system.physmem.perBankWrBursts::10 7243 # Per bank write bursts +system.physmem.perBankWrBursts::10 7244 # Per bank write bursts system.physmem.perBankWrBursts::11 7671 # Per bank write bursts system.physmem.perBankWrBursts::12 7657 # Per bank write bursts -system.physmem.perBankWrBursts::13 7555 # Per bank write bursts +system.physmem.perBankWrBursts::13 7545 # Per bank write bursts system.physmem.perBankWrBursts::14 7813 # Per bank write bursts -system.physmem.perBankWrBursts::15 7948 # Per bank write bursts +system.physmem.perBankWrBursts::15 7943 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 1966734334500 # Total gap between requests +system.physmem.totGap 1966734882500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408131 # Read request sizes (log2) +system.physmem.readPktSize::6 408118 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121489 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121475 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -159,118 +159,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads -system.physmem.totQLat 6252046750 # Total ticks spent queuing -system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads +system.physmem.totQLat 6253232750 # Total ticks spent queuing +system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s @@ -280,74 +280,74 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing -system.physmem.readRowHits 365911 # Number of row buffer hits during reads +system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing +system.physmem.readRowHits 365871 # Number of row buffer hits during reads system.physmem.writeRowHits 97586 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 3713482.00 # Average gap between requests +system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes +system.physmem.avgGap 3713672.35 # Average gap between requests system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.237247 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states -system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.444709 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.241923 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states +system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.452256 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7479115 # DTB read hits +system.cpu0.dtb.read_hits 7479524 # DTB read hits system.cpu0.dtb.read_misses 7764 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524068 # DTB read accesses -system.cpu0.dtb.write_hits 5079820 # DTB write hits +system.cpu0.dtb.write_hits 5079926 # DTB write hits system.cpu0.dtb.write_misses 909 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202594 # DTB write accesses -system.cpu0.dtb.data_hits 12558935 # DTB hits +system.cpu0.dtb.data_hits 12559450 # DTB hits system.cpu0.dtb.data_misses 8673 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726662 # DTB accesses -system.cpu0.itb.fetch_hits 3638634 # ITB hits +system.cpu0.itb.fetch_hits 3638587 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3642618 # ITB accesses +system.cpu0.itb.fetch_accesses 3642571 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -360,55 +360,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3933483254 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3933484352 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed @@ -417,247 +417,247 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.66% # nu system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148125 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches +system.cpu0.kern.callpal::total 148123 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3065 # number of times the context was actually changed -system.cpu0.committedInsts 47690735 # Number of instructions committed -system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses -system.cpu0.num_func_calls 1190980 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44243506 # number of integer instructions -system.cpu0.num_fp_insts 210072 # number of float instructions -system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599733 # number of memory refs -system.cpu0.num_load_insts 7506744 # Number of load instructions -system.cpu0.num_store_insts 5092989 # Number of store instructions -system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles -system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles -system.cpu0.Branches 7182999 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction -system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction -system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction +system.cpu0.kern.swap_context 3064 # number of times the context was actually changed +system.cpu0.committedInsts 47693300 # Number of instructions committed +system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses +system.cpu0.num_func_calls 1191022 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44245928 # number of integer instructions +system.cpu0.num_fp_insts 210005 # number of float instructions +system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written +system.cpu0.num_mem_refs 12600240 # number of memory refs +system.cpu0.num_load_insts 7507148 # Number of load instructions +system.cpu0.num_store_insts 5093092 # Number of store instructions +system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles +system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles +system.cpu0.Branches 7183589 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction +system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction +system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction +system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47699751 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1183172 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. +system.cpu0.op_class::total 47702316 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1183155 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses -system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses +system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks -system.cpu0.dcache.writebacks::total 681271 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks +system.cpu0.dcache.writebacks::total 681263 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 692001 # number of replacements +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 692168 # number of replacements system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy @@ -667,97 +667,97 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits -system.cpu0.icache.overall_hits::total 47007113 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses -system.cpu0.icache.overall_misses::total 692639 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits +system.cpu0.icache.overall_hits::total 47009511 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses +system.cpu0.icache.overall_misses::total 692806 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks -system.cpu0.icache.writebacks::total 692001 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks +system.cpu0.icache.writebacks::total 692168 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2442522 # DTB read hits +system.cpu1.dtb.read_hits 2442461 # DTB read hits system.cpu1.dtb.read_misses 2621 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205338 # DTB read accesses -system.cpu1.dtb.write_hits 1749235 # DTB write hits +system.cpu1.dtb.write_hits 1749247 # DTB write hits system.cpu1.dtb.write_misses 236 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89740 # DTB write accesses -system.cpu1.dtb.data_hits 4191757 # DTB hits +system.cpu1.dtb.data_hits 4191708 # DTB hits system.cpu1.dtb.data_misses 2857 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295078 # DTB accesses -system.cpu1.itb.fetch_hits 1826928 # ITB hits +system.cpu1.itb.fetch_hits 1826964 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1827992 # ITB accesses +system.cpu1.itb.fetch_accesses 1828028 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,40 +772,40 @@ system.cpu1.itb.data_acv 0 # DT system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3931646339 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3931646343 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed @@ -813,7 +813,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed @@ -822,7 +822,7 @@ system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73259 # number of callpals executed +system.cpu1.kern.callpal::total 73263 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches @@ -833,236 +833,236 @@ system.cpu1.kern.mode_switch_good::kernel 0.415479 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2017 # number of times the context was actually changed -system.cpu1.committedInsts 13268743 # Number of instructions committed -system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses +system.cpu1.committedInsts 13268542 # Number of instructions committed +system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses -system.cpu1.num_func_calls 423393 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12224543 # number of integer instructions +system.cpu1.num_func_calls 423403 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12224320 # number of integer instructions system.cpu1.num_fp_insts 175144 # number of float instructions -system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written -system.cpu1.num_mem_refs 4214824 # number of memory refs -system.cpu1.num_load_insts 2456352 # Number of load instructions -system.cpu1.num_store_insts 1758472 # Number of store instructions -system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles -system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles -system.cpu1.Branches 1899015 # Number of branches fetched -system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction -system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction -system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction +system.cpu1.num_mem_refs 4214775 # number of memory refs +system.cpu1.num_load_insts 2456291 # Number of load instructions +system.cpu1.num_store_insts 1758484 # Number of store instructions +system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles +system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles +system.cpu1.Branches 1898911 # Number of branches fetched +system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction +system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction +system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction +system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13271624 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 162095 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor +system.cpu1.op_class::total 13271423 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 162127 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits -system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses -system.cpu1.dcache.overall_misses::total 177419 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits +system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses +system.cpu1.dcache.overall_misses::total 177481 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # 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average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks -system.cpu1.dcache.writebacks::total 111600 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # 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number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # 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number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 326538 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 326560 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -1070,77 +1070,77 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12944535 # 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miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits +system.cpu1.icache.overall_hits::total 12944312 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses +system.cpu1.icache.overall_misses::total 327111 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks -system.cpu1.icache.writebacks::total 326538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks +system.cpu1.icache.writebacks::total 326560 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1153,7 +1153,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7376 # Transaction distribution system.iobus.trans_dist::ReadResp 7376 # Transaction distribution system.iobus.trans_dist::WriteReq 55675 # Transaction distribution @@ -1186,7 +1186,7 @@ system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1202,28 +1202,28 @@ system.iobus.reqLayer25.occupancy 6051000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375570 # Number of tag accesses system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1234,12 +1234,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1258,12 +1258,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked @@ -1282,12 +1282,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1298,29 +1298,29 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 342937 # number of replacements -system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use -system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 342924 # number of replacements +system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use +system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002546 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292654 # Transaction distribution +system.membus.trans_dist::ReadResp 292655 # Transaction distribution system.membus.trans_dist::WriteReq 14123 # Transaction distribution system.membus.trans_dist::WriteResp 14123 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution -system.membus.trans_dist::CleanEvict 262335 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution +system.membus.trans_dist::CleanEvict 262336 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123969 # Transaction distribution -system.membus.trans_dist::ReadExResp 123101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution +system.membus.trans_dist::ReadExReq 123955 # Transaction distribution +system.membus.trans_dist::ReadExResp 123087 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 148 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22774 # Total snoops (count) +system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22923 # Total snoops (count) system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 493929 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram +system.membus.snoop_fanout::samples 493917 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 493929 # Request fanout histogram -system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 493917 # Request fanout histogram +system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 403246 # Total snoops (count) -system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 403271 # Total snoops (count) +system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1753,28 +1755,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index c56df0bbe..0bead1a4b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.926421 # Number of seconds simulated -sim_ticks 1926421414000 # Number of ticks simulated -final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.926422 # Number of seconds simulated +sim_ticks 1926421638000 # Number of ticks simulated +final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834051 # Simulator instruction rate (inst/s) -host_op_rate 834051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28592100047 # Simulator tick rate (ticks/s) -host_mem_usage 333408 # Number of bytes of host memory used -host_seconds 67.38 # Real time elapsed on the host +host_inst_rate 1739419 # Simulator instruction rate (inst/s) +host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59628989604 # Simulator tick rate (ticks/s) +host_mem_usage 334072 # Number of bytes of host memory used +host_seconds 32.31 # Real time elapsed on the host sim_insts 56195014 # Number of instructions simulated sim_ops 56195014 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -29,18 +29,18 @@ system.physmem.num_reads::total 401602 # Nu system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 401602 # Number of read requests accepted system.physmem.writeReqs 115765 # Number of write requests accepted system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue @@ -87,7 +87,7 @@ system.physmem.perBankWrBursts::14 7864 # Pe system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1926409540500 # Total gap between requests +system.physmem.totGap 1926409764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -150,68 +150,68 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes @@ -222,29 +222,29 @@ system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads @@ -252,12 +252,12 @@ system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Wr system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads -system.physmem.totQLat 6110965000 # Total ticks spent queuing -system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6110922250 # Total ticks spent queuing +system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s @@ -268,52 +268,52 @@ system.physmem.busUtilRead 0.10 # Da system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 360227 # Number of row buffer hits during reads +system.physmem.readRowHits 360225 # Number of row buffer hits during reads system.physmem.writeRowHits 93542 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3723487.47 # Average gap between requests +system.physmem.avgGap 3723487.90 # Average gap between requests system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.200016 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states +system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.199922 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states -system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states +system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.542936 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states +system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.543123 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -349,16 +349,16 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12758 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3852842828 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3852843276 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -374,11 +374,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -411,9 +411,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323061 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.committedInsts 56195014 # Number of instructions committed system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed @@ -430,8 +430,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 15476659 # number of memory refs system.cpu.num_load_insts 9103400 # Number of load instructions system.cpu.num_store_insts 6373259 # Number of store instructions -system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles -system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles +system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles +system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles system.cpu.idle_fraction 0.930908 # Percentage of idle cycles system.cpu.Branches 8424278 # Number of branches fetched @@ -474,12 +474,12 @@ system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Cl system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 56206855 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390811 # number of replacements +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1390804 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy @@ -489,41 +489,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits -system.cpu.dcache.overall_hits::total 13669475 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses -system.cpu.dcache.overall_misses::total 1374062 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles +system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits +system.cpu.dcache.overall_hits::total 13669481 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses +system.cpu.dcache.overall_misses::total 1374056 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) @@ -536,96 +536,96 @@ system.cpu.dcache.demand_accesses::cpu.data 15043537 # system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks -system.cpu.dcache.writebacks::total 835205 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks +system.cpu.dcache.writebacks::total 835203 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049419 # 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mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # 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number of replacements -system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks. +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 928685 # number of replacements +system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -634,27 +634,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 55277502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277502 # number of overall hits -system.cpu.icache.overall_hits::total 55277502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929354 # number of overall misses -system.cpu.icache.overall_misses::total 929354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13309679000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13309679000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13309679000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13309679000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13309679000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13309679000 # number of overall miss cycles +system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits +system.cpu.icache.overall_hits::total 55277500 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses +system.cpu.icache.overall_misses::total 929356 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses @@ -667,54 +667,54 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # 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number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928683 # number of writebacks -system.cpu.icache.writebacks::total 928683 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # 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average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 336397 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65387.710851 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy @@ -725,27 +725,27 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # 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number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,101 +850,102 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336953 # Total snoops (count) +system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 336955 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -958,7 +959,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51204 # Transaction distribution @@ -989,7 +990,7 @@ system.iobus.pkt_size_system.bridge.master::total 44580 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1007,28 +1008,28 @@ system.iobus.reqLayer25.occupancy 6041500 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1039,12 +1040,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1063,12 +1064,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -1087,12 +1088,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1103,19 +1104,19 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292275 # Transaction distribution system.membus.trans_dist::WriteReq 9652 # Transaction distribution @@ -1128,6 +1129,7 @@ system.membus.trans_dist::ReadExReq 116686 # Tr system.membus.trans_dist::ReadExResp 116686 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) @@ -1140,32 +1142,32 @@ system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 431 # Total snoops (count) +system.membus.snoops 555 # Total snoops (count) system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 460301 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 460301 # Request fanout histogram -system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1197,28 +1199,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 812c8a1b2..13365cb29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,71 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802883274000 # Number of ticks simulated -final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802884 # Number of seconds simulated +sim_ticks 2802884446000 # Number of ticks simulated +final_tick 2802884446000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1537557 # Simulator instruction rate (inst/s) -host_op_rate 1873488 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29353729253 # Simulator tick rate (ticks/s) -host_mem_usage 598048 # Number of bytes of host memory used -host_seconds 95.49 # Real time elapsed on the host -sim_insts 146815798 # Number of instructions simulated -sim_ops 178892721 # Number of ops (including micro ops) simulated +host_inst_rate 1499640 # Simulator instruction rate (inst/s) +host_op_rate 1827287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28629719673 # Simulator tick rate (ticks/s) +host_mem_usage 593616 # Number of bytes of host memory used +host_seconds 97.90 # Real time elapsed on the host +sim_insts 146816546 # Number of instructions simulated +sim_ops 178893643 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1163300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9541412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 165332 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1112336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1163556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9541156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 165076 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1111568 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11983980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1163300 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 165332 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11983020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1163556 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 165076 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8870080 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8871872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8887644 # Number of bytes written to this memory +system.physmem.bytes_written::total 8889436 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 149604 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2738 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 17400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 149600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 17388 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 196397 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138595 # Number of write requests responded to by this memory +system.physmem.num_reads::total 196382 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138623 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142986 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143014 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 415037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3404142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 58986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 396854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 415128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3404049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 58895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 396580 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4275590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 415037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 58986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4275246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 415128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 58895 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3164627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3165265 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3170893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3164627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3171531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3165265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 415037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3410394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 58986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 396868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 415128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3410301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 58895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 396594 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7446483 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7446777 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -84,9 +88,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -94,7 +98,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,7 +128,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 7964 # Table walker walks requested system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency @@ -145,9 +149,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20338226 # DTB read hits +system.cpu0.dtb.read_hits 20338335 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16389726 # DTB write hits +system.cpu0.dtb.write_hits 16389802 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -158,13 +162,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20345097 # DTB read accesses -system.cpu0.dtb.write_accesses 16390819 # DTB write accesses +system.cpu0.dtb.read_accesses 20345206 # DTB read accesses +system.cpu0.dtb.write_accesses 16390895 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36727952 # DTB hits +system.cpu0.dtb.hits 36728137 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36735916 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.accesses 36736101 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -194,7 +198,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3358 # Table walker walks requested system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency @@ -213,7 +217,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97433318 # ITB inst hits +system.cpu0.itb.inst_hits 97433825 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -230,54 +234,54 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97436676 # ITB inst accesses -system.cpu0.itb.hits 97433318 # DTB hits +system.cpu0.itb.inst_accesses 97437183 # ITB inst accesses +system.cpu0.itb.hits 97433825 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97436676 # DTB accesses -system.cpu0.numPwrStateTransitions 3946 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 97437183 # DTB accesses +system.cpu0.numPwrStateTransitions 3948 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1974 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1390119373.406788 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23077022550.794018 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1158 58.66% 58.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.03% 99.70% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5605768522 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 1974 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 58788802895 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744095643105 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5605770867 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed -system.cpu0.committedInsts 95420875 # Number of instructions committed -system.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1974 # number of quiesce instructions executed +system.cpu0.committedInsts 95421368 # Number of instructions committed +system.cpu0.committedOps 115553536 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100756492 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000037 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100755950 # number of integer instructions +system.cpu0.num_func_calls 8000109 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13203633 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100756492 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182435981 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69130832 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written -system.cpu0.num_mem_refs 37870790 # number of memory refs -system.cpu0.num_load_insts 20595754 # Number of load instructions -system.cpu0.num_store_insts 17275036 # Number of store instructions -system.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles -system.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles +system.cpu0.num_cc_register_reads 349950831 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44904973 # number of times the CC registers were written +system.cpu0.num_mem_refs 37870982 # number of memory refs +system.cpu0.num_load_insts 20595866 # Number of load instructions +system.cpu0.num_store_insts 17275116 # Number of store instructions +system.cpu0.num_idle_cycles 5488193219.783614 # Number of idle cycles +system.cpu0.num_busy_cycles 117577647.216386 # Number of busy cycles system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles -system.cpu0.Branches 21940702 # Number of branches fetched +system.cpu0.Branches 21940830 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction -system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78883265 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110622 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -307,21 +311,21 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20593498 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17267541 14.77% 99.99% # Class of executed instruction +system.cpu0.op_class::MemRead 20593610 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17267621 14.77% 99.99% # Class of executed instruction system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116874608 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 693483 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. +system.cpu0.op_class::total 116875229 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 693487 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.728118 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35929711 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693999 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.771992 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728118 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -329,51 +333,51 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15689072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15689072 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363048 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363048 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34796160 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34796160 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35142202 # number of overall hits -system.cpu0.dcache.overall_hits::total 35142202 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295787 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295787 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.tags.tag_accesses 74108594 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74108594 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 19107187 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19107187 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15689146 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15689146 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346045 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346045 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379608 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379608 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34796333 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34796333 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35142378 # number of overall hits +system.cpu0.dcache.overall_hits::total 35142378 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373137 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373137 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295785 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295785 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100323 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100323 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18411 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18422 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18422 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769244 # number of overall misses -system.cpu0.dcache.overall_misses::total 769244 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses +system.cpu0.dcache.overall_misses::cpu0.data 769245 # number of overall misses +system.cpu0.dcache.overall_misses::total 769245 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480324 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19480324 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15984931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446368 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446368 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386349 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386349 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381463 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381463 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35465255 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35465255 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35911623 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35911623 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses @@ -382,8 +386,8 @@ system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048265 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048265 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048293 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048293 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses @@ -394,14 +398,14 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks -system.cpu0.dcache.writebacks::total 693483 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1109362 # number of replacements +system.cpu0.dcache.writebacks::writebacks 693487 # number of writebacks +system.cpu0.dcache.writebacks::total 693487 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1109393 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96326253 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1109905 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.787836 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -411,27 +415,27 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits -system.cpu0.icache.overall_hits::total 96325777 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses -system.cpu0.icache.overall_misses::total 1109883 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195982248 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195982248 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 96326253 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96326253 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96326253 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96326253 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96326253 # number of overall hits +system.cpu0.icache.overall_hits::total 96326253 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1109914 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1109914 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1109914 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1109914 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1109914 # number of overall misses +system.cpu0.icache.overall_misses::total 1109914 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436167 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97436167 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97436167 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97436167 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97436167 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97436167 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses @@ -444,192 +448,191 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks -system.cpu0.icache.writebacks::total 1109362 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 1109393 # number of writebacks +system.cpu0.icache.writebacks::total 1109393 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 244755 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15690.306286 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1516961 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 260398 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.825548 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 245116 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15690.277500 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1517282 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 260748 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.818959 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.001822 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.238695 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065768 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.004723 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.222065 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.050711 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000137 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.957660 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15637 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 527 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 887 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7822 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60864487 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60864487 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10088 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4467 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14555 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510065 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510065 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1264919 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1264919 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94269 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94269 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1050188 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1050188 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344415 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 344415 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10088 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4467 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1050188 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 438684 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1503427 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10088 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4467 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1050188 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 438684 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1503427 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 414 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26265 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26265 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18411 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18411 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175253 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175253 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59695 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 59695 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135783 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 135783 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 59695 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 311036 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 371145 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 59695 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 311036 # number of overall misses -system.cpu0.l2cache.overall_misses::total 371145 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10362 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4607 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14969 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510065 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510065 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264919 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1264919 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26265 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26265 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18411 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18411 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10362 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4607 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874572 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10362 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4607 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874572 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030389 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.027657 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000136 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.957659 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15629 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 528 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 881 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7801 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5151 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1268 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.953918 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 60866660 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 60866660 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10118 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4491 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14609 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 509920 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 509920 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265098 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265098 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94164 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94164 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1049983 # 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number of overall hits +system.cpu0.l2cache.overall_hits::total 1503209 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 266 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 132 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 398 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26262 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26262 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18422 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18422 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175359 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175359 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59931 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 59931 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135748 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 135748 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 266 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 132 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 59931 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 311107 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 371436 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 266 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 132 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 59931 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 311107 # number of overall misses +system.cpu0.l2cache.overall_misses::total 371436 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10384 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4623 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15007 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 509920 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 509920 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265098 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265098 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26262 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26262 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18422 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18422 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109914 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1109914 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480201 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480201 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10384 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4623 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1109914 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749724 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874645 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10384 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4623 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1109914 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749724 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1874645 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028553 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.026521 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650236 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650236 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053785 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053785 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282765 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282765 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030389 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053785 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414870 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.197989 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030389 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053785 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414870 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.197989 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650627 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650627 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053996 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053996 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282690 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282690 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028553 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053996 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414962 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.198137 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028553 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053996 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414962 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.198137 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 192868 # number of writebacks -system.cpu0.l2cache.writebacks::total 192868 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 3719490 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859911 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 111560 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109856 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1704 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.writebacks::writebacks 192903 # number of writebacks +system.cpu0.l2cache.writebacks::total 192903 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 3719568 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859945 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 111615 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109909 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1706 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651525 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1292780 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18411 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44676 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402107 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::WritebackDirty 509920 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292960 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26262 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18422 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109914 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480201 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347265 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402135 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5790903 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791024 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142071736 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92556032 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 530280 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 12377344 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 4224545 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.042934 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.204688 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 234711016 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 530821 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 12390272 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 4225152 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.042946 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.204717 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4044873 95.75% 95.75% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 177968 4.21% 99.96% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1704 0.04% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4045406 95.75% 95.75% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 178040 4.21% 99.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1706 0.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4224545 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 4225152 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -659,7 +662,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 3359 # Table walker walks requested system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency @@ -680,9 +683,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12172373 # DTB read hits +system.cpu1.dtb.read_hits 12172433 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7586083 # DTB write hits +system.cpu1.dtb.write_hits 7586113 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -693,13 +696,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12175226 # DTB read accesses -system.cpu1.dtb.write_accesses 7586589 # DTB write accesses +system.cpu1.dtb.read_accesses 12175286 # DTB read accesses +system.cpu1.dtb.write_accesses 7586619 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19758456 # DTB hits +system.cpu1.dtb.hits 19758546 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19761815 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.accesses 19761905 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -729,7 +732,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1734 # Table walker walks requested system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency @@ -748,7 +751,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53665127 # ITB inst hits +system.cpu1.itb.inst_hits 53665397 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -765,14 +768,14 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53666861 # ITB inst accesses -system.cpu1.itb.hits 53665127 # DTB hits +system.cpu1.itb.inst_accesses 53667131 # ITB inst accesses +system.cpu1.itb.hits 53665397 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53666861 # DTB accesses +system.cpu1.itb.accesses 53667131 # DTB accesses system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1013196310.731163 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25944771747.523987 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state @@ -782,37 +785,37 @@ system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00 system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5605297416 # number of cpu cycles simulated +system.cpu1.pwrStateResidencyTicks::ON 32805732461 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770078713539 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5605299760 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed -system.cpu1.committedInsts 51394923 # Number of instructions committed -system.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses +system.cpu1.committedInsts 51395178 # Number of instructions committed +system.cpu1.committedOps 63340107 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56977448 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170267 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56977163 # number of integer instructions +system.cpu1.num_func_calls 9170327 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5966466 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56977448 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110657896 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41293618 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written -system.cpu1.num_mem_refs 20023552 # number of memory refs -system.cpu1.num_load_insts 12287954 # Number of load instructions -system.cpu1.num_store_insts 7735598 # Number of store instructions -system.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles -system.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles +system.cpu1.num_cc_register_reads 196245989 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18891972 # number of times the CC registers were written +system.cpu1.num_mem_refs 20023642 # number of memory refs +system.cpu1.num_load_insts 12288014 # Number of load instructions +system.cpu1.num_store_insts 7735628 # Number of store instructions +system.cpu1.num_idle_cycles 5539693785.928316 # Number of idle cycles +system.cpu1.num_busy_cycles 65605974.071684 # Number of busy cycles system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles -system.cpu1.Branches 15216243 # Number of branches fetched +system.cpu1.Branches 15216333 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45396557 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -843,82 +846,82 @@ system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12287438 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7734322 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12287498 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7734352 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65451587 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 191903 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. +system.cpu1.op_class::total 65451917 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 191899 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.757768 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19500995 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192253 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.434022 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757768 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7396381 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7396381 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39746768 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39746768 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 11857290 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11857290 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7396404 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7396404 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72441 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72441 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19253609 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19253609 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19303712 # number of overall hits -system.cpu1.dcache.overall_hits::total 19303712 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92475 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92475 # number of WriteReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72438 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19253694 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19253694 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19303797 # number of overall hits +system.cpu1.dcache.overall_hits::total 19303797 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136572 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136572 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92482 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92482 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22520 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22520 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229049 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229049 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259766 # number of overall misses -system.cpu1.dcache.overall_misses::total 259766 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22523 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22523 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229054 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229054 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259771 # number of overall misses +system.cpu1.dcache.overall_misses::total 259771 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993862 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11993862 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488886 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7488886 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19482748 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19482748 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19563568 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19563568 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012349 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012349 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237150 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237150 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237182 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses @@ -929,43 +932,43 @@ system.cpu1.dcache.blocked::no_mshrs 0 # nu system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks -system.cpu1.dcache.writebacks::total 191903 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 523286 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. +system.cpu1.dcache.writebacks::writebacks 191899 # number of writebacks +system.cpu1.dcache.writebacks::total 191899 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 523278 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.709352 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53142697 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523790 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.458021 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709352 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits -system.cpu1.icache.overall_hits::total 53142419 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses -system.cpu1.icache.overall_misses::total 523798 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses +system.cpu1.icache.tags.tag_accesses 107856764 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107856764 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 53142697 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53142697 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53142697 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53142697 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53142697 # number of overall hits +system.cpu1.icache.overall_hits::total 53142697 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523790 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523790 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523790 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523790 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523790 # number of overall misses +system.cpu1.icache.overall_misses::total 523790 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666487 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53666487 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53666487 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53666487 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53666487 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53666487 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses @@ -978,190 +981,190 @@ system.cpu1.icache.blocked::no_mshrs 0 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 523286 # number of writebacks -system.cpu1.icache.writebacks::total 523286 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 523278 # number of writebacks +system.cpu1.icache.writebacks::total 523278 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 45747 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14812.613567 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 613917 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 60319 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.177838 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 45622 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14812.583642 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 612745 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 60182 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.181533 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.372104 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.216207 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.025256 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.903831 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.904090 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.341040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.229622 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.012979 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.903829 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.904088 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14538 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1590 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8844 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4115 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 25046952 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 25046952 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1892 # number of ReadReq hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1592 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8923 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4023 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887329 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 25046700 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 25046700 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3523 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1897 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 120650 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 120650 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583378 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583378 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19790 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19790 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502408 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 502408 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97451 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 97451 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1892 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 502408 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 117241 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 625069 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1892 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 502408 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 117241 # number of overall hits -system.cpu1.l2cache.overall_hits::total 625069 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 299 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 735 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28860 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28860 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22520 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22520 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43825 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43825 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21390 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 21390 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75158 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 75158 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 299 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 21390 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 118983 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 141108 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 299 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 21390 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 118983 # number of overall misses -system.cpu1.l2cache.overall_misses::total 141108 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3964 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_hits::writebacks 120664 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 120664 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583352 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583352 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19842 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19842 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502374 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 502374 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97505 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 97505 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3523 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1897 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 502374 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 117347 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 625141 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3523 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1897 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 502374 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 117347 # number of overall hits +system.cpu1.l2cache.overall_hits::total 625141 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 442 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 736 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28867 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28867 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22523 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22523 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43773 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43773 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21416 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 21416 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75102 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 75102 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 442 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 21416 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 118875 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 141027 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 442 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 21416 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 118875 # number of overall misses +system.cpu1.l2cache.overall_misses::total 141027 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6155 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120650 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 120650 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583378 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583378 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28860 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28860 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22520 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22520 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120664 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 120664 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583352 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583352 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22523 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22523 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3964 # number of demand (read+write) accesses +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523790 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 523790 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172607 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 172607 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 766177 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3964 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 523790 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 236222 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766168 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766177 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136467 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.119415 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523790 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236222 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 766168 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134185 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.119558 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688910 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688910 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040836 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040836 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435423 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435423 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136467 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040836 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503687 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.184172 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136467 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040836 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503687 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.184172 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688092 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688092 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040887 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040887 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435104 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435104 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134185 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040887 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503234 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.184068 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134185 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040887 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503234 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.184068 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 32289 # number of writebacks -system.cpu1.l2cache.writebacks::total 32289 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533143 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773124 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 32251 # number of writebacks +system.cpu1.l2cache.writebacks::total 32251 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533131 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 97275 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6697 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.snoop_filter.tot_snoops 97486 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90800 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6686 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709146 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 120650 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 594539 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28860 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 120664 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594513 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22523 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51390 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778567 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523790 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172607 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571212 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778579 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2368499 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2368487 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67013060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27418918 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 295837 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 2333632 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1767980 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.075142 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.277617 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 94469370 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 297967 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 2396032 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1770091 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.075165 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.277614 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1641828 92.86% 92.86% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 119455 6.76% 99.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 6697 0.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1643728 92.86% 92.86% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 119677 6.76% 99.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 6686 0.38% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1767980 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.snoop_fanout::total 1770091 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1212,14 +1215,14 @@ system.iobus.pkt_size_system.bridge.master::total 162766 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586087 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 14.586087 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1227,7 +1230,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1260,249 +1263,259 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 135163 # number of replacements -system.l2c.tags.tagsinuse 65177.726515 # Cycle average of tags in use -system.l2c.tags.total_refs 431584 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200605 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.151412 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 135222 # number of replacements +system.l2c.tags.tagsinuse 65177.722092 # Cycle average of tags in use +system.l2c.tags.total_refs 431767 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200667 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.151659 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6643.934415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 6644.063591 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032741 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7087.737158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 43017.411906 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1645.646531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6779.026349 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.101378 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7087.775672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 43017.281235 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1645.603615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6779.025879 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.101380 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.108150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.656394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025111 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.108151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.656392 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025110 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65436 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # 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number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 3254 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13449 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 779 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1161 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1940 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13430 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3004 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16434 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 116 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 70 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 42080 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 82797 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 24 # 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number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits -system.l2c.overall_hits::cpu0.inst 42080 # number of overall hits -system.l2c.overall_hits::cpu0.data 96227 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 24 # number of overall hits -system.l2c.overall_hits::cpu1.inst 18817 # number of overall hits -system.l2c.overall_hits::cpu1.data 15982 # number of overall hits -system.l2c.overall_hits::total 173352 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 275 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 112 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 387 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 30 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 26 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 56 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 137059 # 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number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 96 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 62 # number of overall hits +system.l2c.overall_hits::cpu0.inst 42312 # number of overall hits +system.l2c.overall_hits::cpu0.data 96260 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits +system.l2c.overall_hits::cpu1.inst 18847 # number of overall hits +system.l2c.overall_hits::cpu1.data 15925 # number of overall hits +system.l2c.overall_hits::total 173559 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 280 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 93 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 373 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 37 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 72 # 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number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2569 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 17369 # number of demand (read+write) misses +system.l2c.demand_misses::total 186904 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17615 # number of overall misses -system.l2c.overall_misses::cpu0.data 149337 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2573 # number of overall misses -system.l2c.overall_misses::cpu1.data 17383 # number of overall misses -system.l2c.overall_misses::total 186918 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 225157 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 225157 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10470 # 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number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 59695 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 95075 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 24 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 21390 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 14428 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 190844 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 59695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 245564 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 33365 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 360270 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026266 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.033274 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.027971 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037083 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.021904 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.028056 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.910758 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.841369 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.903002 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.295083 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129140 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.120290 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.100499 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.177768 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.295083 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.608139 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.120290 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.520995 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.518828 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.295083 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.608139 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.120290 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.520995 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.518828 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150594 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18864 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169458 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 64 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 59931 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 95002 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 21416 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14430 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 191005 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 59931 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 245596 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 21416 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 33294 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 360463 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 59931 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 245596 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 21416 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 33294 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 360463 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026779 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.027482 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.026951 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.043317 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.031145 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.036072 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.910076 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.844731 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.902802 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.031250 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.293988 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129303 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.050000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.119957 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.099376 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.177571 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.031250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.293988 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.608056 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.050000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.119957 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.521686 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.518511 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.031250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.293988 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.608056 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.050000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.119957 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.521686 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.518511 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 102405 # number of writebacks -system.l2c.writebacks::total 102405 # number of writebacks -system.membus.snoop_filter.tot_requests 459549 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 242014 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 102433 # number of writebacks +system.l2c.writebacks::total 102433 # number of writebacks +system.membus.snoop_filter.tot_requests 459623 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 242074 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 43995 # Transaction distribution -system.membus.trans_dist::ReadResp 78173 # Transaction distribution +system.membus.trans_dist::ReadResp 78164 # Transaction distribution system.membus.trans_dist::WriteReq 30844 # Transaction distribution system.membus.trans_dist::WriteResp 30844 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138595 # Transaction distribution -system.membus.trans_dist::CleanEvict 11037 # Transaction distribution -system.membus.trans_dist::UpgradeReq 47132 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38991 # Transaction distribution -system.membus.trans_dist::UpgradeResp 461 # Transaction distribution -system.membus.trans_dist::ReadExReq 153373 # Transaction distribution -system.membus.trans_dist::ReadExResp 152974 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34178 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138623 # Transaction distribution +system.membus.trans_dist::CleanEvict 11066 # Transaction distribution +system.membus.trans_dist::UpgradeReq 47127 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39021 # Transaction distribution +system.membus.trans_dist::UpgradeResp 464 # Transaction distribution +system.membus.trans_dist::ReadExReq 153374 # Transaction distribution +system.membus.trans_dist::ReadExResp 152968 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34169 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 723651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 723713 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833107 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18572232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18762002 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18573064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18762834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21094290 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21095122 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 534369 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010375 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.101327 # Request fanout histogram +system.membus.snoop_fanout::samples 534443 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010413 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.101510 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 528825 98.96% 98.96% # Request fanout histogram -system.membus.snoop_fanout::1 5544 1.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 528878 98.96% 98.96% # Request fanout histogram +system.membus.snoop_fanout::1 5565 1.04% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 534369 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 534443 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1534,66 +1547,66 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 898844 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 454083 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 154581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 30372 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 29420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 952 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 899310 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 443343 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 166356 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1052 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 337174 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 337330 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225157 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 65355 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40931 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101494 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213640 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213640 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 293175 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1214281 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442535 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1656816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36095992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10996714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 47092706 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 140680 # Total snoops (count) -system.toL2Bus.snoopTraffic 6570496 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 1114107 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.326086 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.470599 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225154 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 65596 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60575 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40945 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101520 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213686 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213686 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 293331 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1215242 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1657510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36117688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10987754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 47105442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 144217 # Total snoops (count) +system.toL2Bus.snoopTraffic 6573440 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 1114653 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.328092 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.471525 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 751764 67.48% 67.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 361391 32.44% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 952 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 749996 67.29% 67.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 363605 32.62% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1052 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1114107 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1114653 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e1c368a8b..290cf5517 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854715000 # Number of ticks simulated -final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783856 # Number of seconds simulated +sim_ticks 2783855588000 # Number of ticks simulated +final_tick 2783855588000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1570014 # Simulator instruction rate (inst/s) -host_op_rate 1911240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30613244357 # Simulator tick rate (ticks/s) -host_mem_usage 581428 # Number of bytes of host memory used -host_seconds 90.94 # Real time elapsed on the host -sim_insts 142771202 # Number of instructions simulated -sim_ops 173801044 # Number of ops (including micro ops) simulated +host_inst_rate 1539062 # Simulator instruction rate (inst/s) +host_op_rate 1873561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30009675812 # Simulator tick rate (ticks/s) +host_mem_usage 581968 # Number of bytes of host memory used +host_seconds 92.77 # Real time elapsed on the host +sim_insts 142771499 # Number of instructions simulated +sim_ops 173801409 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory @@ -28,31 +28,31 @@ system.physmem.bytes_written::total 8858420 # Nu system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708849 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142976 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175774 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 7325045 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 10028 # Table walker walks requested system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency @@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525882 # DTB read hits +system.cpu.dtb.read_hits 31525952 # DTB read hits system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124079 # DTB write hits +system.cpu.dtb.write_hits 23124113 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534462 # DTB read accesses -system.cpu.dtb.write_accesses 23125527 # DTB write accesses +system.cpu.dtb.read_accesses 31534532 # DTB read accesses +system.cpu.dtb.write_accesses 23125561 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649961 # DTB hits +system.cpu.dtb.hits 54650065 # DTB hits system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659989 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 54660093 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4762 # Table walker walks requested system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency @@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147037694 # ITB inst hits +system.cpu.itb.inst_hits 147038008 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042456 # ITB inst accesses -system.cpu.itb.hits 147037694 # DTB hits +system.cpu.itb.inst_accesses 147042770 # ITB inst accesses +system.cpu.itb.hits 147038008 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042456 # DTB accesses +system.cpu.itb.accesses 147042770 # DTB accesses system.cpu.numPwrStateTransitions 6160 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 874939855.098377 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17329944394.226795 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -228,37 +228,37 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567712511 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 89040834297 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5567714257 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771202 # Number of instructions committed -system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses +system.cpu.committedInsts 142771499 # Number of instructions committed +system.cpu.committedOps 173801409 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161120 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873864 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls -system.cpu.num_int_insts 153160791 # number of integer instructions +system.cpu.num_func_calls 16873932 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730256 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161120 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written +system.cpu.num_int_register_reads 285043874 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178310 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written -system.cpu.num_mem_refs 55938510 # number of memory refs -system.cpu.num_load_insts 31855508 # Number of load instructions -system.cpu.num_store_insts 24083002 # Number of store instructions -system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles -system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles +system.cpu.num_cc_register_reads 530848973 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363815 # number of times the CC registers were written +system.cpu.num_mem_refs 55938612 # number of memory refs +system.cpu.num_load_insts 31855576 # Number of load instructions +system.cpu.num_store_insts 24083036 # Number of store instructions +system.cpu.num_idle_cycles 5389632489.859149 # Number of idle cycles +system.cpu.num_busy_cycles 178081767.140850 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396820 # Number of branches fetched +system.cpu.Branches 36396926 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntAlu 121151851 68.36% 68.36% # Class of executed instruction system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction @@ -289,19 +289,19 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31852800 17.97% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24074230 13.58% 99.99% # Class of executed instruction +system.cpu.op_class::MemRead 31852868 17.97% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24074264 13.58% 99.99% # Class of executed instruction system.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177217860 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819387 # number of replacements +system.cpu.op_class::total 177218242 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 819384 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783890 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819896 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.598430 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -311,55 +311,55 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219235120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235120 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 30128814 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128814 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339797 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339797 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits -system.cpu.dcache.overall_hits::total 52863571 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 52468611 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468611 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863678 # number of overall hits +system.cpu.dcache.overall_hits::total 52863678 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396270 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396270 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301666 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses -system.cpu.dcache.overall_misses::total 814058 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697936 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697936 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814055 # number of overall misses +system.cpu.dcache.overall_misses::total 814055 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641463 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641463 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53166547 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677733 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677733 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses @@ -376,14 +376,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks -system.cpu.dcache.writebacks::total 682138 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698988 # number of replacements +system.cpu.dcache.writebacks::writebacks 682141 # number of writebacks +system.cpu.dcache.writebacks::total 682141 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1698986 # number of replacements system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145341611 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699498 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.520319 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -394,27 +394,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits -system.cpu.icache.overall_hits::total 145341295 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses -system.cpu.icache.overall_misses::total 1699506 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148740619 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740619 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 145341611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341611 # number of overall hits +system.cpu.icache.overall_hits::total 145341611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699504 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699504 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699504 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699504 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699504 # number of overall misses +system.cpu.icache.overall_misses::total 1699504 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041115 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041115 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041115 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041115 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041115 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041115 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses @@ -427,19 +427,19 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks -system.cpu.icache.writebacks::total 1698988 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109912 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. +system.cpu.icache.writebacks::writebacks 1698986 # number of writebacks +system.cpu.icache.writebacks::total 1698986 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 109914 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65246.862425 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4827677 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175340 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.533233 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.133245 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734054 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy @@ -454,34 +454,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 40257153 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40257153 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682141 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682141 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666986 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666986 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 152792 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 152792 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681189 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681189 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505433 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505433 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681189 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 658225 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2347799 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits -system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681189 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 658225 # number of overall hits +system.cpu.l2cache.overall_hits::total 2347799 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -489,8 +489,8 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146119 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146119 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses @@ -498,40 +498,40 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 161687 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179994 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses -system.cpu.l2cache.overall_misses::total 179992 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 161687 # number of overall misses +system.cpu.l2cache.overall_misses::total 179994 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682141 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682141 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666986 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666986 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699487 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699487 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521001 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521001 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699487 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819912 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527793 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699487 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819912 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527793 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses @@ -548,13 +548,13 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.197200 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071206 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.197200 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071206 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,51 +563,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059862 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540459 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39267 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 427 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 427 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288305 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137243 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521001 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581944 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 115326 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 313964445 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 115353 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6542464 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5251071 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5152778 98.13% 98.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98293 1.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 5251071 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -658,14 +658,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909895 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909895 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -673,7 +673,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328176 # Number of tag accesses system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -706,71 +706,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 362813 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 151005 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::CleanEvict 8205 # Transaction distribution system.membus.trans_dist::UpgradeReq 130 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 145996 # Transaction distribution -system.membus.trans_dist::ReadExResp 145996 # Transaction distribution +system.membus.trans_dist::ReadExReq 145998 # Transaction distribution +system.membus.trans_dist::ReadExResp 145998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 714548 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430442 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram +system.membus.snoop_fanout::samples 430446 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012887 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112786 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram -system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 424899 98.71% 98.71% # Request fanout histogram +system.membus.snoop_fanout::1 5547 1.29% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 430442 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 430446 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -802,28 +802,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 51aad138d..24ac1035d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.870989 # Number of seconds simulated -sim_ticks 2870988926500 # Number of ticks simulated -final_tick 2870988926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870996 # Number of seconds simulated +sim_ticks 2870995800500 # Number of ticks simulated +final_tick 2870995800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 334502 # Simulator instruction rate (inst/s) -host_op_rate 404603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7301303629 # Simulator tick rate (ticks/s) -host_mem_usage 607968 # Number of bytes of host memory used -host_seconds 393.22 # Real time elapsed on the host -sim_insts 131531628 # Number of instructions simulated -sim_ops 159096162 # Number of ops (including micro ops) simulated +host_inst_rate 1013503 # Simulator instruction rate (inst/s) +host_op_rate 1225877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22160332076 # Simulator tick rate (ticks/s) +host_mem_usage 622032 # Number of bytes of host memory used +host_seconds 129.56 # Real time elapsed on the host +sim_insts 131304972 # Number of instructions simulated +sim_ops 158819278 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1293924 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8559616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 569684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 405184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1181796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1294372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8555136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 573844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 414464 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12163760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1333816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8766400 # Number of bytes written to this memory +system.physmem.bytes_read::total 12173424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1181796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152212 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1334008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8754752 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8783964 # Number of bytes written to this memory +system.physmem.bytes_written::total 8772316 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20737 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2555 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6331 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2533 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6476 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199207 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136975 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199358 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136793 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141366 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141184 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 411076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 450689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2981417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 141130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 450844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2979850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 199876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 144362 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4236784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 411076 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53508 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3053443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4240140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411633 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3049378 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3059560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3053443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3055496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3049378 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 411076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 456793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2981417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 141130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 411633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 456948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2979850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 199890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 144362 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7296344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199207 # Number of read requests accepted -system.physmem.writeReqs 141366 # Number of write requests accepted -system.physmem.readBursts 199207 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141366 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12740608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8796800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12163760 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8783964 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7295636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199358 # Number of read requests accepted +system.physmem.writeReqs 141184 # Number of write requests accepted +system.physmem.readBursts 199358 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141184 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12748800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue +system.physmem.bytesWritten 8785280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12173424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8772316 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11688 # Per bank write bursts -system.physmem.perBankRdBursts::1 11970 # Per bank write bursts -system.physmem.perBankRdBursts::2 12095 # Per bank write bursts -system.physmem.perBankRdBursts::3 12159 # Per bank write bursts -system.physmem.perBankRdBursts::4 20723 # Per bank write bursts -system.physmem.perBankRdBursts::5 12090 # Per bank write bursts -system.physmem.perBankRdBursts::6 12329 # Per bank write bursts -system.physmem.perBankRdBursts::7 12246 # Per bank write bursts -system.physmem.perBankRdBursts::8 12200 # Per bank write bursts -system.physmem.perBankRdBursts::9 12543 # Per bank write bursts -system.physmem.perBankRdBursts::10 11897 # Per bank write bursts -system.physmem.perBankRdBursts::11 11487 # Per bank write bursts -system.physmem.perBankRdBursts::12 11682 # Per bank write bursts -system.physmem.perBankRdBursts::13 11835 # Per bank write bursts -system.physmem.perBankRdBursts::14 11042 # Per bank write bursts -system.physmem.perBankRdBursts::15 11086 # Per bank write bursts -system.physmem.perBankWrBursts::0 8412 # Per bank write bursts -system.physmem.perBankWrBursts::1 8881 # Per bank write bursts -system.physmem.perBankWrBursts::2 9049 # Per bank write bursts -system.physmem.perBankWrBursts::3 8857 # Per bank write bursts -system.physmem.perBankWrBursts::4 8522 # Per bank write bursts -system.physmem.perBankWrBursts::5 8714 # Per bank write bursts -system.physmem.perBankWrBursts::6 9020 # Per bank write bursts -system.physmem.perBankWrBursts::7 8690 # Per bank write bursts -system.physmem.perBankWrBursts::8 8720 # Per bank write bursts -system.physmem.perBankWrBursts::9 9031 # Per bank write bursts -system.physmem.perBankWrBursts::10 8698 # Per bank write bursts -system.physmem.perBankWrBursts::11 8602 # Per bank write bursts -system.physmem.perBankWrBursts::12 8645 # Per bank write bursts -system.physmem.perBankWrBursts::13 8180 # Per bank write bursts -system.physmem.perBankWrBursts::14 7869 # Per bank write bursts -system.physmem.perBankWrBursts::15 7560 # Per bank write bursts +system.physmem.perBankRdBursts::0 11937 # Per bank write bursts +system.physmem.perBankRdBursts::1 11961 # Per bank write bursts +system.physmem.perBankRdBursts::2 12063 # Per bank write bursts +system.physmem.perBankRdBursts::3 12015 # Per bank write bursts +system.physmem.perBankRdBursts::4 20362 # Per bank write bursts +system.physmem.perBankRdBursts::5 11984 # Per bank write bursts +system.physmem.perBankRdBursts::6 12067 # Per bank write bursts +system.physmem.perBankRdBursts::7 12160 # Per bank write bursts +system.physmem.perBankRdBursts::8 12406 # Per bank write bursts +system.physmem.perBankRdBursts::9 12763 # Per bank write bursts +system.physmem.perBankRdBursts::10 11654 # Per bank write bursts +system.physmem.perBankRdBursts::11 11199 # Per bank write bursts +system.physmem.perBankRdBursts::12 11763 # Per bank write bursts +system.physmem.perBankRdBursts::13 11689 # Per bank write bursts +system.physmem.perBankRdBursts::14 11766 # Per bank write bursts +system.physmem.perBankRdBursts::15 11411 # Per bank write bursts +system.physmem.perBankWrBursts::0 8587 # Per bank write bursts +system.physmem.perBankWrBursts::1 8807 # Per bank write bursts +system.physmem.perBankWrBursts::2 8988 # Per bank write bursts +system.physmem.perBankWrBursts::3 8742 # Per bank write bursts +system.physmem.perBankWrBursts::4 8269 # Per bank write bursts +system.physmem.perBankWrBursts::5 8555 # Per bank write bursts +system.physmem.perBankWrBursts::6 8883 # Per bank write bursts +system.physmem.perBankWrBursts::7 8651 # Per bank write bursts +system.physmem.perBankWrBursts::8 8881 # Per bank write bursts +system.physmem.perBankWrBursts::9 9204 # Per bank write bursts +system.physmem.perBankWrBursts::10 8442 # Per bank write bursts +system.physmem.perBankWrBursts::11 8330 # Per bank write bursts +system.physmem.perBankWrBursts::12 8611 # Per bank write bursts +system.physmem.perBankWrBursts::13 8076 # Per bank write bursts +system.physmem.perBankWrBursts::14 8388 # Per bank write bursts +system.physmem.perBankWrBursts::15 7856 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 78 # Number of times write queue was full causing retry -system.physmem.totGap 2870987895000 # Total gap between requests +system.physmem.numWrRetry 86 # Number of times write queue was full causing retry +system.physmem.totGap 2870994769000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189447 # Read request sizes (log2) +system.physmem.readPktSize::6 189598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136975 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 135724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136793 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 136138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -181,124 +185,125 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 232 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.780968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.250026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.334701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42821 50.06% 50.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18143 21.21% 71.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6218 7.27% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3674 4.30% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2664 3.11% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1727 2.02% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 953 1.11% 89.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 967 1.13% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8373 9.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85540 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6799 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.279453 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.517669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6797 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 244 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 85519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.803880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.212865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.683468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42851 50.11% 50.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18042 21.10% 71.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6336 7.41% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3652 4.27% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2667 3.12% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 1.96% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 875 1.02% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 945 1.11% 90.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8474 9.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 85519 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.315232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.685462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6799 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6799 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.216208 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.546976 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.866150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5813 85.50% 85.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 291 4.28% 89.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 61 0.90% 90.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 49 0.72% 91.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 268 3.94% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.29% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 11 0.16% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 22 0.32% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.18% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 154 2.27% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6799 # Writes before turning the bus around for reads -system.physmem.totQLat 9415943788 # Total ticks spent queuing -system.physmem.totMemAccLat 13148543788 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 995360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47299.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.201619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.574221 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.473858 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5740 84.47% 84.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 356 5.24% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 65 0.96% 90.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.68% 91.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 271 3.99% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.28% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 18 0.26% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.16% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 153 2.25% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads +system.physmem.totQLat 9377591483 # Total ticks spent queuing +system.physmem.totMemAccLat 13112591483 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 996000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47076.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66049.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 65826.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s @@ -307,53 +312,53 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 166164 # Number of row buffer hits during reads -system.physmem.writeRowHits 84817 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 166242 # Number of row buffer hits during reads +system.physmem.writeRowHits 84708 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.physmem.avgGap 8429875.22 # Average gap between requests +system.physmem.avgGap 8430662.79 # Average gap between requests system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 312774840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 166239975 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 751842000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 366156900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6214010400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5556704280 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 357731520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11629133730 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9364882080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 675113260110 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 709836228825 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.244502 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2857863952057 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 659296177 # Time in different power states -system.physmem_0.memoryStateTime::REF 2641884000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2807973624000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 24387714557 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9823730266 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25502677500 # Time in different power states -system.physmem_1.actEnergy 297987900 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 158384325 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 669532080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 351332100 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6199259040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5628324780 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351060000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11278473150 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9521383680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 675168861345 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 709627419000 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.171771 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2857510482171 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 643430972 # Time in different power states -system.physmem_1.memoryStateTime::REF 2635632000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2808196835750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24795240087 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9984355357 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24733432334 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.physmem_0.actEnergy 309183420 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 164331090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 746479860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 362696040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6139024320.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5630456580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 369226560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11487380430 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9121751040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 675280298985 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 709613489745 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.166328 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2857680941179 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 688127950 # Time in different power states +system.physmem_0.memoryStateTime::REF 2609960000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2808734663750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 23754548081 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10016707371 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25191793348 # Time in different power states +system.physmem_1.actEnergy 301429380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 160213515 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 675808140 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 353853360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6242283840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5675698050 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 365488800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11403357870 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9537644640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 675067441050 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 709786212765 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.226489 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2857340478310 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 678311229 # Time in different power states +system.physmem_1.memoryStateTime::REF 2653946000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2807745675250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24837614861 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10072973461 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 25007279699 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -372,9 +377,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -382,7 +387,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -412,61 +417,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7799 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7799 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1450 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6349 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7799 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7799 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7799 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6405 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6523.003169 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5861 91.51% 91.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 469 7.32% 98.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 66 1.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7823 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7823 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1468 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6355 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7823 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7823 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6429 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6296.322703 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5867 91.26% 91.26% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 463 7.20% 98.46% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 86 1.34% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6405 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6429 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4994 77.97% 77.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1411 22.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6405 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5000 77.77% 77.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1429 22.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6429 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7799 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6405 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6405 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14204 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14252 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25116933 # DTB read hits -system.cpu0.dtb.read_misses 6669 # DTB read misses -system.cpu0.dtb.write_hits 18718433 # DTB write hits -system.cpu0.dtb.write_misses 1130 # DTB write misses +system.cpu0.dtb.read_hits 25081905 # DTB read hits +system.cpu0.dtb.read_misses 6707 # DTB read misses +system.cpu0.dtb.write_hits 18693539 # DTB write hits +system.cpu0.dtb.write_misses 1116 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1753 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25123602 # DTB read accesses -system.cpu0.dtb.write_accesses 18719563 # DTB write accesses +system.cpu0.dtb.read_accesses 25088612 # DTB read accesses +system.cpu0.dtb.write_accesses 18694655 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43835366 # DTB hits -system.cpu0.dtb.misses 7799 # DTB misses -system.cpu0.dtb.accesses 43843165 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43775444 # DTB hits +system.cpu0.dtb.misses 7823 # DTB misses +system.cpu0.dtb.accesses 43783267 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -496,44 +501,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3348 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3349 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3049 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5848.484815 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 389 16.68% 16.68% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1671 71.66% 88.34% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 217 9.31% 97.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.16% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 21 0.90% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.13% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5903.446394 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 363 15.56% 15.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1682 72.10% 87.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 212 9.09% 96.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.59% 98.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.54% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2033 87.18% 87.18% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 118797664 # ITB inst hits -system.cpu0.itb.inst_misses 3348 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 118659015 # ITB inst hits +system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -542,674 +545,671 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2086 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 118801012 # ITB inst accesses -system.cpu0.itb.hits 118797664 # DTB hits -system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 118801012 # DTB accesses -system.cpu0.numPwrStateTransitions 3664 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1832 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1490824715.864083 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23921725256.931263 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1059 57.81% 57.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.92% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 118662364 # ITB inst accesses +system.cpu0.itb.hits 118659015 # DTB hits +system.cpu0.itb.misses 3349 # DTB misses +system.cpu0.itb.accesses 118662364 # DTB accesses +system.cpu0.numPwrStateTransitions 3724 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1862 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1466902343.272825 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23730658455.603134 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499964287288 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1832 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 139798047037 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5741977853 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963373360 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1862 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 139623637326 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5741991601 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1832 # number of quiesce instructions executed -system.cpu0.committedInsts 115134358 # Number of instructions committed -system.cpu0.committedOps 139131175 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123155389 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed +system.cpu0.committedInsts 114996919 # Number of instructions committed +system.cpu0.committedOps 138962993 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 122999157 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12669084 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15658471 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123155389 # number of integer instructions +system.cpu0.num_func_calls 12659267 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15643522 # number of instructions that are conditional controls +system.cpu0.num_int_insts 122999157 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 226724524 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85578914 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226444380 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85465434 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504070716 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52161373 # number of times the CC registers were written -system.cpu0.num_mem_refs 44970744 # number of memory refs -system.cpu0.num_load_insts 25368600 # Number of load instructions -system.cpu0.num_store_insts 19602144 # Number of store instructions -system.cpu0.num_idle_cycles 5462381758.924097 # Number of idle cycles -system.cpu0.num_busy_cycles 279596094.075903 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048693 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951307 # Percentage of idle cycles -system.cpu0.Branches 29063879 # Number of branches fetched +system.cpu0.num_cc_register_reads 503448381 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52091583 # number of times the CC registers were written +system.cpu0.num_mem_refs 44908198 # number of memory refs +system.cpu0.num_load_insts 25331105 # Number of load instructions +system.cpu0.num_store_insts 19577093 # Number of store instructions +system.cpu0.num_idle_cycles 5462744326.346097 # Number of idle cycles +system.cpu0.num_busy_cycles 279247274.653903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048632 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951368 # Percentage of idle cycles +system.cpu0.Branches 29039529 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97803517 68.44% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109759 0.08% 68.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8141 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::IntAlu 97695313 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 108459 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25366344 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19594649 13.71% 99.99% # Class of executed instruction +system.cpu0.op_class::MemRead 25328849 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19569598 13.71% 99.99% # Class of executed instruction system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 142894434 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 691910 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.841324 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42965158 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 692422 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.050539 # Average number of references to valid blocks. +system.cpu0.op_class::total 142722234 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 690121 # number of replacements +system.cpu0.dcache.tags.tagsinuse 498.373175 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42907120 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 690633 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.127237 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.841324 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.960628 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.960628 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.373175 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973385 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.973385 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88306903 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88306903 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23857214 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23857214 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17987587 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17987587 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319351 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319351 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364951 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364951 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361858 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361858 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41844801 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41844801 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42164152 # number of overall hits -system.cpu0.dcache.overall_hits::total 42164152 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 395864 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 395864 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 325028 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325028 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126936 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 126936 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21386 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21386 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19587 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19587 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 720892 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 720892 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847828 # number of overall misses -system.cpu0.dcache.overall_misses::total 847828 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519668500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5519668500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6305983500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6305983500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336140000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 336140000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459598500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 459598500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1175500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1175500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11825652000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11825652000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11825652000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11825652000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24253078 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24253078 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18312615 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18312615 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446287 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446287 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386337 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386337 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381445 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381445 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42565693 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42565693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43011980 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43011980 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016322 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016322 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017749 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017749 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055356 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055356 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016936 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016936 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88185256 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88185256 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23824030 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23824030 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17964029 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17964029 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318863 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318863 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364525 # 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number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21435 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21435 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19554 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19554 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 718912 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 718912 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 845920 # number of overall misses +system.cpu0.dcache.overall_misses::total 845920 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5517390500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5517390500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6298218500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6298218500 # 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24218857 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24218857 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18288114 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18288114 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445871 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 445871 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385960 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 385960 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381064 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381064 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42506971 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 691910 # number of writebacks -system.cpu0.dcache.writebacks::total 691910 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25218 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25218 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15019 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15019 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25219 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25219 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25219 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25219 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370646 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 370646 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325027 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325027 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99914 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 99914 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6367 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6367 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19587 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19587 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 695673 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 695673 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 795587 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 795587 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60236 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4741194000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741194000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5980473000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5980473000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1654728000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1654728000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97962000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97962000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440045500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440045500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1141500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1141500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10721667000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10721667000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376395000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12376395000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631909500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631909500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631909500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631909500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015282 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015282 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017749 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017749 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223878 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223878 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016480 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051349 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051349 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016344 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016344 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 690121 # number of writebacks +system.cpu0.dcache.writebacks::total 690121 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25200 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25200 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15056 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15056 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25200 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25200 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25200 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25200 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369627 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369627 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324085 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324085 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100010 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100010 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6379 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6379 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19554 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19554 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 693712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 693712 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 793722 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 793722 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31768 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60214 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4739955500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739955500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5974133500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5974133500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1650418500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1650418500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101003000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101003000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439215500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439215500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1081000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1081000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10714089000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10714089000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12364507500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12364507500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631169500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631169500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631169500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631169500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015262 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015262 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017721 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017721 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224303 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224303 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016528 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016528 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051314 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051314 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016320 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016320 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018479 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018479 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1101405 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.436911 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117695738 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1101917 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.809985 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1095423 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.436912 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117563071 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1095935 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 107.271938 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436911 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436912 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 238697254 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 238697254 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117695738 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117695738 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117695738 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117695738 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117695738 # number of overall hits -system.cpu0.icache.overall_hits::total 117695738 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1101926 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1101926 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1101926 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1101926 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1101926 # number of overall misses -system.cpu0.icache.overall_misses::total 1101926 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11884591500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11884591500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11884591500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11884591500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11884591500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11884591500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 118797664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 118797664 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 118797664 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 118797664 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 118797664 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 118797664 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # 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Number of tag accesses +system.cpu0.icache.tags.data_accesses 238413974 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117563071 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117563071 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117563071 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117563071 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117563071 # number of overall hits +system.cpu0.icache.overall_hits::total 117563071 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1095944 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1095944 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1095944 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1095944 # 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average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10809.830612 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10809.830612 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1101405 # 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average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009236 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009236 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009236 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842335 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1842343 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843455 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1843489 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 30 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236049 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 259510 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15639.759609 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1683263 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 275158 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.117442 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237167 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 260392 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15616.554479 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1673878 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 276011 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.064534 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.607944 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.119153 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1173.013607 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.882875 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000098 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071595 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954575 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 297 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15346 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 119 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.380966 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135465 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1156.527151 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.882477 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070589 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.953159 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15300 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 129 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 150 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 812 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6453 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1818 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018127 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936646 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 61207036 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 61207036 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9838 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4464 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14302 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4943218500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8008936000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2694500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3056153000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4943218500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24757589122 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377241500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6376615000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172255500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377241500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172882000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029913 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6376615000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172255500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032577 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1218,118 +1218,120 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154173 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154173 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056319 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211487 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211487 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110007 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153631 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153631 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.057080 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212182 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212182 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110670 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.250882 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251662 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3728751 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879521 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27804 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 211480 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1677 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1688185 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28454 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28454 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 702444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1317788 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 79827 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309039 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86996 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41768 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111544 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 289661 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286091 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1101926 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562800 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3273 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3323301 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2556545 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10999 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24289 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5915134 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141049272 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96382808 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18408 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40564 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 237491052 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 885699 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18622452 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2792086 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.090598 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.289121 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3713043 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871637 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27791 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 210694 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1647 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61395 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1681090 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28446 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28446 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 701864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1311457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 80209 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86960 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111633 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288540 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562349 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3305355 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550756 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11066 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24460 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5891637 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140283576 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96129280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18668 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41128 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 236472652 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 885693 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18656572 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2784580 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.090516 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.288973 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2540806 91.00% 91.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 249603 8.94% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1677 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2534179 91.01% 91.01% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 248754 8.93% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1647 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2792086 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3710834999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2784580 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3695245998 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114296030 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113887546 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1661911000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1652938000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1204165985 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1201348488 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14154986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14180994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1359,67 +1361,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3359 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3368 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3368 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2589 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5453.033399 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 2 0.08% 0.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 579 22.36% 22.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1101 42.53% 64.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 577 22.29% 87.25% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 84 3.24% 90.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 148 5.72% 96.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 49 1.89% 98.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 18 0.70% 98.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 23 0.89% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.08% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 4 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2589 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3368 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3368 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3368 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2598 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5669.313441 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 611 23.52% 23.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 64.32% 87.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 8.85% 96.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 69 2.66% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 10 0.38% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2598 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1928 74.47% 74.47% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 661 25.53% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.56% 74.56% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 661 25.44% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3368 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3368 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5966 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3975776 # DTB read hits -system.cpu1.dtb.read_misses 2856 # DTB read misses -system.cpu1.dtb.write_hits 3446428 # DTB write hits -system.cpu1.dtb.write_misses 503 # DTB write misses +system.cpu1.dtb.read_hits 3952331 # DTB read hits +system.cpu1.dtb.read_misses 2852 # DTB read misses +system.cpu1.dtb.write_hits 3427850 # DTB write hits +system.cpu1.dtb.write_misses 516 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1973 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1975 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 329 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 341 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3978632 # DTB read accesses -system.cpu1.dtb.write_accesses 3446931 # DTB write accesses +system.cpu1.dtb.read_accesses 3955183 # DTB read accesses +system.cpu1.dtb.write_accesses 3428366 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7422204 # DTB hits -system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 7425563 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7380181 # DTB hits +system.cpu1.dtb.misses 3368 # DTB misses +system.cpu1.dtb.accesses 7383549 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1449,7 +1447,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1458,20 +1456,21 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5775.216215 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 143 12.92% 12.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 70.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 85.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 51 4.61% 90.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 51 4.61% 94.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.53% 97.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 98.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.45% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5651.710937 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.36% 15.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 628 56.73% 72.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 162 14.63% 86.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.43% 91.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 38 3.43% 94.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 32 2.89% 97.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 4 0.36% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution @@ -1486,7 +1485,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16753470 # ITB inst hits +system.cpu1.itb.inst_hits 16663369 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1503,16 +1502,16 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16755216 # ITB inst accesses -system.cpu1.itb.hits 16753470 # DTB hits +system.cpu1.itb.inst_accesses 16665115 # ITB inst accesses +system.cpu1.itb.hits 16663369 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16755216 # DTB accesses -system.cpu1.numPwrStateTransitions 5461 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2731 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1041523757.275357 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25854556705.104488 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1955 71.59% 71.59% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 770 28.19% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16665115 # DTB accesses +system.cpu1.numPwrStateTransitions 5435 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2718 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1046549937.704562 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25917662670.452511 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1945 71.56% 71.56% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 767 28.22% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state @@ -1520,39 +1519,39 @@ system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96 system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2731 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 26587545381 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5741033861 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2718 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26473069819 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5741059879 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed -system.cpu1.committedInsts 16397270 # Number of instructions committed -system.cpu1.committedOps 19964987 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17986629 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed +system.cpu1.committedInsts 16308053 # Number of instructions committed +system.cpu1.committedOps 19856285 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17888019 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1033857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1854028 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17986629 # number of integer instructions +system.cpu1.num_func_calls 1028859 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1844250 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17888019 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 32622652 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12608250 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32444258 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12537466 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72946565 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6544066 # number of times the CC registers were written -system.cpu1.num_mem_refs 7656991 # number of memory refs -system.cpu1.num_load_insts 4087327 # Number of load instructions -system.cpu1.num_store_insts 3569664 # Number of store instructions -system.cpu1.num_idle_cycles 5687867512.323336 # Number of idle cycles -system.cpu1.num_busy_cycles 53166348.676665 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009261 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990739 # Percentage of idle cycles -system.cpu1.Branches 2968001 # Number of branches fetched +system.cpu1.num_cc_register_reads 72543530 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6508973 # number of times the CC registers were written +system.cpu1.num_mem_refs 7613771 # number of memory refs +system.cpu1.num_load_insts 4063495 # Number of load instructions +system.cpu1.num_store_insts 3550276 # Number of store instructions +system.cpu1.num_idle_cycles 5688122330.646462 # Number of idle cycles +system.cpu1.num_busy_cycles 52937548.353538 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009221 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990779 # Percentage of idle cycles +system.cpu1.Branches 2952894 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12630695 62.17% 62.17% # Class of executed instruction -system.cpu1.op_class::IntMult 26529 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntAlu 12563541 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 26310 0.13% 62.30% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction @@ -1578,586 +1577,586 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3311 0.02% 62.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% # Class of executed instruction -system.cpu1.op_class::MemRead 4086811 20.11% 82.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 3568388 17.56% 99.99% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::MemRead 4062979 20.11% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3549000 17.56% 99.99% # Class of executed instruction system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20317592 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 188214 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.650282 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7155880 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188578 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.946526 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105561245500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.650282 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917286 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917286 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15064679 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15064679 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3662279 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3662279 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3257080 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3257080 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49206 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49206 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79332 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79332 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71298 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71298 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6919359 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6919359 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6968565 # number of overall hits -system.cpu1.dcache.overall_hits::total 6968565 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 134376 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 134376 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92202 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92202 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30516 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30516 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17009 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17009 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23197 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23197 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 226578 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 226578 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 257094 # number of overall misses -system.cpu1.dcache.overall_misses::total 257094 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2053970000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2053970000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2521876000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2521876000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321694000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 321694000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544347500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544347500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1836500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1836500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4575846000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4575846000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4575846000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4575846000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3796655 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3796655 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3349282 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3349282 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79722 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79722 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96341 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96341 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94495 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94495 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7145937 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7145937 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7225659 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7225659 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035393 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035393 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027529 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027529 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382780 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382780 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.245484 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.245484 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031707 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031707 # miss rate for demand accesses +system.cpu1.op_class::total 20206967 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 187241 # number of replacements +system.cpu1.dcache.tags.tagsinuse 470.165247 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7113602 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187604 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.918179 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 128171950500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.165247 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.918291 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14979376 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14979376 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3640649 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3640649 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3239316 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3239316 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49005 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49005 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78940 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78940 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70837 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70837 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6879965 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6879965 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6928970 # number of overall hits +system.cpu1.dcache.overall_hits::total 6928970 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133578 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133578 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91863 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91863 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30193 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30193 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16916 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16916 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23207 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23207 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225441 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225441 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255634 # number of overall misses +system.cpu1.dcache.overall_misses::total 255634 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2045952000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2045952000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2531885000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2531885000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322352500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322352500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544400500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 544400500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2036500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2036500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4577837000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4577837000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4577837000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4577837000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3774227 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3774227 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3331179 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3331179 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79198 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79198 # 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miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027577 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381234 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381234 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176473 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176473 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246767 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246767 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031728 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031728 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 188214 # number of writebacks -system.cpu1.dcache.writebacks::total 188214 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 253 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12043 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12043 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 253 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 253 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 253 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134123 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 134123 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92202 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92202 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29799 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29799 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4966 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4966 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23197 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23197 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 226325 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 226325 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256124 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256124 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5526 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1909849500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1909849500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2429674000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2429674000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508192000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508192000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89547000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89547000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1793500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4339523500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4339523500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4847715500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4847715500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443097000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443097000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443097000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443097000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035327 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035327 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027529 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027529 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373786 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373786 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051546 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051546 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.245484 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.245484 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031672 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031672 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035446 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 187241 # number of writebacks +system.cpu1.dcache.writebacks::total 187241 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 248 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11947 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11947 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 248 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133330 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133330 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91863 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91863 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29503 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29503 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4969 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4969 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23207 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23207 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225193 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225193 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254696 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254696 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3077 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5509 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901282500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901282500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2440022000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2440022000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 505317500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 505317500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91175500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91175500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521240500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521240500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1989500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1989500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4341304500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4341304500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846622000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4846622000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442663500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442663500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442663500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442663500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035326 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035326 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027577 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027577 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372522 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372522 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051838 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246767 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246767 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031693 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031693 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035450 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035450 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 506865 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.456606 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16246088 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 507377 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 32.019757 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85409397000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.456606 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973548 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973548 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 503470 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.455555 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16159382 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 503982 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.063411 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85409649000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455555 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973546 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 389 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 34014307 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 34014307 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16246088 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16246088 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16246088 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16246088 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16246088 # number of overall hits -system.cpu1.icache.overall_hits::total 16246088 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 507377 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 507377 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 507377 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 507377 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 507377 # number of overall misses -system.cpu1.icache.overall_misses::total 507377 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4790701000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4790701000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4790701000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4790701000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4790701000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4790701000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16753465 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16753465 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16753465 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16753465 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16753465 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16753465 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030285 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030285 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030285 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030285 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030285 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030285 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9442.093355 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9442.093355 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9442.093355 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9442.093355 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33830710 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33830710 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16159382 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16159382 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16159382 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16159382 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16159382 # number of overall hits +system.cpu1.icache.overall_hits::total 16159382 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 503982 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 503982 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 503982 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 503982 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 503982 # number of overall misses +system.cpu1.icache.overall_misses::total 503982 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4760681000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4760681000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4760681000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4760681000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4760681000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4760681000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16663364 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16663364 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16663364 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16663364 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16663364 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16663364 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030245 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030245 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030245 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030245 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030245 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030245 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9446.132997 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9446.132997 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9446.132997 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9446.132997 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 506865 # number of writebacks -system.cpu1.icache.writebacks::total 506865 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 507377 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 507377 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 507377 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 507377 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 507377 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 507377 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 503470 # number of writebacks +system.cpu1.icache.writebacks::total 503470 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503982 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 503982 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 503982 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 503982 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 503982 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 503982 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4537012500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4537012500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4537012500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4537012500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4537012500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4537012500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4508690000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4508690000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4508690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4508690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4508690000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4508690000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030285 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030285 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030285 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8942.093355 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030245 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030245 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030245 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8946.132997 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 202159 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 202159 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 202393 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 202393 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59833 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43683 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14553.446834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 604546 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 57834 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.453124 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 60767 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 44084 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14674.344516 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 603056 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58488 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 10.310765 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.245443 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.035798 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 412.309882 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.862845 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000137 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025165 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.888272 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13825 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 293 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1016 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2429 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10380 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843811 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24413579 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24413579 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3816 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5831 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 114934 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 114934 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 568988 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 568988 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27893 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27893 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485948 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 485948 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99069 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99069 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3816 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 485948 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 126962 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 618741 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3816 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2015 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 485948 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 126962 # number of overall hits -system.cpu1.l2cache.overall_hits::total 618741 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 325 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 766 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29445 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29445 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23189 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23189 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34864 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34864 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21429 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 21429 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69819 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 69819 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 325 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 21429 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104683 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 126878 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 325 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 21429 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104683 # number of overall misses -system.cpu1.l2cache.overall_misses::total 126878 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9097000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6572000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 15669000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14547500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 14547500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17306000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17306000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1729000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1729000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1479795000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1479795000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845906500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845906500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606277000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606277000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9097000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6572000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845906500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3086072000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3947647500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9097000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6572000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845906500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3086072000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3947647500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4257 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2340 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6597 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114934 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 114934 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 568988 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 568988 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29445 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29445 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23189 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23189 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62757 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62757 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 507377 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 507377 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168888 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 168888 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4257 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2340 # 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miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.272921 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.058859 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.410915 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.872107 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023279 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.895651 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14077 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 292 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 892 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2699 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10486 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000977 # 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number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115944 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2166,123 +2165,123 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # 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mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.204741 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183875 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183875 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206367 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1493074 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 754096 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11157 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 112771 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12635 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 726264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2441 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2441 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 148991 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 580145 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 27848 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30881 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70910 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85257 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69946 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67407 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 507377 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 264100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 245 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1521973 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 842546 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5664 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10306 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2380489 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64912196 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29583168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9360 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17028 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94521752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 332142 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4881760 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1061400 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.130546 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.359362 # Request fanout histogram +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1483973 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749706 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112750 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12645 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 721727 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2432 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2432 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 148874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 576372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 28336 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31823 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40952 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85036 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69693 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67178 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 503982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263487 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 292 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511788 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838524 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5603 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10248 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2366163 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64477636 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29432570 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9116 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16724 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 93936046 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 334351 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4909260 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1058830 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.130816 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359612 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 931138 87.73% 87.73% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 121963 11.49% 99.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8299 0.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 928586 87.70% 87.70% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 121976 11.52% 99.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8268 0.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1061400 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1447209000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1058830 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1438248000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79433455 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79282585 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 761242500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 756150000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 378138998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 376097000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6050996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6067998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 59423 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2301,11 +2300,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2324,23 +2323,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48592000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48604000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 318500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 615500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2362,32 +2361,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6203500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6201500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32039500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32041500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187757841 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187869528 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.377097 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.382505 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290025611000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.377097 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898569 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898569 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290037968000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.382505 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898907 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898907 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2396,14 +2395,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 40988875 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 40988875 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4375977966 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4375977966 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4416966841 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4416966841 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4416966841 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4416966841 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 41042377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 41042377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4379492151 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4379492151 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4420534528 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4420534528 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4420534528 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4420534528 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2420,19 +2419,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160740.686275 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121082.454042 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121082.454042 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160950.498039 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121180.255161 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121180.255161 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 33.111111 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2444,14 +2443,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 28238875 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 28238875 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562446714 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2562446714 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2590685589 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2590685589 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2590685589 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2590685589 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28292377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28292377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2566405842 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2566405842 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2594698219 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2594698219 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2594698219 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2594698219 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2460,565 +2459,593 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137086 # number of replacements -system.l2c.tags.tagsinuse 65074.643000 # Cycle average of tags in use -system.l2c.tags.total_refs 524868 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202455 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.592517 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 103102985000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6607.466111 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.944223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7194.422354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6927.905114 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1475.884148 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3147.084233 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2554.669060 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.100822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137345 # number of replacements +system.l2c.tags.tagsinuse 65074.392349 # Cycle average of tags in use +system.l2c.tags.total_refs 526935 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202695 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.599645 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 103119965000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6537.248776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009779 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7065.227850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6920.254188 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1513.426266 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3159.258777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2388.379223 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.099751 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.109778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105711 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.022520 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038981 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992960 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 34101 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31263 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.107807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105595 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571985 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.023093 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.048206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 34308 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31034 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4715 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29456 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30056 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.520340 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.477036 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6098343 # Number of tag accesses -system.l2c.tags.data_accesses 6098343 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 259635 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 259635 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 39907 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4995 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 44902 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2353 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2177 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4530 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1485 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5463 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 146 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44179 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 52512 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45683 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 56 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 30 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 19035 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 10985 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5208 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 177905 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 56490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45683 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 56 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 30 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 19035 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12470 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5208 # number of demand (read+write) hits -system.l2c.demand_hits::total 183368 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44179 # number of overall hits -system.l2c.overall_hits::cpu0.data 56490 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45683 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 56 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 30 # number of overall hits -system.l2c.overall_hits::cpu1.inst 19035 # number of overall hits -system.l2c.overall_hits::cpu1.data 12470 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5208 # number of overall hits -system.l2c.overall_hits::total 183368 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 508 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 339 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 847 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 113 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 106 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 219 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11276 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7954 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19230 # number of ReadExReq misses +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1168 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29797 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.523499 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.473541 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6118121 # Number of tag accesses +system.l2c.tags.data_accesses 6118121 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 260748 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 260748 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 39886 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4893 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 44779 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2390 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2219 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4609 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3995 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1504 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5499 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 159 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 44649 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 52745 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45897 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 18994 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11024 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5470 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 179087 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 159 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 44649 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 56740 # 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average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015574 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055770 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.020132 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033562 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.041469 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037385 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.738821 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.778534 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146935 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078723 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487893 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.507160 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.507160 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 503139 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 282937 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 589 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 502698 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 282285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 634 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44063 # Transaction distribution -system.membus.trans_dist::ReadResp 214894 # Transaction distribution -system.membus.trans_dist::WriteReq 30895 # Transaction distribution -system.membus.trans_dist::WriteResp 30895 # Transaction distribution -system.membus.trans_dist::WritebackDirty 136975 # Transaction distribution -system.membus.trans_dist::CleanEvict 16276 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64763 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38177 # Transaction distribution -system.membus.trans_dist::UpgradeResp 17 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44041 # Transaction distribution +system.membus.trans_dist::ReadResp 214925 # Transaction distribution +system.membus.trans_dist::WriteReq 30878 # Transaction distribution +system.membus.trans_dist::WriteResp 30878 # Transaction distribution +system.membus.trans_dist::WritebackDirty 136793 # Transaction distribution +system.membus.trans_dist::CleanEvict 16421 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64440 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38073 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39789 # Transaction distribution -system.membus.trans_dist::ReadExResp 19204 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170831 # Transaction distribution +system.membus.trans_dist::ReadExReq 39751 # Transaction distribution +system.membus.trans_dist::ReadExResp 19302 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170884 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 4530 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 769460 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 769084 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842399 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 842023 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18630604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18820796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18628620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18818654 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21137916 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123039 # Total snoops (count) +system.membus.pkt_size::total 21135774 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126969 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 424743 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109769 # Request fanout histogram +system.membus.snoop_fanout::samples 424292 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012213 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109837 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 419562 98.78% 98.78% # Request fanout histogram -system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419110 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 5182 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 424743 # Request fanout histogram -system.membus.reqLayer0.occupancy 88158500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 424292 # Request fanout histogram +system.membus.reqLayer0.occupancy 88179000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11394500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11330000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 971210962 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 970733801 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1112716909 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1113560532 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1441377 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 7243389 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3050,77 +3077,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1012483 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 538775 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 174846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29019 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27944 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1075 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44066 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 511105 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30895 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30895 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 360420 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 118997 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152346 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50919 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50919 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 467041 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1013922 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 527446 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 187526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29573 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28355 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1218 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44044 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 511645 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30878 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30878 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 361351 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 119836 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109190 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42682 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 151872 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50757 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50757 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 467605 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1269868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316423 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1586291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35149508 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5612856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40762364 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 388626 # Total snoops (count) -system.toL2Bus.snoopTraffic 15721036 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 887021 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.395992 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.491535 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateResp 3427 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1275330 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317115 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1592445 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35259052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5662514 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40921566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 390876 # Total snoops (count) +system.toL2Bus.snoopTraffic 15646988 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 887171 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.397282 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.492133 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 536843 60.52% 60.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 349103 39.36% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1075 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 535932 60.41% 60.41% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 350021 39.45% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1218 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 887021 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 892902016 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 887171 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 894860010 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2155585 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 675868420 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 676392933 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 239041660 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 238880542 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 507baa590..ff7f585c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.905318 # Number of seconds simulated -sim_ticks 2905317504500 # Number of ticks simulated -final_tick 2905317504500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.905317 # Number of seconds simulated +sim_ticks 2905316914500 # Number of ticks simulated +final_tick 2905316914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 372777 # Simulator instruction rate (inst/s) -host_op_rate 449455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9630563349 # Simulator tick rate (ticks/s) -host_mem_usage 568288 # Number of bytes of host memory used -host_seconds 301.68 # Real time elapsed on the host -sim_insts 112458065 # Number of instructions simulated -sim_ops 135590016 # Number of ops (including micro ops) simulated +host_inst_rate 1074625 # Simulator instruction rate (inst/s) +host_op_rate 1295669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27762631762 # Simulator tick rate (ticks/s) +host_mem_usage 582724 # Number of bytes of host memory used +host_seconds 104.65 # Real time elapsed on the host +sim_insts 112457861 # Number of instructions simulated +sim_ops 135589764 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8969508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8969572 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10157576 # Number of bytes read from this memory +system.physmem.bytes_read::total 10157640 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7562112 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7562240 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7579636 # Number of bytes written to this memory +system.physmem.bytes_written::total 7579764 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140669 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 167685 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118158 # Number of write requests responded to by this memory +system.physmem.num_reads::total 167686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118160 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122539 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122541 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3087273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3087296 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3496202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3496224 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2602852 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2602897 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2608884 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2602852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2608928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2602897 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3093305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3093327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6105086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 167685 # Number of read requests accepted -system.physmem.writeReqs 122539 # Number of write requests accepted -system.physmem.readBursts 167685 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122539 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10724096 # Total number of bytes read from DRAM +system.physmem.bw_total::total 6105153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 167686 # Number of read requests accepted +system.physmem.writeReqs 122541 # Number of write requests accepted +system.physmem.readBursts 167686 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122541 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10724160 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7592512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10157576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7579636 # Total written bytes from the system interface side +system.physmem.bytesWritten 7592640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10157640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7579764 # Total written bytes from the system interface side system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9872 # Per bank write bursts +system.physmem.perBankRdBursts::0 9873 # Per bank write bursts system.physmem.perBankRdBursts::1 9614 # Per bank write bursts system.physmem.perBankRdBursts::2 9963 # Per bank write bursts system.physmem.perBankRdBursts::3 9595 # Per bank write bursts @@ -80,7 +80,7 @@ system.physmem.perBankRdBursts::12 10202 # Pe system.physmem.perBankRdBursts::13 10190 # Per bank write bursts system.physmem.perBankRdBursts::14 10325 # Per bank write bursts system.physmem.perBankRdBursts::15 9515 # Per bank write bursts -system.physmem.perBankWrBursts::0 7135 # Per bank write bursts +system.physmem.perBankWrBursts::0 7137 # Per bank write bursts system.physmem.perBankWrBursts::1 7022 # Per bank write bursts system.physmem.perBankWrBursts::2 7742 # Per bank write bursts system.physmem.perBankWrBursts::3 7365 # Per bank write bursts @@ -98,22 +98,22 @@ system.physmem.perBankWrBursts::14 7752 # Pe system.physmem.perBankWrBursts::15 6956 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 62 # Number of times write queue was full causing retry -system.physmem.totGap 2905317142500 # Total gap between requests +system.physmem.totGap 2905316552500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158113 # Read request sizes (log2) +system.physmem.readPktSize::6 158114 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118158 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 166730 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118160 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 166731 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -160,89 +160,90 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 187 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.389430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.497805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.903414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20578 35.66% 35.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14720 25.51% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5637 9.77% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3163 5.48% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2413 4.18% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1394 2.42% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1275 2.21% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 905 1.57% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7625 13.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57710 # Bytes accessed per row activation +system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.409257 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.502400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.930049 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20577 35.66% 35.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14716 25.50% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5644 9.78% 70.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3157 5.47% 76.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2419 4.19% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1386 2.40% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1272 2.20% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 912 1.58% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7624 13.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57707 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.919917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 588.859232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.920090 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 588.859251 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.475147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.526106 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.995822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5070 87.50% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36 0.62% 88.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 58 1.00% 89.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 41 0.71% 89.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 290 5.01% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 32 0.55% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.09% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.14% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.09% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.03% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.475492 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.528054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.935092 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5069 87.49% 87.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 41 0.71% 88.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 52 0.90% 89.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 288 4.97% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 23 0.40% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.28% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.09% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads @@ -254,26 +255,26 @@ system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Wr system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.16% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads -system.physmem.totQLat 4573778750 # Total ticks spent queuing -system.physmem.totMemAccLat 7715603750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 837820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27295.71 # Average queueing delay per DRAM burst +system.physmem.totQLat 4572629500 # Total ticks spent queuing +system.physmem.totMemAccLat 7714473250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 837825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27288.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46045.71 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46038.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s @@ -283,52 +284,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing -system.physmem.readRowHits 138574 # Number of row buffer hits during reads -system.physmem.writeRowHits 89912 # Number of row buffer hits during writes +system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing +system.physmem.readRowHits 138575 # Number of row buffer hits during reads +system.physmem.writeRowHits 89917 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes -system.physmem.avgGap 10010602.65 # Average gap between requests +system.physmem.avgGap 10010497.14 # Average gap between requests system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 209951700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 111591975 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 639486960 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 313377480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6673146480.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4797272190 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 415271520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13955015310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9412509120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 682622001540 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 719151899205 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.529538 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2893187374000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 780943500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2837778000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2838595786500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 24511740750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7987774000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 30603481750 # Time in different power states -system.physmem_1.actEnergy 202104840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 107417475 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 209944560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 111588180 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 639494100 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313387920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6674375760.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4793281050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 418187520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13958691240 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9415844160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 682618118940 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 719155193400 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.530722 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2893187924000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 788400750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2838298000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2838579624000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24520427750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7978656750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 30611507250 # Time in different power states +system.physmem_1.actEnergy 202090560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 107409885 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6671302560.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4519380090 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 410434080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13655969940 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9525025920 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 682931246265 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 718886718750 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.438264 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2894335381000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 777927000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2837694000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2839583336000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24804588750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7366436500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29947522250 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.physmem_1.refreshEnergy 6670687920.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4519112190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 410472000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13651117530 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9526323840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 682932964665 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 718884016170 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.437384 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2894335317000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 777922000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2837434000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2839590532250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24808008250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7366175500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29936842500 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -341,9 +342,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -351,7 +352,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,7 +382,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 9553 # Table walker walks requested system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate @@ -390,9 +391,9 @@ system.cpu.dtb.walker.walkWaitTime::samples 9553 # system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10013.804304 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8464.395211 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6610.536044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10013.601299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8464.254766 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6610.467359 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency @@ -413,9 +414,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24519779 # DTB read hits +system.cpu.dtb.read_hits 24519746 # DTB read hits system.cpu.dtb.read_misses 8140 # DTB read misses -system.cpu.dtb.write_hits 19605270 # DTB write hits +system.cpu.dtb.write_hits 19605246 # DTB write hits system.cpu.dtb.write_misses 1413 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -426,13 +427,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24527919 # DTB read accesses -system.cpu.dtb.write_accesses 19606683 # DTB write accesses +system.cpu.dtb.read_accesses 24527886 # DTB read accesses +system.cpu.dtb.write_accesses 19606659 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44125049 # DTB hits +system.cpu.dtb.hits 44124992 # DTB hits system.cpu.dtb.misses 9553 # DTB misses -system.cpu.dtb.accesses 44134602 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.accesses 44134545 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -462,7 +463,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 4763 # Table walker walks requested system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate @@ -493,7 +494,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115555925 # ITB inst hits +system.cpu.itb.inst_hits 115555708 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -510,14 +511,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115560688 # ITB inst accesses -system.cpu.itb.hits 115555925 # DTB hits +system.cpu.itb.inst_accesses 115560471 # ITB inst accesses +system.cpu.itb.hits 115555708 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115560688 # DTB accesses +system.cpu.itb.accesses 115560471 # DTB accesses system.cpu.numPwrStateTransitions 6064 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887473047.745383 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17466686250.192787 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887473262.784960 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17466686239.333317 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -527,37 +528,37 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 214499223736 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818280764 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5810635009 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 214497981736 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818932764 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5810633829 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu.committedInsts 112458065 # Number of instructions committed -system.cpu.committedOps 135590016 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119895072 # Number of integer alu accesses +system.cpu.committedInsts 112457861 # Number of instructions committed +system.cpu.committedOps 135589764 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119894844 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9894802 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230859 # number of instructions that are conditional controls -system.cpu.num_int_insts 119895072 # number of integer instructions +system.cpu.num_func_calls 9894754 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230835 # number of instructions that are conditional controls +system.cpu.num_int_insts 119894844 # number of integer instructions system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218056824 # number of times the integer registers were read -system.cpu.num_int_register_writes 82647475 # number of times the integer registers were written +system.cpu.num_int_register_reads 218056368 # number of times the integer registers were read +system.cpu.num_int_register_writes 82647309 # number of times the integer registers were written system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489748178 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51895154 # number of times the CC registers were written -system.cpu.num_mem_refs 45405351 # number of memory refs -system.cpu.num_load_insts 24842092 # Number of load instructions -system.cpu.num_store_insts 20563259 # Number of store instructions -system.cpu.num_idle_cycles 5381636561.526148 # Number of idle cycles -system.cpu.num_busy_cycles 428998447.473852 # Number of busy cycles -system.cpu.not_idle_fraction 0.073830 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.926170 # Percentage of idle cycles -system.cpu.Branches 25919628 # Number of branches fetched +system.cpu.num_cc_register_reads 489747242 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51895082 # number of times the CC registers were written +system.cpu.num_mem_refs 45405279 # number of memory refs +system.cpu.num_load_insts 24842044 # Number of load instructions +system.cpu.num_store_insts 20563235 # Number of store instructions +system.cpu.num_idle_cycles 5381637865.526148 # Number of idle cycles +system.cpu.num_busy_cycles 428995963.473852 # Number of busy cycles +system.cpu.not_idle_fraction 0.073829 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.926171 # Percentage of idle cycles +system.cpu.Branches 25919556 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93180053 67.18% 67.18% # Class of executed instruction +system.cpu.op_class::IntAlu 93179861 67.18% 67.18% # Class of executed instruction system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction @@ -588,19 +589,19 @@ system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::MemRead 24839384 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20554681 14.82% 99.99% # Class of executed instruction +system.cpu.op_class::MemRead 24839336 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20554657 14.82% 99.99% # Class of executed instruction system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138710700 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 821158 # number of replacements +system.cpu.op_class::total 138710436 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 821157 # number of replacements system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43232098 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821670 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.614916 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 43232042 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821669 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.614912 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy @@ -611,97 +612,97 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177104923 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177104923 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23110979 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23110979 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18822589 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18822589 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 177104694 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177104694 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23110946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23110946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18822565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18822565 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443107 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443107 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443108 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443108 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41933568 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41933568 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42326041 # number of overall hits -system.cpu.dcache.overall_hits::total 42326041 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41933511 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41933511 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42325984 # number of overall hits +system.cpu.dcache.overall_hits::total 42325984 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22807 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22807 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22806 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses system.cpu.dcache.overall_misses::total 818708 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437634500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6437634500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14441729500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14441729500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297474000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 297474000 # number of LoadLockedReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437831500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6437831500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440805000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14440805000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297461000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 297461000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20879364000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20879364000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20879364000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20879364000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512121 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19121471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19121471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 20878636500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20878636500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20878636500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20878636500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19121447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19121447 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42633592 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42633592 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43144749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43144749 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42633535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42633535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43144692 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43144692 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048949 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.268444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.268444 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48319.167765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48319.167765 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.100802 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.100802 # average LoadLockedReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.759542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.759542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48316.074571 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48316.074571 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.102692 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.102692 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29826.640229 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29826.640229 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25502.821519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25502.821519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29825.600979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29825.600979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25501.932924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25501.932924 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 685618 # number of writebacks -system.cpu.dcache.writebacks::total 685618 # number of writebacks +system.cpu.dcache.writebacks::writebacks 685616 # number of writebacks +system.cpu.dcache.writebacks::total 685616 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits @@ -716,8 +717,8 @@ system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8529 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8529 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8528 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses @@ -730,20 +731,20 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6011986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6011986000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14142847500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14142847500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587073500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118989500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118989500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6012304000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6012304000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141923000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141923000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1586831500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1586831500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118977500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118977500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20154833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741907000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21741907000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20154227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741058500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21741058500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles @@ -754,38 +755,38 @@ system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018306 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018306 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018304 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018304 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15013.675162 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15013.675162 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47319.167765 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47319.167765 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13604.147916 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13604.147916 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.166608 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.166608 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15014.469301 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15014.469301 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47316.074571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47316.074571 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13602.073529 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13602.073529 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.395403 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.395403 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28820.781306 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28820.781306 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26645.244903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26645.244903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28819.914030 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28819.914030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26644.205045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26644.205045 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1700061 # number of replacements +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1700062 # number of replacements system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113855346 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1700573 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.951166 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 113855128 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1700574 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.950999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy @@ -796,69 +797,69 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 212 system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117256504 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117256504 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113855346 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113855346 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113855346 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113855346 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113855346 # number of overall hits -system.cpu.icache.overall_hits::total 113855346 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1700579 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1700579 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1700579 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1700579 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1700579 # number of overall misses -system.cpu.icache.overall_misses::total 1700579 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24045189500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24045189500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24045189500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24045189500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24045189500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24045189500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115555925 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115555925 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115555925 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115555925 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115555925 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115555925 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 117256288 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117256288 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 113855128 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113855128 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113855128 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113855128 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113855128 # number of overall hits +system.cpu.icache.overall_hits::total 113855128 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1700580 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1700580 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1700580 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1700580 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1700580 # number of overall misses +system.cpu.icache.overall_misses::total 1700580 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24044969500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24044969500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24044969500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24044969500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24044969500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24044969500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115555708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115555708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115555708 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115555708 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115555708 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115555708 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.413400 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14139.413400 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14139.413400 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.413400 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14139.413400 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.275718 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14139.275718 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14139.275718 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14139.275718 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1700061 # number of writebacks -system.cpu.icache.writebacks::total 1700061 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700579 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1700579 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1700579 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1700579 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1700579 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1700579 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1700062 # number of writebacks +system.cpu.icache.writebacks::total 1700062 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700580 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1700580 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1700580 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1700580 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1700580 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1700580 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344610500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22344610500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344610500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22344610500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344610500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22344610500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22344389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22344389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344389500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22344389500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles @@ -869,27 +870,27 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.413400 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.413400 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.413400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.413400 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.275718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.275718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 88597 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65011.992500 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4854150 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154024 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.515543 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 88598 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65011.992508 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4854149 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 154025 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 31.515332 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.970202 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.930460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.969504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.931167 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy @@ -904,34 +905,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40276407 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40276407 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 40276408 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40276408 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 685618 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 685618 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 685616 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 685616 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 167649 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 167649 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682585 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1682585 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513552 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 513552 # number of ReadSharedReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 167648 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 167648 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682586 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1682586 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513551 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 513551 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1682585 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 681201 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2371533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1682586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 681199 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2371532 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1682585 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 681201 # number of overall hits -system.cpu.l2cache.overall_hits::total 2371533 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1682586 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 681199 # number of overall hits +system.cpu.l2cache.overall_hits::total 2371532 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -939,8 +940,8 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128426 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128426 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 128427 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 128427 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses @@ -948,13 +949,13 @@ system.cpu.l2cache.ReadSharedReq_misses::total 12072 system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140498 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 158485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140499 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 158486 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140498 # number of overall misses -system.cpu.l2cache.overall_misses::total 158485 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140499 # number of overall misses +system.cpu.l2cache.overall_misses::total 158486 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles @@ -962,27 +963,27 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11900828000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11900828000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066597500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066597500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1519988500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1519988500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899913500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11899913500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066366000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066366000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1520063000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1520063000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2066597500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13420816500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15488748000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2066366000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13419976500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15487676500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2066597500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13420816500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15488748000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2066366000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13419976500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15487676500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 685618 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 685618 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 685616 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 685616 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses) @@ -991,19 +992,19 @@ system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700563 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1700563 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525624 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 525624 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700564 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1700564 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525623 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 525623 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1700563 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 821699 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1700564 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 821698 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1700563 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 821699 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1700564 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 821698 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses @@ -1012,8 +1013,8 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433762 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.433762 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433765 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.433765 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses @@ -1021,12 +1022,12 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170985 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170986 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170986 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency @@ -1035,30 +1036,30 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92666.812016 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92666.812016 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114951.468461 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114951.468461 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125910.246852 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125910.246852 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92658.969687 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92658.969687 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114938.591612 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114938.591612 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125916.418158 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125916.418158 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97730.056472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97722.678975 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114951.468461 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95523.185383 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97730.056472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97722.678975 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 81968 # number of writebacks -system.cpu.l2cache.writebacks::total 81968 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 81970 # number of writebacks +system.cpu.l2cache.writebacks::total 81970 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses @@ -1066,8 +1067,8 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128426 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128427 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 128427 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses @@ -1075,13 +1076,13 @@ system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140498 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 158485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140499 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 158486 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140498 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 158485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140499 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 158486 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1097,22 +1098,22 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10616568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10616568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886817500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886817500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399268500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399268500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615643500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615643500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886586000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886586000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399343000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886817500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12015836500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13903898000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886586000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12014986500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13902816500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886817500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12015836500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13903898000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886586000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12014986500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13902816500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles @@ -1126,8 +1127,8 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433762 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433762 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433765 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433765 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses @@ -1135,12 +1136,12 @@ system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency @@ -1149,22 +1150,22 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82666.812016 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82666.812016 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104951.468461 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104951.468461 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115910.246852 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115910.246852 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82658.969687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82658.969687 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104938.591612 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104938.591612 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115916.418158 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115916.418158 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104951.468461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85523.185383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87730.056472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency @@ -1172,63 +1173,64 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543364 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 222 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 222 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543358 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 227 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1700061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1700062 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700579 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700580 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525822 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587819 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::InvalidateResp 14 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587830 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7741888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663645 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7741902 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663453 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 314370693 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112662 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5336440 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2713047 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021691 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145674 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 314370629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112679 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5336568 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2713050 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021694 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2654197 97.83% 97.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 58850 2.17% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2654194 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 58856 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2713047 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970034000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2713050 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4970033000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 347377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 354876 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2559890500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2559892000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278885500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1278884000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30159 # Transaction distribution system.iobus.trans_dist::ReadResp 30159 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1279,7 +1281,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46336000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1317,28 +1319,28 @@ system.iobus.reqLayer23.occupancy 6289000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187558131 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187507137 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36400 # number of replacements -system.iocache.tags.tagsinuse 1.079865 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079862 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079865 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067492 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 1.079862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067491 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067491 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327906 # Number of tag accesses system.iocache.tags.data_accesses 327906 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses system.iocache.ReadReq_misses::total 210 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1347,14 +1349,14 @@ system.iocache.demand_misses::realview.ide 36434 # system.iocache.demand_misses::total 36434 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36434 # number of overall misses system.iocache.overall_misses::total 36434 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 34063377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 34063377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4369997754 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4369997754 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4404061131 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4404061131 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4404061131 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4404061131 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4377262761 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4377262761 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4411329137 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4411329137 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4411329137 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4411329137 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1371,14 +1373,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162206.557143 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162206.557143 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120638.188880 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120638.188880 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120877.782593 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120877.782593 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120877.782593 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120838.746715 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120838.746715 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121077.266756 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121077.266756 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -1395,14 +1397,14 @@ system.iocache.demand_mshr_misses::realview.ide 36434 system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 23563377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 23563377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2556779983 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2556779983 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2580343360 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2580343360 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2580343360 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2580343360 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564294505 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2564294505 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2587860881 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2587860881 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2587860881 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2587860881 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1411,90 +1413,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112206.557143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112206.557143 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70582.486280 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70582.486280 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70822.401054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70822.401054 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 319998 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 129556 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70789.932227 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70789.932227 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 320000 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 129537 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 496 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70429 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118158 # Transaction distribution -system.membus.trans_dist::CleanEvict 6839 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118160 # Transaction distribution +system.membus.trans_dist::CleanEvict 6838 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 128316 # Transaction distribution -system.membus.trans_dist::ReadExResp 128316 # Transaction distribution +system.membus.trans_dist::ReadExReq 128317 # Transaction distribution +system.membus.trans_dist::ReadExResp 128317 # Transaction distribution system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4315 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433109 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540701 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 613547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 613550 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583445 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583637 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17900565 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 474 # Total snoops (count) +system.membus.pkt_size::total 17900757 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4789 # Total snoops (count) system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 262688 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018375 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134305 # Request fanout histogram +system.membus.snoop_fanout::samples 262689 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018383 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134332 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 257861 98.16% 98.16% # Request fanout histogram -system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 257860 98.16% 98.16% # Request fanout histogram +system.membus.snoop_fanout::1 4829 1.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 262688 # Request fanout histogram -system.membus.reqLayer0.occupancy 90466500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 262689 # Request fanout histogram +system.membus.reqLayer0.occupancy 90467000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 822811335 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 822822299 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 948647750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 948652750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1085623 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5614930 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1526,28 +1529,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index bb1f2fc41..e575d4b01 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 125996000 # Number of ticks simulated final_tick 125996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71299 # Simulator instruction rate (inst/s) -host_op_rate 71299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7711593 # Simulator tick rate (ticks/s) -host_mem_usage 250104 # Number of bytes of host memory used -host_seconds 16.34 # Real time elapsed on the host +host_inst_rate 220398 # Simulator instruction rate (inst/s) +host_op_rate 220398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23837880 # Simulator tick rate (ticks/s) +host_mem_usage 265580 # Number of bytes of host memory used +host_seconds 5.29 # Real time elapsed on the host sim_insts 1164916 # Number of instructions simulated sim_ops 1164916 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -2880,8 +2880,8 @@ system.membus.reqLayer0.utilization 0.7 # La system.membus.respLayer1.occupancy 3778500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.0 # Layer utilization (%) system.toL2Bus.snoop_filter.tot_requests 6307 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1738 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3220 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 1711 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3247 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -2918,13 +2918,13 @@ system.toL2Bus.pkt_size::total 332608 # Cu system.toL2Bus.snoops 1024 # Total snoops (count) system.toL2Bus.snoopTraffic 53184 # Total snoop traffic (bytes) system.toL2Bus.snoop_fanout::samples 4190 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.288067 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.121770 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.302625 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.130775 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 1349 32.20% 32.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1142 27.26% 59.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 842 20.10% 79.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 857 20.45% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1111 26.52% 58.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 843 20.12% 78.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 887 21.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index fe9ceb9c1..12e1a788b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1262575 # Simulator instruction rate (inst/s) -host_op_rate 1262551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163483418 # Simulator tick rate (ticks/s) -host_mem_usage 263368 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 1154171 # Simulator instruction rate (inst/s) +host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149440007 # Simulator tick rate (ticks/s) +host_mem_usage 264052 # Number of bytes of host memory used +host_seconds 0.59 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -974,8 +974,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 799 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1011,13 +1011,13 @@ system.toL2Bus.pkt_size::total 233088 # Cu system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.218885 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 882 22.51% 60.41% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 521 13.30% 73.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index e24c67483..458816493 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 263409500 # Number of ticks simulated final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 919692 # Simulator instruction rate (inst/s) -host_op_rate 919679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 364903746 # Simulator tick rate (ticks/s) -host_mem_usage 263368 # Number of bytes of host memory used -host_seconds 0.72 # Real time elapsed on the host +host_inst_rate 870162 # Simulator instruction rate (inst/s) +host_op_rate 870149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345251596 # Simulator tick rate (ticks/s) +host_mem_usage 264052 # Number of bytes of host memory used +host_seconds 0.76 # Real time elapsed on the host sim_insts 663871 # Number of instructions simulated sim_ops 663871 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1584,8 +1584,8 @@ system.membus.reqLayer0.utilization 0.2 # La system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1097 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1878 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1621,13 +1621,13 @@ system.toL2Bus.pkt_size::total 183616 # Cu system.toL2Bus.snoops 1028 # Total snoops (count) system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.282631 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.164624 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 771 26.41% 60.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 465 15.93% 76.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 681 23.33% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram |