Update refs for tru64 with initialized cache stats

--HG--
extra : convert_revision : 708553b57307c353d6a8e403dc1ed4deb6dd2dfb

4 files changed, 23 insertions, 23 deletions

diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index fe8183125..5f05f07dd 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -189,7 +189,7 @@ bus_id=0
 type=LiveProcess
 cmd=hello
 env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 input=cin
 output=cout
 system=system
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
index 09d8f0c22..1914b47e7 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
@@ -62,7 +62,7 @@ hit_latency=1
 [system.cpu.workload]
 type=LiveProcess
 cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 input=cin
 output=cout
 env=
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index 5b851e100..ee76bf8d8 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,28 +1,28 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  39478                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 158176                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                                  57469                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   5953                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159132                       # Number of bytes of host memory used
+host_seconds                                     0.43                       # Real time elapsed on the host
+host_tick_rate                                   8713                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2578                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
 sim_ticks                                        3777                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses                416                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency            3                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits                    361                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency   160540198482307121152                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency            165                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.132212                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_miss_latency          110                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.132212                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency            3                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency            2                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   267                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency  120861284004822319104                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency            81                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.091837                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                  27                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_miss_latency           54                       # number of WriteReq MSHR miss cycles
@@ -37,10 +37,10 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses                 710                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3431725396184505344                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency            3                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits                     628                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency    281401482487129440256                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency             246                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.115493                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                    82                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
@@ -51,11 +51,11 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses                710                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3431725396184505344                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                    628                       # number of overall hits
-system.cpu.dcache.overall_miss_latency   281401482487129440256                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency            246                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.115493                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                   82                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
@@ -81,10 +81,10 @@ system.cpu.dcache.total_refs                      628                       # To
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
 system.cpu.icache.ReadReq_accesses               2579                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency            3                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   2416                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency   562005703046928072704                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency            489                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.063203                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  163                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_miss_latency          326                       # number of ReadReq MSHR miss cycles
@@ -99,10 +99,10 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                2579                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3447887748754160128                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency            3                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    2416                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency    562005703046928072704                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency             489                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.063203                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   163                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
@@ -113,11 +113,11 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               2579                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3447887748754160128                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency            3                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   2416                       # number of overall hits
-system.cpu.icache.overall_miss_latency   562005703046928072704                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency            489                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.063203                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  163                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index d4669aed9..f4d7a3959 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:48 2006
+M5 compiled Aug 21 2006 14:18:48
+M5 started Mon Aug 21 14:19:22 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
 Exiting @ tick 3777 because target called exit()